/*
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/*
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Copyright 2011, City University of Hong Kong
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Copyright 2011, City University of Hong Kong
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Author is Homer (Dongsheng) Xing.
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Author is Homer (Dongsheng) Hsing.
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This file is part of Tate Bilinear Pairing Core.
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This file is part of Tate Bilinear Pairing Core.
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Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
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Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
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Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Lesser General Public License for more details.
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public License
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You should have received a copy of the GNU Lesser General Public License
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along with Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
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along with Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
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*/
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*/
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`include "inc.v"
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`include "inc.v"
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`define ZERO {(2*`M){1'b0}}
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`define ZERO {(2*`M){1'b0}}
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`define TWO {(2*`M-2){1'b0}},2'b10
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`define TWO {(2*`M-2){1'b0}},2'b10
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// The Modified Duursma-Lee Algorithm
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// The Modified Duursma-Lee Algorithm
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// out == e_({xp,yp}, {xr,yr})
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// out == e_({xp,yp}, {xr,yr})
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module duursma_lee_algo(clk, reset, xp, yp, xr, yr, done, out);
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module duursma_lee_algo(clk, reset, xp, yp, xr, yr, done, out);
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input clk, reset;
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input clk, reset;
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input [`WIDTH:0] xp, yp, xr, yr;
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input [`WIDTH:0] xp, yp, xr, yr;
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output reg done;
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output reg done;
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output reg [`W6:0] out;
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output reg [`W6:0] out;
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reg [`W6:0] t;
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reg [`W6:0] t;
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reg [`WIDTH:0] a, b, y;
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reg [`WIDTH:0] a, b, y;
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reg [1:0] d;
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reg [1:0] d;
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reg [`M:0] i;
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reg [`M:0] i;
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reg f3m_reset, delay1, delay2;
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reg f3m_reset, delay1, delay2;
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wire [`W6:0] g,v7,v8;
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wire [`W6:0] g,v7,v8;
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wire [`WIDTH:0] mu /* my name is "mew" */,nmu,ny,
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wire [`WIDTH:0] mu /* my name is "mew" */,nmu,ny,
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x,v2,v3,v4,v5,v6;
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x,v2,v3,v4,v5,v6;
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wire [1:0] v9;
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wire [1:0] v9;
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wire f36m_reset, dummy, f3m_done, f36m_done, finish, change;
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wire f36m_reset, dummy, f3m_done, f36m_done, finish, change;
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assign g = {`ZERO,`TWO,`ZERO,nmu,v6,v5};
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assign g = {`ZERO,`TWO,`ZERO,nmu,v6,v5};
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assign finish = i[0];
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assign finish = i[0];
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f3m_cubic
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f3m_cubic
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ins1 (xr, x), // x == {x_r}^3
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ins1 (xr, x), // x == {x_r}^3
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ins2 (yr, v2); // v2 == {y_r}^3
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ins2 (yr, v2); // v2 == {y_r}^3
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f3m_nine
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f3m_nine
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ins3 (clk, a, v3), // v3 == a^9
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ins3 (clk, a, v3), // v3 == a^9
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ins4 (clk, b, v4); // v4 == b^9
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ins4 (clk, b, v4); // v4 == b^9
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f3m_add3
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f3m_add3
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ins5 (v3, x, {{(2*`M-2){1'b0}},d}, mu); // mu == a^9+x+d
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ins5 (v3, x, {{(2*`M-2){1'b0}},d}, mu); // mu == a^9+x+d
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f3m_neg
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f3m_neg
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ins6 (mu, nmu), // nmu == -mu
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ins6 (mu, nmu), // nmu == -mu
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ins7 (y, ny); // ny == -y
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ins7 (y, ny); // ny == -y
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f3m_mult
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f3m_mult
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ins8 (clk, delay2, mu, nmu, v5, f3m_done), // v5 == - mu^2
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ins8 (clk, delay2, mu, nmu, v5, f3m_done), // v5 == - mu^2
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ins9 (clk, delay2, v4, ny, v6, dummy); // v6 == - (b^9)*y
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ins9 (clk, delay2, v4, ny, v6, dummy); // v6 == - (b^9)*y
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f36m_cubic
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f36m_cubic
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ins10 (clk, t, v7); // v7 == t^3
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ins10 (clk, t, v7); // v7 == t^3
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f36m_mult
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f36m_mult
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ins11 (clk, f36m_reset, v7, g, v8, f36m_done); // v8 == v7*g = (t^3)*g
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ins11 (clk, f36m_reset, v7, g, v8, f36m_done); // v8 == v7*g = (t^3)*g
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func6
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func6
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ins12 (clk, reset, f36m_done, change),
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ins12 (clk, reset, f36m_done, change),
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ins13 (clk, reset, f3m_done, f36m_reset);
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ins13 (clk, reset, f3m_done, f36m_reset);
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f3_sub1
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f3_sub1
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ins14 (d, v9); // v9 == d-1
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ins14 (d, v9); // v9 == d-1
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset)
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if (reset)
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i <= {1'b1, {`M{1'b0}}};
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i <= {1'b1, {`M{1'b0}}};
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else if (change | i[0])
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else if (change | i[0])
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i <= i >> 1;
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i <= i >> 1;
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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a <= xp; b <= yp; t <= 1;
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a <= xp; b <= yp; t <= 1;
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y <= v2; d <= 1;
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y <= v2; d <= 1;
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end
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end
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else if (change)
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else if (change)
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begin
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begin
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a <= v3; b <= v4; t <= v8;
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a <= v3; b <= v4; t <= v8;
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y <= ny; d <= v9;
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y <= ny; d <= v9;
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end
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end
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset)
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if (reset)
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begin done <= 0; end
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begin done <= 0; end
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else if (finish)
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else if (finish)
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begin done <= 1; out <= v8; end
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begin done <= 1; out <= v8; end
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset)
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if (reset)
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begin delay1 <= 1; delay2 <= 1; end
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begin delay1 <= 1; delay2 <= 1; end
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else
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else
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begin delay2 <= delay1; delay1 <= f3m_reset; end
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begin delay2 <= delay1; delay1 <= f3m_reset; end
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) f3m_reset <= 1;
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if (reset) f3m_reset <= 1;
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else if (change) f3m_reset <= 1;
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else if (change) f3m_reset <= 1;
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else f3m_reset <= 0;
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else f3m_reset <= 0;
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endmodule
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endmodule
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// do Tate pairing, hahahaha
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// do Tate pairing, hahahaha
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module tate_pairing(clk, reset, x1, y1, x2, y2, done, out);
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module tate_pairing(clk, reset, x1, y1, x2, y2, done, out);
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input clk, reset;
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input clk, reset;
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input [`WIDTH:0] x1, y1, x2, y2;
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input [`WIDTH:0] x1, y1, x2, y2;
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output reg done;
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output reg done;
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output reg [`W6:0] out;
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output reg [`W6:0] out;
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reg delay1, rst1;
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reg delay1, rst1;
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wire done1, rst2, done2;
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wire done1, rst2, done2;
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wire [`W6:0] out1, out2;
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wire [`W6:0] out1, out2;
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reg [2:0] K;
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reg [2:0] K;
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duursma_lee_algo
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duursma_lee_algo
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ins1 (clk, rst1, x1, y1, x2, y2, done1, out1);
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ins1 (clk, rst1, x1, y1, x2, y2, done1, out1);
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second_part
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second_part
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ins2 (clk, rst2, out1, out2, done2);
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ins2 (clk, rst2, out1, out2, done2);
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func6
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func6
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ins3 (clk, reset, done1, rst2);
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ins3 (clk, reset, done1, rst2);
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset)
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if (reset)
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begin
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begin
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rst1 <= 1; delay1 <= 1;
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rst1 <= 1; delay1 <= 1;
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end
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end
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else
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else
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begin
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begin
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rst1 <= delay1; delay1 <= reset;
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rst1 <= delay1; delay1 <= reset;
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) K <= 3'b100;
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if (reset) K <= 3'b100;
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else if ((K[2]&rst2)|(K[1]&done2)|K[0])
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else if ((K[2]&rst2)|(K[1]&done2)|K[0])
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K <= K >> 1;
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K <= K >> 1;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) done <= 0;
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if (reset) done <= 0;
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else if (K[0]) begin done <= 1; out <= out2; end
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else if (K[0]) begin done <= 1; out <= out2; end
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endmodule
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endmodule
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