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[/] [pairing/] [trunk/] [testbench/] [test_post_route.v] - Diff between revs 20 and 22
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| Rev 20 |
Rev 22 |
`timescale 1ns / 1ns
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`timescale 1ns / 1ns
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`include "../rtl/inc.v"
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`include "../rtl/inc.v"
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/* purpose of this module is ISE post-route simulation */
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/* purpose of this module is ISE post-route simulation */
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/* if you don't use Xilinx ISE, please ignore this file :) */
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/* if you don't use Xilinx ISE, please ignore this file :) */
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module test_post_route;
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module test_post_route;
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// Inputs
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// Inputs
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reg clk;
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reg clk;
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reg reset;
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reg reset;
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reg [`WIDTH:0] x1, y1, x2, y2;
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reg [`WIDTH:0] x1, y1, x2, y2;
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// Outputs
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// Outputs
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wire done, ok;
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wire done, ok;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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post_route_debug uut (
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post_route_debug uut (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.x1(x1),
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.x1(x1),
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.y1(y1),
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.y1(y1),
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.x2(x2),
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.x2(x2),
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.y2(y2),
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.y2(y2),
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.done(done),
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.done(done),
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.ok(ok)
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.ok(ok)
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);
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);
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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clk = 0;
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clk = 0;
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reset = 0;
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reset = 0;
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x1 = 0;
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x1 = 0;
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y1 = 0;
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y1 = 0;
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x2 = 0;
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x2 = 0;
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y2 = 0;
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y2 = 0;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#100;
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#100;
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// Add stimulus here
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// Add stimulus here
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x1 = 194'h6a18950064046a122a14118668466a262a91509688159890;
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x1 = 194'h6a18950064046a122a14118668466a262a91509688159890;
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y1 = 194'h69112569422aa0a25224aa010888066061124a8685566825;
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y1 = 194'h69112569422aa0a25224aa010888066061124a8685566825;
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x2 = 194'h155945aa8924654812564110544995a28845901211454814;
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x2 = 194'h155945aa8924654812564110544995a28845901211454814;
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y2 = 194'h8481099460280628960a82559920000a99a2106955289a40;
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y2 = 194'h8481099460280628960a82559920000a99a2106955289a40;
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@ (negedge clk); reset = 1;
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@ (negedge clk); reset = 1;
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@ (negedge clk); reset = 0;
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@ (negedge clk); reset = 0;
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@ (posedge done); @ (negedge clk);
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@ (posedge done); @ (negedge clk);
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if (ok !== 1'b1) $display("E");
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if (ok !== 1'b1) $display("E");
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$finish;
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$finish;
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end
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end
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always #5 clk = ~clk;
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always #5 clk = ~clk;
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endmodule
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endmodule
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