-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
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--
|
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
|
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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--
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--
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-- This file contains confidential and proprietary information
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- international copyright and other intellectual property
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-- laws.
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-- laws.
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--
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--
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-- DISCLAIMER
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- CRITICAL APPLICATIONS
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--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Project : Series-7 Integrated Block for PCI Express
|
-- Project : Series-7 Integrated Block for PCI Express
|
-- File : cl_a7pcie_x4_pcie_brams_7x.vhd
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-- File : cl_a7pcie_x4_pcie_brams_7x.vhd
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-- Version : 1.10
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-- Version : 1.11
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-- Description : pcie bram wrapper
|
-- Description : pcie bram wrapper
|
-- arrange and connect brams
|
-- arrange and connect brams
|
-- implement address decoding, datapath muxing and pipeline stages
|
-- implement address decoding, datapath muxing and pipeline stages
|
--
|
--
|
-- banks of brams are used for 1,2,4,8,18 brams
|
-- banks of brams are used for 1,2,4,8,18 brams
|
-- brams are stacked for other values of NUM_BRAMS
|
-- brams are stacked for other values of NUM_BRAMS
|
--
|
--
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
|
use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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|
|
entity cl_a7pcie_x4_pcie_brams_7x is
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entity cl_a7pcie_x4_pcie_brams_7x is
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generic(
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generic(
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LINK_CAP_MAX_LINK_SPEED : integer := 1; -- PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
|
LINK_CAP_MAX_LINK_SPEED : integer := 1; -- PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
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LINK_CAP_MAX_LINK_WIDTH : integer := 8; -- PCIe Link Width : 1 / 2 / 4 / 8
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LINK_CAP_MAX_LINK_WIDTH : integer := 8; -- PCIe Link Width : 1 / 2 / 4 / 8
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IMPL_TARGET : string := "HARD"; -- the implementation target : HARD, SOFT
|
IMPL_TARGET : string := "HARD"; -- the implementation target : HARD, SOFT
|
|
|
-- the number of BRAMs to use
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-- the number of BRAMs to use
|
-- supported values are:
|
-- supported values are:
|
-- 1,2,4,8,18
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-- 1,2,4,8,18
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NUM_BRAMS : integer := 0;
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NUM_BRAMS : integer := 0;
|
|
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-- BRAM read address latency
|
-- BRAM read address latency
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--
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--
|
-- value meaning
|
-- value meaning
|
-- ==========================
|
-- ==========================
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-- 0 BRAM read address port sample
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-- 0 BRAM read address port sample
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-- 1 BRAM read address port sample and a pipeline stage on the address port
|
-- 1 BRAM read address port sample and a pipeline stage on the address port
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RAM_RADDR_LATENCY : integer := 1;
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RAM_RADDR_LATENCY : integer := 1;
|
|
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-- BRAM read data latency
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-- BRAM read data latency
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--
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--
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-- value meaning
|
-- value meaning
|
-- ==========================
|
-- ==========================
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-- 1 no BRAM OREG
|
-- 1 no BRAM OREG
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-- 2 use BRAM OREG
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-- 2 use BRAM OREG
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-- 3 use BRAM OREG and a pipeline stage on the data port
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-- 3 use BRAM OREG and a pipeline stage on the data port
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RAM_RDATA_LATENCY :integer := 1;
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RAM_RDATA_LATENCY :integer := 1;
|
|
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-- BRAM write latency
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-- BRAM write latency
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-- The BRAM write port is synchronous
|
-- The BRAM write port is synchronous
|
--
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--
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-- value meaning
|
-- value meaning
|
-- ==========================
|
-- ==========================
|
-- 0 BRAM write port sample
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-- 0 BRAM write port sample
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-- 1 BRAM write port sample plus pipeline stage
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-- 1 BRAM write port sample plus pipeline stage
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RAM_WRITE_LATENCY :integer := 1
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RAM_WRITE_LATENCY :integer := 1
|
);
|
);
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port (
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port (
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user_clk_i : in std_logic; -- user clock
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user_clk_i : in std_logic; -- user clock
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reset_i : in std_logic; -- bram reset
|
reset_i : in std_logic; -- bram reset
|
wen : in std_logic; -- write enable
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wen : in std_logic; -- write enable
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waddr : in std_logic_vector(12 downto 0); -- write address
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waddr : in std_logic_vector(12 downto 0); -- write address
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wdata : in std_logic_vector(71 downto 0); -- write data
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wdata : in std_logic_vector(71 downto 0); -- write data
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ren : in std_logic; -- read enable
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ren : in std_logic; -- read enable
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rce : in std_logic; -- output register clock enable
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rce : in std_logic; -- output register clock enable
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raddr : in std_logic_vector(12 downto 0); -- read address
|
raddr : in std_logic_vector(12 downto 0); -- read address
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rdata : out std_logic_vector(71 downto 0) -- read data
|
rdata : out std_logic_vector(71 downto 0) -- read data
|
);
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);
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end cl_a7pcie_x4_pcie_brams_7x;
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end cl_a7pcie_x4_pcie_brams_7x;
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|
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architecture pcie_7x of cl_a7pcie_x4_pcie_brams_7x is
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architecture pcie_7x of cl_a7pcie_x4_pcie_brams_7x is
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component cl_a7pcie_x4_pcie_bram_7x is
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component cl_a7pcie_x4_pcie_bram_7x is
|
generic (
|
generic (
|
LINK_CAP_MAX_LINK_SPEED : INTEGER := 1; -- PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
|
LINK_CAP_MAX_LINK_SPEED : INTEGER := 1; -- PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
|
LINK_CAP_MAX_LINK_WIDTH : INTEGER := 8; -- PCIe Link Width : 1 / 2 / 4 / 8
|
LINK_CAP_MAX_LINK_WIDTH : INTEGER := 8; -- PCIe Link Width : 1 / 2 / 4 / 8
|
IMPL_TARGET : STRING := "HARD"; -- the implementation target : HARD, SOFT
|
IMPL_TARGET : STRING := "HARD"; -- the implementation target : HARD, SOFT
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DOB_REG : INTEGER := 0; -- 1 - use the output register;
|
DOB_REG : INTEGER := 0; -- 1 - use the output register;
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-- 0 - don't use the output register
|
-- 0 - don't use the output register
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WIDTH : INTEGER := 0 -- supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
|
WIDTH : INTEGER := 0 -- supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
|
-- 72 - uses RAMB36SDP
|
-- 72 - uses RAMB36SDP
|
);
|
);
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port (
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port (
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user_clk_i : in std_logic; -- user clock
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user_clk_i : in std_logic; -- user clock
|
reset_i : in std_logic; -- bram reset
|
reset_i : in std_logic; -- bram reset
|
wen_i : in std_logic; -- write enable
|
wen_i : in std_logic; -- write enable
|
waddr_i : in std_logic_vector(12 downto 0); -- write address
|
waddr_i : in std_logic_vector(12 downto 0); -- write address
|
wdata_i : in std_logic_vector(WIDTH - 1 downto 0); -- write data
|
wdata_i : in std_logic_vector(WIDTH - 1 downto 0); -- write data
|
ren_i : in std_logic; -- read enable
|
ren_i : in std_logic; -- read enable
|
rce_i : in std_logic; -- output register clock enable
|
rce_i : in std_logic; -- output register clock enable
|
raddr_i : in std_logic_vector(12 downto 0); -- read address
|
raddr_i : in std_logic_vector(12 downto 0); -- read address
|
rdata_o : out std_logic_vector(WIDTH - 1 downto 0) -- read data
|
rdata_o : out std_logic_vector(WIDTH - 1 downto 0) -- read data
|
);
|
);
|
end component;
|
end component;
|
|
|
function get_dob_reg (
|
function get_dob_reg (
|
constant rdata_lat : integer)
|
constant rdata_lat : integer)
|
return integer is
|
return integer is
|
begin -- get_dob_reg
|
begin -- get_dob_reg
|
if (rdata_lat > 1) then
|
if (rdata_lat > 1) then
|
return 1;
|
return 1;
|
else
|
else
|
return 0;
|
return 0;
|
end if;
|
end if;
|
end get_dob_reg;
|
end get_dob_reg;
|
|
|
function get_width (
|
function get_width (
|
constant num_brams : integer)
|
constant num_brams : integer)
|
return integer is
|
return integer is
|
begin -- msb_d
|
begin -- msb_d
|
|
|
if (num_brams = 1) then
|
if (num_brams = 1) then
|
return 72;
|
return 72;
|
elsif (num_brams = 2) then
|
elsif (num_brams = 2) then
|
return 36;
|
return 36;
|
elsif (num_brams = 4) then
|
elsif (num_brams = 4) then
|
return 18;
|
return 18;
|
elsif (num_brams = 8) then
|
elsif (num_brams = 8) then
|
return 9;
|
return 9;
|
else
|
else
|
return 4;
|
return 4;
|
end if;
|
end if;
|
end get_width;
|
end get_width;
|
|
|
constant DOB_REG : integer := get_dob_reg(RAM_RDATA_LATENCY);
|
constant DOB_REG : integer := get_dob_reg(RAM_RDATA_LATENCY);
|
constant WIDTH : integer := get_width(NUM_BRAMS);
|
constant WIDTH : integer := get_width(NUM_BRAMS);
|
constant TCQ : integer := 1;
|
constant TCQ : integer := 1;
|
|
|
signal wen_int : std_logic;
|
signal wen_int : std_logic;
|
signal waddr_int : std_logic_vector(12 downto 0);
|
signal waddr_int : std_logic_vector(12 downto 0);
|
signal wdata_int : std_logic_vector(71 downto 0);
|
signal wdata_int : std_logic_vector(71 downto 0);
|
|
|
signal wen_q : std_logic := '0';
|
signal wen_q : std_logic := '0';
|
signal waddr_q : std_logic_vector(12 downto 0) := (others => '0');
|
signal waddr_q : std_logic_vector(12 downto 0) := (others => '0');
|
signal wdata_q : std_logic_vector(71 downto 0) := (others => '0');
|
signal wdata_q : std_logic_vector(71 downto 0) := (others => '0');
|
|
|
signal ren_int : std_logic;
|
signal ren_int : std_logic;
|
signal raddr_int : std_logic_vector(12 downto 0);
|
signal raddr_int : std_logic_vector(12 downto 0);
|
signal rdata_int : std_logic_vector(71 downto 0);
|
signal rdata_int : std_logic_vector(71 downto 0);
|
|
|
signal ren_q : std_logic := '0';
|
signal ren_q : std_logic := '0';
|
signal raddr_q : std_logic_vector(12 downto 0) := (others => '0');
|
signal raddr_q : std_logic_vector(12 downto 0) := (others => '0');
|
signal rdata_q : std_logic_vector(71 downto 0) := (others => '0');
|
signal rdata_q : std_logic_vector(71 downto 0) := (others => '0');
|
|
|
begin
|
begin
|
|
|
--synthesis translate_off
|
--synthesis translate_off
|
process
|
process
|
begin
|
begin
|
-- $display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
|
-- $display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
|
-- now, to_stdlogic(NUM_BRAMS), to_stdlogicvector(DOB_REG, 13),
|
-- now, to_stdlogic(NUM_BRAMS), to_stdlogicvector(DOB_REG, 13),
|
-- ("00000000000000000000000000000000000000000000000000000000000000000" & WIDTH), to_stdlogic(RAM_WRITE_LATENCY),
|
-- ("00000000000000000000000000000000000000000000000000000000000000000" & WIDTH), to_stdlogic(RAM_WRITE_LATENCY),
|
-- to_stdlogic(RAM_RADDR_LATENCY), to_stdlogicvector(RAM_RDATA_LATENCY, 13));
|
-- to_stdlogic(RAM_RADDR_LATENCY), to_stdlogicvector(RAM_RDATA_LATENCY, 13));
|
case NUM_BRAMS is
|
case NUM_BRAMS is
|
when 1 | 2 | 4 | 8 | 18 =>
|
when 1 | 2 | 4 | 8 | 18 =>
|
when others =>
|
when others =>
|
-- $display("[%t] %m Error NUM_BRAMS %0d not supported", now, to_stdlogic(NUM_BRAMS));
|
-- $display("[%t] %m Error NUM_BRAMS %0d not supported", now, to_stdlogic(NUM_BRAMS));
|
-- $finish();
|
-- $finish();
|
end case; -- case(NUM_BRAMS)
|
end case; -- case(NUM_BRAMS)
|
case RAM_RADDR_LATENCY is
|
case RAM_RADDR_LATENCY is
|
when 0 | 1 =>
|
when 0 | 1 =>
|
when others =>
|
when others =>
|
-- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", now, to_stdlogic(RAM_RADDR_LATENCY));
|
-- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", now, to_stdlogic(RAM_RADDR_LATENCY));
|
-- $finish();
|
-- $finish();
|
end case; -- case (RAM_RADDR_LATENCY)
|
end case; -- case (RAM_RADDR_LATENCY)
|
case RAM_RDATA_LATENCY is
|
case RAM_RDATA_LATENCY is
|
when 1 | 2 | 3 =>
|
when 1 | 2 | 3 =>
|
when others =>
|
when others =>
|
-- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", now, to_stdlogic(RAM_RDATA_LATENCY));
|
-- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", now, to_stdlogic(RAM_RDATA_LATENCY));
|
-- $finish();
|
-- $finish();
|
end case; -- case (RAM_RDATA_LATENCY)
|
end case; -- case (RAM_RDATA_LATENCY)
|
case RAM_WRITE_LATENCY is
|
case RAM_WRITE_LATENCY is
|
when 0 | 1 =>
|
when 0 | 1 =>
|
when others =>
|
when others =>
|
-- $display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", now, to_stdlogic(RAM_WRITE_LATENCY));
|
-- $display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", now, to_stdlogic(RAM_WRITE_LATENCY));
|
-- $finish();
|
-- $finish();
|
end case; -- case(RAM_WRITE_LATENCY)
|
end case; -- case(RAM_WRITE_LATENCY)
|
wait;
|
wait;
|
end process;
|
end process;
|
--synthesis translate_on
|
--synthesis translate_on
|
|
|
-- model the delays for ram write latency
|
-- model the delays for ram write latency
|
wr_lat_2 : if (RAM_WRITE_LATENCY = 1) generate
|
wr_lat_2 : if (RAM_WRITE_LATENCY = 1) generate
|
process (user_clk_i)
|
process (user_clk_i)
|
begin
|
begin
|
if (user_clk_i'event and user_clk_i = '1') then
|
if (user_clk_i'event and user_clk_i = '1') then
|
if (reset_i = '1') then
|
if (reset_i = '1') then
|
wen_q <= '0' after (TCQ)*1 ps;
|
wen_q <= '0' after (TCQ)*1 ps;
|
waddr_q <= "0000000000000" after (TCQ)*1 ps;
|
waddr_q <= "0000000000000" after (TCQ)*1 ps;
|
wdata_q <= "000000000000000000000000000000000000000000000000000000000000000000000000" after (TCQ)*1 ps;
|
wdata_q <= "000000000000000000000000000000000000000000000000000000000000000000000000" after (TCQ)*1 ps;
|
else
|
else
|
wen_q <= wen after (TCQ)*1 ps;
|
wen_q <= wen after (TCQ)*1 ps;
|
waddr_q <= waddr after (TCQ)*1 ps;
|
waddr_q <= waddr after (TCQ)*1 ps;
|
wdata_q <= wdata after (TCQ)*1 ps;
|
wdata_q <= wdata after (TCQ)*1 ps;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
wen_int <= wen_q;
|
wen_int <= wen_q;
|
waddr_int <= waddr_q;
|
waddr_int <= waddr_q;
|
wdata_int <= wdata_q;
|
wdata_int <= wdata_q;
|
end generate;
|
end generate;
|
|
|
wr_lat_1 : if (RAM_WRITE_LATENCY = 0) generate
|
wr_lat_1 : if (RAM_WRITE_LATENCY = 0) generate
|
wen_int <= wen;
|
wen_int <= wen;
|
waddr_int <= waddr;
|
waddr_int <= waddr;
|
wdata_int <= wdata;
|
wdata_int <= wdata;
|
end generate;
|
end generate;
|
|
|
raddr_lat_2 : if (RAM_RADDR_LATENCY = 1) generate
|
raddr_lat_2 : if (RAM_RADDR_LATENCY = 1) generate
|
|
|
process (user_clk_i)
|
process (user_clk_i)
|
begin
|
begin
|
if (user_clk_i'event and user_clk_i = '1') then
|
if (user_clk_i'event and user_clk_i = '1') then
|
if (reset_i = '1') then
|
if (reset_i = '1') then
|
ren_q <= '0' after (TCQ)*1 ps;
|
ren_q <= '0' after (TCQ)*1 ps;
|
raddr_q <= "0000000000000" after (TCQ)*1 ps;
|
raddr_q <= "0000000000000" after (TCQ)*1 ps;
|
else
|
else
|
ren_q <= ren after (TCQ)*1 ps;
|
ren_q <= ren after (TCQ)*1 ps;
|
raddr_q <= raddr after (TCQ)*1 ps;
|
raddr_q <= raddr after (TCQ)*1 ps;
|
end if; -- else: !if(reset_i)
|
end if; -- else: !if(reset_i)
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
ren_int <= ren_q;
|
ren_int <= ren_q;
|
raddr_int <= raddr_q;
|
raddr_int <= raddr_q;
|
|
|
end generate; -- block: rd_lat_addr_2
|
end generate; -- block: rd_lat_addr_2
|
|
|
raddr_lat_1 : if (not(RAM_RADDR_LATENCY = 1)) generate
|
raddr_lat_1 : if (not(RAM_RADDR_LATENCY = 1)) generate
|
ren_int <= ren;
|
ren_int <= ren;
|
raddr_int <= raddr;
|
raddr_int <= raddr;
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end generate;
|
end generate;
|
|
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rdata_lat_3 : if (RAM_RDATA_LATENCY = 3) generate
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rdata_lat_3 : if (RAM_RDATA_LATENCY = 3) generate
|
|
|
process (user_clk_i)
|
process (user_clk_i)
|
begin
|
begin
|
if (user_clk_i'event and user_clk_i = '1') then
|
if (user_clk_i'event and user_clk_i = '1') then
|
if (reset_i = '1') then
|
if (reset_i = '1') then
|
rdata_q <= "000000000000000000000000000000000000000000000000000000000000000000000000" after (TCQ)*1 ps;
|
rdata_q <= "000000000000000000000000000000000000000000000000000000000000000000000000" after (TCQ)*1 ps;
|
else
|
else
|
rdata_q <= rdata_int after (TCQ)*1 ps;
|
rdata_q <= rdata_int after (TCQ)*1 ps;
|
end if; -- else: !if(reset_i)
|
end if; -- else: !if(reset_i)
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
rdata <= rdata_q;
|
rdata <= rdata_q;
|
|
|
end generate; -- block: rd_lat_data_3
|
end generate; -- block: rd_lat_data_3
|
|
|
rdata_lat_1_2 : if (not(RAM_RDATA_LATENCY = 3)) generate
|
rdata_lat_1_2 : if (not(RAM_RDATA_LATENCY = 3)) generate
|
rdata <= rdata_int after (TCQ)*1 ps;
|
rdata <= rdata_int after (TCQ)*1 ps;
|
end generate;
|
end generate;
|
|
|
-- instantiate the brams
|
-- instantiate the brams
|
brams : for ii in 0 to NUM_BRAMS - 1 generate
|
brams : for ii in 0 to NUM_BRAMS - 1 generate
|
|
|
ram : cl_a7pcie_x4_pcie_bram_7x
|
ram : cl_a7pcie_x4_pcie_bram_7x
|
generic map (
|
generic map (
|
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH,
|
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH,
|
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
|
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED,
|
IMPL_TARGET => IMPL_TARGET,
|
IMPL_TARGET => IMPL_TARGET,
|
DOB_REG => DOB_REG,
|
DOB_REG => DOB_REG,
|
WIDTH => WIDTH
|
WIDTH => WIDTH
|
)
|
)
|
port map (
|
port map (
|
user_clk_i => user_clk_i,
|
user_clk_i => user_clk_i,
|
reset_i => reset_i,
|
reset_i => reset_i,
|
wen_i => wen_int,
|
wen_i => wen_int,
|
waddr_i => waddr_int,
|
waddr_i => waddr_int,
|
wdata_i => wdata_int(((ii+1)*WIDTH-1) downto (ii * WIDTH)),
|
wdata_i => wdata_int(((ii+1)*WIDTH-1) downto (ii * WIDTH)),
|
ren_i => ren_int,
|
ren_i => ren_int,
|
raddr_i => raddr_int,
|
raddr_i => raddr_int,
|
rdata_o => rdata_int(((ii+1)*WIDTH-1) downto (ii * WIDTH)),
|
rdata_o => rdata_int(((ii+1)*WIDTH-1) downto (ii * WIDTH)),
|
rce_i => rce
|
rce_i => rce
|
);
|
);
|
end generate;
|
end generate;
|
-- pcie_brams_7x
|
-- pcie_brams_7x
|
end pcie_7x;
|
end pcie_7x;
|
|
|
|
|
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