-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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--
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--
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-- This file contains confidential and proprietary information
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- international copyright and other intellectual property
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-- laws.
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-- laws.
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--
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--
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-- DISCLAIMER
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Project : Series-7 Integrated Block for PCI Express
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-- Project : Series-7 Integrated Block for PCI Express
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-- File : cl_a7pcie_x4_pcie_pipe_misc.vhd
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-- File : cl_a7pcie_x4_pcie_pipe_misc.vhd
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-- Version : 1.10
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-- Version : 1.11
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-- Description: Misc PIPE module for 7-SeriesPCIe Block
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-- Description: Misc PIPE module for 7-SeriesPCIe Block
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--
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--
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--
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--
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity cl_a7pcie_x4_pcie_pipe_misc is
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entity cl_a7pcie_x4_pcie_pipe_misc is
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generic (
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generic (
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PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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);
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);
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port (
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port (
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pipe_tx_rcvr_det_i : in std_logic; -- PIPE Tx Receiver Detect
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pipe_tx_rcvr_det_i : in std_logic; -- PIPE Tx Receiver Detect
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pipe_tx_reset_i : in std_logic; -- PIPE Tx Reset
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pipe_tx_reset_i : in std_logic; -- PIPE Tx Reset
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pipe_tx_rate_i : in std_logic; -- PIPE Tx Rate
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pipe_tx_rate_i : in std_logic; -- PIPE Tx Rate
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pipe_tx_deemph_i : in std_logic; -- PIPE Tx Deemphasis
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pipe_tx_deemph_i : in std_logic; -- PIPE Tx Deemphasis
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pipe_tx_margin_i : in std_logic_vector(2 downto 0); -- PIPE Tx Margin
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pipe_tx_margin_i : in std_logic_vector(2 downto 0); -- PIPE Tx Margin
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pipe_tx_swing_i : in std_logic; -- PIPE Tx Swing
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pipe_tx_swing_i : in std_logic; -- PIPE Tx Swing
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pipe_tx_rcvr_det_o : out std_logic; -- Pipelined PIPE Tx Receiver Detect
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pipe_tx_rcvr_det_o : out std_logic; -- Pipelined PIPE Tx Receiver Detect
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pipe_tx_reset_o : out std_logic; -- Pipelined PIPE Tx Reset
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pipe_tx_reset_o : out std_logic; -- Pipelined PIPE Tx Reset
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pipe_tx_rate_o : out std_logic; -- Pipelined PIPE Tx Rate
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pipe_tx_rate_o : out std_logic; -- Pipelined PIPE Tx Rate
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pipe_tx_deemph_o : out std_logic; -- Pipelined PIPE Tx Deemphasis
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pipe_tx_deemph_o : out std_logic; -- Pipelined PIPE Tx Deemphasis
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pipe_tx_margin_o : out std_logic_vector(2 downto 0); -- Pipelined PIPE Tx Margin
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pipe_tx_margin_o : out std_logic_vector(2 downto 0); -- Pipelined PIPE Tx Margin
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pipe_tx_swing_o : out std_logic; -- Pipelined PIPE Tx Swing
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pipe_tx_swing_o : out std_logic; -- Pipelined PIPE Tx Swing
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pipe_clk : in std_logic; -- PIPE Clock
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pipe_clk : in std_logic; -- PIPE Clock
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rst_n : in std_logic -- Reset
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rst_n : in std_logic -- Reset
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);
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);
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end cl_a7pcie_x4_pcie_pipe_misc;
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end cl_a7pcie_x4_pcie_pipe_misc;
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architecture rtl of cl_a7pcie_x4_pcie_pipe_misc is
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architecture rtl of cl_a7pcie_x4_pcie_pipe_misc is
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--******************************************************************//
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--******************************************************************//
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-- Reality check. //
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-- Reality check. //
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--******************************************************************//
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--******************************************************************//
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constant TCQ : integer := 1; -- clock to out delay model
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constant TCQ : integer := 1; -- clock to out delay model
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signal pipe_tx_rcvr_det_q : std_logic;
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signal pipe_tx_rcvr_det_q : std_logic;
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signal pipe_tx_reset_q : std_logic;
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signal pipe_tx_reset_q : std_logic;
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signal pipe_tx_rate_q : std_logic;
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signal pipe_tx_rate_q : std_logic;
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signal pipe_tx_deemph_q : std_logic;
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signal pipe_tx_deemph_q : std_logic;
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signal pipe_tx_margin_q : std_logic_vector(2 downto 0);
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signal pipe_tx_margin_q : std_logic_vector(2 downto 0);
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signal pipe_tx_swing_q : std_logic;
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signal pipe_tx_swing_q : std_logic;
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signal pipe_tx_rcvr_det_qq : std_logic;
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signal pipe_tx_rcvr_det_qq : std_logic;
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signal pipe_tx_reset_qq : std_logic;
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signal pipe_tx_reset_qq : std_logic;
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signal pipe_tx_rate_qq : std_logic;
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signal pipe_tx_rate_qq : std_logic;
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signal pipe_tx_deemph_qq : std_logic;
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signal pipe_tx_deemph_qq : std_logic;
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signal pipe_tx_margin_qq : std_logic_vector(2 downto 0);
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signal pipe_tx_margin_qq : std_logic_vector(2 downto 0);
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signal pipe_tx_swing_qq : std_logic;
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signal pipe_tx_swing_qq : std_logic;
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begin
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begin
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pipe_stages_0 : if (PIPE_PIPELINE_STAGES = 0) generate
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pipe_stages_0 : if (PIPE_PIPELINE_STAGES = 0) generate
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pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_i;
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pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_i;
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pipe_tx_reset_o <= pipe_tx_reset_i;
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pipe_tx_reset_o <= pipe_tx_reset_i;
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pipe_tx_rate_o <= pipe_tx_rate_i;
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pipe_tx_rate_o <= pipe_tx_rate_i;
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pipe_tx_deemph_o <= pipe_tx_deemph_i;
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pipe_tx_deemph_o <= pipe_tx_deemph_i;
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pipe_tx_margin_o <= pipe_tx_margin_i;
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pipe_tx_margin_o <= pipe_tx_margin_i;
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pipe_tx_swing_o <= pipe_tx_swing_i;
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pipe_tx_swing_o <= pipe_tx_swing_i;
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end generate; -- pipe_stages_0
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end generate; -- pipe_stages_0
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pipe_stages_1 : if (PIPE_PIPELINE_STAGES = 1) generate
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pipe_stages_1 : if (PIPE_PIPELINE_STAGES = 1) generate
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process (pipe_clk)
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process (pipe_clk)
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begin
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begin
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if (pipe_clk'event and pipe_clk = '1') then
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if (pipe_clk'event and pipe_clk = '1') then
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if (rst_n = '1') then
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if (rst_n = '1') then
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pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps;
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pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps;
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pipe_tx_reset_q <= '1' after (TCQ)*1 ps;
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pipe_tx_reset_q <= '1' after (TCQ)*1 ps;
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pipe_tx_rate_q <= '0' after (TCQ)*1 ps;
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pipe_tx_rate_q <= '0' after (TCQ)*1 ps;
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pipe_tx_deemph_q <= '1' after (TCQ)*1 ps;
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pipe_tx_deemph_q <= '1' after (TCQ)*1 ps;
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pipe_tx_margin_q <= "000" after (TCQ)*1 ps;
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pipe_tx_margin_q <= "000" after (TCQ)*1 ps;
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pipe_tx_swing_q <= '0' after (TCQ)*1 ps;
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pipe_tx_swing_q <= '0' after (TCQ)*1 ps;
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else
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else
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pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps;
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pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps;
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pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps;
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pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps;
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pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps;
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pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps;
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pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps;
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pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps;
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pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps;
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pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps;
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pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps;
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pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_q;
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pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_q;
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pipe_tx_reset_o <= pipe_tx_reset_q;
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pipe_tx_reset_o <= pipe_tx_reset_q;
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pipe_tx_rate_o <= pipe_tx_rate_q;
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pipe_tx_rate_o <= pipe_tx_rate_q;
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pipe_tx_deemph_o <= pipe_tx_deemph_q;
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pipe_tx_deemph_o <= pipe_tx_deemph_q;
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pipe_tx_margin_o <= pipe_tx_margin_q;
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pipe_tx_margin_o <= pipe_tx_margin_q;
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pipe_tx_swing_o <= pipe_tx_swing_q;
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pipe_tx_swing_o <= pipe_tx_swing_q;
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end generate; -- pipe_stages_1
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end generate; -- pipe_stages_1
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pipe_stages_2 : if (PIPE_PIPELINE_STAGES = 2) generate
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pipe_stages_2 : if (PIPE_PIPELINE_STAGES = 2) generate
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process (pipe_clk)
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process (pipe_clk)
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begin
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begin
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if (pipe_clk'event and pipe_clk = '1') then
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if (pipe_clk'event and pipe_clk = '1') then
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if (rst_n = '1') then
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if (rst_n = '1') then
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pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps;
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pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps;
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pipe_tx_reset_q <= '1' after (TCQ)*1 ps;
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pipe_tx_reset_q <= '1' after (TCQ)*1 ps;
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pipe_tx_rate_q <= '0' after (TCQ)*1 ps;
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pipe_tx_rate_q <= '0' after (TCQ)*1 ps;
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pipe_tx_deemph_q <= '1' after (TCQ)*1 ps;
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pipe_tx_deemph_q <= '1' after (TCQ)*1 ps;
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pipe_tx_margin_q <= "000" after (TCQ)*1 ps;
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pipe_tx_margin_q <= "000" after (TCQ)*1 ps;
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pipe_tx_swing_q <= '0' after (TCQ)*1 ps;
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pipe_tx_swing_q <= '0' after (TCQ)*1 ps;
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pipe_tx_rcvr_det_qq <= '0' after (TCQ)*1 ps;
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pipe_tx_rcvr_det_qq <= '0' after (TCQ)*1 ps;
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pipe_tx_reset_qq <= '1' after (TCQ)*1 ps;
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pipe_tx_reset_qq <= '1' after (TCQ)*1 ps;
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pipe_tx_rate_qq <= '0' after (TCQ)*1 ps;
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pipe_tx_rate_qq <= '0' after (TCQ)*1 ps;
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pipe_tx_deemph_qq <= '1' after (TCQ)*1 ps;
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pipe_tx_deemph_qq <= '1' after (TCQ)*1 ps;
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pipe_tx_margin_qq <= "000" after (TCQ)*1 ps;
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pipe_tx_margin_qq <= "000" after (TCQ)*1 ps;
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pipe_tx_swing_qq <= '0' after (TCQ)*1 ps;
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pipe_tx_swing_qq <= '0' after (TCQ)*1 ps;
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else
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else
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pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps;
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pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps;
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pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps;
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pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps;
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pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps;
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pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps;
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pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps;
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pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps;
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pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps;
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pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps;
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pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps;
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pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps;
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pipe_tx_rcvr_det_qq <= pipe_tx_rcvr_det_q after (TCQ)*1 ps;
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pipe_tx_rcvr_det_qq <= pipe_tx_rcvr_det_q after (TCQ)*1 ps;
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pipe_tx_reset_qq <= pipe_tx_reset_q after (TCQ)*1 ps;
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pipe_tx_reset_qq <= pipe_tx_reset_q after (TCQ)*1 ps;
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pipe_tx_rate_qq <= pipe_tx_rate_q after (TCQ)*1 ps;
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pipe_tx_rate_qq <= pipe_tx_rate_q after (TCQ)*1 ps;
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pipe_tx_deemph_qq <= pipe_tx_deemph_q after (TCQ)*1 ps;
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pipe_tx_deemph_qq <= pipe_tx_deemph_q after (TCQ)*1 ps;
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pipe_tx_margin_qq <= pipe_tx_margin_q after (TCQ)*1 ps;
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pipe_tx_margin_qq <= pipe_tx_margin_q after (TCQ)*1 ps;
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pipe_tx_swing_qq <= pipe_tx_swing_q after (TCQ)*1 ps;
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pipe_tx_swing_qq <= pipe_tx_swing_q after (TCQ)*1 ps;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_qq;
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pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_qq;
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pipe_tx_reset_o <= pipe_tx_reset_qq;
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pipe_tx_reset_o <= pipe_tx_reset_qq;
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pipe_tx_rate_o <= pipe_tx_rate_qq;
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pipe_tx_rate_o <= pipe_tx_rate_qq;
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pipe_tx_deemph_o <= pipe_tx_deemph_qq;
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pipe_tx_deemph_o <= pipe_tx_deemph_qq;
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pipe_tx_margin_o <= pipe_tx_margin_qq;
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pipe_tx_margin_o <= pipe_tx_margin_qq;
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pipe_tx_swing_o <= pipe_tx_swing_qq;
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pipe_tx_swing_o <= pipe_tx_swing_qq;
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|
|
end generate; -- pipe_stages_2
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end generate; -- pipe_stages_2
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|
|
end rtl;
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end rtl;
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