//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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//
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// This file contains confidential and proprietary information
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// international copyright and other intellectual property
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// laws.
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// laws.
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//
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//
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// DISCLAIMER
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// CRITICAL APPLICATIONS
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// CRITICAL APPLICATIONS
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// (individually and collectively, "Critical
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// PART OF THIS FILE AT ALL TIMES.
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_clock.v
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// File : cl_a7pcie_x4_pipe_clock.v
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// Version : 1.10
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// Version : 1.11
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : pipe_clock.v
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// Filename : pipe_clock.v
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// Description : PIPE Clock Module for 7 Series Transceiver
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// Description : PIPE Clock Module for 7 Series Transceiver
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// Version : 15.3
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// Version : 15.3
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//---------- PIPE Clock Module -------------------------------------------------
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//---------- PIPE Clock Module -------------------------------------------------
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module cl_a7pcie_x4_pipe_clock #
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module cl_a7pcie_x4_pipe_clock #
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(
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(
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parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
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parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
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parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
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parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
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parameter PCIE_LANE = 1, // PCIe number of lanes
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parameter PCIE_LANE = 1, // PCIe number of lanes
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parameter PCIE_LINK_SPEED = 3, // PCIe link speed
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parameter PCIE_LINK_SPEED = 3, // PCIe link speed
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parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
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parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
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parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
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parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
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parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
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parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
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parameter PCIE_OOBCLK_MODE = 1, // PCIe oob clock mode
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parameter PCIE_OOBCLK_MODE = 1, // PCIe oob clock mode
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parameter PCIE_DEBUG_MODE = 0 // PCIe Debug mode
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parameter PCIE_DEBUG_MODE = 0 // PCIe Debug mode
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)
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)
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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input CLK_CLK,
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input CLK_CLK,
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input CLK_TXOUTCLK,
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input CLK_TXOUTCLK,
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input [PCIE_LANE-1:0] CLK_RXOUTCLK_IN,
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input [PCIE_LANE-1:0] CLK_RXOUTCLK_IN,
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input CLK_RST_N,
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input CLK_RST_N,
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input [PCIE_LANE-1:0] CLK_PCLK_SEL,
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input [PCIE_LANE-1:0] CLK_PCLK_SEL,
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input CLK_GEN3,
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input CLK_GEN3,
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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output CLK_PCLK,
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output CLK_PCLK,
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output CLK_RXUSRCLK,
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output CLK_RXUSRCLK,
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output [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT,
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output [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT,
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output CLK_DCLK,
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output CLK_DCLK,
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output CLK_OOBCLK,
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output CLK_OOBCLK,
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output CLK_USERCLK1,
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output CLK_USERCLK1,
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output CLK_USERCLK2,
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output CLK_USERCLK2,
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output CLK_MMCM_LOCK
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output CLK_MMCM_LOCK
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);
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);
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//---------- Select Clock Divider ----------------------
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//---------- Select Clock Divider ----------------------
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localparam DIVCLK_DIVIDE = (PCIE_REFCLK_FREQ == 2) ? 1 :
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localparam DIVCLK_DIVIDE = (PCIE_REFCLK_FREQ == 2) ? 1 :
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(PCIE_REFCLK_FREQ == 1) ? 1 : 1;
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(PCIE_REFCLK_FREQ == 1) ? 1 : 1;
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localparam CLKFBOUT_MULT_F = (PCIE_REFCLK_FREQ == 2) ? 4 :
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localparam CLKFBOUT_MULT_F = (PCIE_REFCLK_FREQ == 2) ? 4 :
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(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
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(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
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localparam CLKIN1_PERIOD = (PCIE_REFCLK_FREQ == 2) ? 4 :
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localparam CLKIN1_PERIOD = (PCIE_REFCLK_FREQ == 2) ? 4 :
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(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
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(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
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localparam CLKOUT0_DIVIDE_F = 8;
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localparam CLKOUT0_DIVIDE_F = 8;
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localparam CLKOUT1_DIVIDE = 4;
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localparam CLKOUT1_DIVIDE = 4;
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localparam CLKOUT2_DIVIDE = (PCIE_USERCLK1_FREQ == 5) ? 2 :
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localparam CLKOUT2_DIVIDE = (PCIE_USERCLK1_FREQ == 5) ? 2 :
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(PCIE_USERCLK1_FREQ == 4) ? 4 :
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(PCIE_USERCLK1_FREQ == 4) ? 4 :
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(PCIE_USERCLK1_FREQ == 3) ? 8 :
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(PCIE_USERCLK1_FREQ == 3) ? 8 :
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(PCIE_USERCLK1_FREQ == 1) ? 32 : 16;
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(PCIE_USERCLK1_FREQ == 1) ? 32 : 16;
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localparam CLKOUT3_DIVIDE = (PCIE_USERCLK2_FREQ == 5) ? 2 :
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localparam CLKOUT3_DIVIDE = (PCIE_USERCLK2_FREQ == 5) ? 2 :
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(PCIE_USERCLK2_FREQ == 4) ? 4 :
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(PCIE_USERCLK2_FREQ == 4) ? 4 :
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(PCIE_USERCLK2_FREQ == 3) ? 8 :
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(PCIE_USERCLK2_FREQ == 3) ? 8 :
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(PCIE_USERCLK2_FREQ == 1) ? 32 : 16;
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(PCIE_USERCLK2_FREQ == 1) ? 32 : 16;
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localparam CLKOUT4_DIVIDE = 20;
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localparam CLKOUT4_DIVIDE = 20;
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//---------- Select Reference Clock --------------------
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//---------- Select Reference Clock --------------------
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localparam REFCLK_SEL = ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3)) ? 1'd1 : 1'd0;
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localparam REFCLK_SEL = ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3)) ? 1'd1 : 1'd0;
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//---------- Input Registers ---------------------------
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//---------- Input Registers ---------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1 = 1'd0;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1 = 1'd0;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2 = 1'd0;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2 = 1'd0;
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//---------- Internal Signals --------------------------
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//---------- Internal Signals --------------------------
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wire refclk;
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wire refclk;
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wire mmcm_fb;
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wire mmcm_fb;
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wire clk_125mhz;
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wire clk_125mhz;
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wire clk_125mhz_buf;
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wire clk_125mhz_buf;
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wire clk_250mhz;
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wire clk_250mhz;
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wire userclk1;
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wire userclk1;
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wire userclk2;
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wire userclk2;
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wire oobclk;
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wire oobclk;
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reg pclk_sel = 1'd0;
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reg pclk_sel = 1'd0;
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//---------- Output Registers --------------------------
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//---------- Output Registers --------------------------
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wire pclk_1;
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wire pclk_1;
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wire pclk;
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wire pclk;
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wire userclk1_1;
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wire userclk1_1;
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wire userclk2_1;
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wire userclk2_1;
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wire mmcm_lock;
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wire mmcm_lock;
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//---------- Generate Per-Lane Signals -----------------
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//---------- Generate Per-Lane Signals -----------------
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genvar i; // Index for per-lane signals
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genvar i; // Index for per-lane signals
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//---------- Input FF ----------------------------------------------------------
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge pclk)
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always @ (posedge pclk)
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begin
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begin
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if (!CLK_RST_N)
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if (!CLK_RST_N)
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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pclk_sel_reg1 <= {PCIE_LANE{1'd0}};
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pclk_sel_reg1 <= {PCIE_LANE{1'd0}};
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gen3_reg1 <= 1'd0;
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gen3_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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pclk_sel_reg2 <= {PCIE_LANE{1'd0}};
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pclk_sel_reg2 <= {PCIE_LANE{1'd0}};
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gen3_reg2 <= 1'd0;
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gen3_reg2 <= 1'd0;
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end
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end
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else
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else
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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pclk_sel_reg1 <= CLK_PCLK_SEL;
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pclk_sel_reg1 <= CLK_PCLK_SEL;
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gen3_reg1 <= CLK_GEN3;
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gen3_reg1 <= CLK_GEN3;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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pclk_sel_reg2 <= pclk_sel_reg1;
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pclk_sel_reg2 <= pclk_sel_reg1;
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gen3_reg2 <= gen3_reg1;
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gen3_reg2 <= gen3_reg1;
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end
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end
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end
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end
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//---------- Select Reference clock or TXOUTCLK --------------------------------
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//---------- Select Reference clock or TXOUTCLK --------------------------------
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generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))
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generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))
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begin : refclk_i
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begin : refclk_i
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//---------- Select Reference Clock ----------------------------------------
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//---------- Select Reference Clock ----------------------------------------
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BUFG refclk_i
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BUFG refclk_i
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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.I (CLK_CLK),
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.I (CLK_CLK),
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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.O (refclk)
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.O (refclk)
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);
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);
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end
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end
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else
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else
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begin : txoutclk_i
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begin : txoutclk_i
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//---------- Select TXOUTCLK -----------------------------------------------
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//---------- Select TXOUTCLK -----------------------------------------------
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BUFG txoutclk_i
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BUFG txoutclk_i
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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.I (CLK_TXOUTCLK),
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.I (CLK_TXOUTCLK),
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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.O (refclk)
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.O (refclk)
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);
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);
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end
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end
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endgenerate
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endgenerate
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//---------- MMCM --------------------------------------------------------------
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//---------- MMCM --------------------------------------------------------------
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MMCME2_ADV #
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MMCME2_ADV #
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(
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(
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.BANDWIDTH ("OPTIMIZED"),
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.BANDWIDTH ("OPTIMIZED"),
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.CLKOUT4_CASCADE ("FALSE"),
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.CLKOUT4_CASCADE ("FALSE"),
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.COMPENSATION ("ZHOLD"),
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.COMPENSATION ("ZHOLD"),
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.STARTUP_WAIT ("FALSE"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
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.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
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.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
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.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
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.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
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.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
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.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
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.CLKOUT2_PHASE (0.000),
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.CLKOUT2_PHASE (0.000),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKOUT2_USE_FINE_PS ("FALSE"),
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.CLKOUT2_USE_FINE_PS ("FALSE"),
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.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
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.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
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.CLKOUT3_PHASE (0.000),
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.CLKOUT3_PHASE (0.000),
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.CLKOUT3_DUTY_CYCLE (0.500),
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.CLKOUT3_DUTY_CYCLE (0.500),
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.CLKOUT3_USE_FINE_PS ("FALSE"),
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.CLKOUT3_USE_FINE_PS ("FALSE"),
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.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
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.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
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.CLKOUT4_PHASE (0.000),
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.CLKOUT4_PHASE (0.000),
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.CLKOUT4_DUTY_CYCLE (0.500),
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.CLKOUT4_DUTY_CYCLE (0.500),
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.CLKOUT4_USE_FINE_PS ("FALSE"),
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.CLKOUT4_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (CLKIN1_PERIOD),
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.CLKIN1_PERIOD (CLKIN1_PERIOD),
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.REF_JITTER1 (0.010)
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.REF_JITTER1 (0.010)
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|
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)
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)
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mmcm_i
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mmcm_i
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(
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(
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//---------- Input ------------------------------------
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//---------- Input ------------------------------------
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.CLKIN1 (refclk),
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.CLKIN1 (refclk),
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//.CLKIN2 (1'd0), // not used, comment out CLKIN2 if it cause implementation issues
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.CLKIN2 (1'd0), // not used, comment out CLKIN2 if it cause implementation issues
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//.CLKIN2 (refclk), // not used, comment out CLKIN2 if it cause implementation issues
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//.CLKIN2 (refclk), // not used, comment out CLKIN2 if it cause implementation issues
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.CLKINSEL (1'd1),
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.CLKINSEL (1'd1),
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.CLKFBIN (mmcm_fb),
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.CLKFBIN (mmcm_fb),
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.RST (!CLK_RST_N),
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.RST (!CLK_RST_N),
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.PWRDWN (1'd0),
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.PWRDWN (1'd0),
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|
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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.CLKFBOUT (mmcm_fb),
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.CLKFBOUT (mmcm_fb),
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.CLKFBOUTB (),
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.CLKFBOUTB (),
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.CLKOUT0 (clk_125mhz),
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.CLKOUT0 (clk_125mhz),
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.CLKOUT0B (),
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.CLKOUT0B (),
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.CLKOUT1 (clk_250mhz),
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.CLKOUT1 (clk_250mhz),
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.CLKOUT1B (),
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.CLKOUT1B (),
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.CLKOUT2 (userclk1),
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.CLKOUT2 (userclk1),
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.CLKOUT2B (),
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.CLKOUT2B (),
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.CLKOUT3 (userclk2),
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.CLKOUT3 (userclk2),
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.CLKOUT3B (),
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.CLKOUT3B (),
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.CLKOUT4 (oobclk),
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.CLKOUT4 (oobclk),
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.CLKOUT5 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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.CLKOUT6 (),
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.LOCKED (mmcm_lock),
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.LOCKED (mmcm_lock),
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|
|
//---------- Dynamic Reconfiguration -------------------
|
//---------- Dynamic Reconfiguration -------------------
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.DCLK ( 1'd0),
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.DCLK ( 1'd0),
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.DADDR ( 7'd0),
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.DADDR ( 7'd0),
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.DEN ( 1'd0),
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.DEN ( 1'd0),
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.DWE ( 1'd0),
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.DWE ( 1'd0),
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.DI (16'd0),
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.DI (16'd0),
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.DO (),
|
.DO (),
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.DRDY (),
|
.DRDY (),
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|
|
//---------- Dynamic Phase Shift -----------------------
|
//---------- Dynamic Phase Shift -----------------------
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.PSCLK (1'd0),
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.PSCLK (1'd0),
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.PSEN (1'd0),
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.PSEN (1'd0),
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.PSINCDEC (1'd0),
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.PSINCDEC (1'd0),
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.PSDONE (),
|
.PSDONE (),
|
|
|
//---------- Status ------------------------------------
|
//---------- Status ------------------------------------
|
.CLKINSTOPPED (),
|
.CLKINSTOPPED (),
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.CLKFBSTOPPED ()
|
.CLKFBSTOPPED ()
|
|
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);
|
);
|
|
|
|
|
|
|
//---------- Select PCLK MUX ---------------------------------------------------
|
//---------- Select PCLK MUX ---------------------------------------------------
|
generate if (PCIE_LINK_SPEED != 1)
|
generate if (PCIE_LINK_SPEED != 1)
|
|
|
begin : pclk_i1_bufgctrl
|
begin : pclk_i1_bufgctrl
|
//---------- PCLK Mux ----------------------------------
|
//---------- PCLK Mux ----------------------------------
|
BUFGCTRL pclk_i1
|
BUFGCTRL pclk_i1
|
(
|
(
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.CE0 (1'd1),
|
.CE0 (1'd1),
|
.CE1 (1'd1),
|
.CE1 (1'd1),
|
.I0 (clk_125mhz),
|
.I0 (clk_125mhz),
|
.I1 (clk_250mhz),
|
.I1 (clk_250mhz),
|
.IGNORE0 (1'd0),
|
.IGNORE0 (1'd0),
|
.IGNORE1 (1'd0),
|
.IGNORE1 (1'd0),
|
.S0 (~pclk_sel),
|
.S0 (~pclk_sel),
|
.S1 ( pclk_sel),
|
.S1 ( pclk_sel),
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.O (pclk_1)
|
.O (pclk_1)
|
);
|
);
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- Select PCLK Buffer ------------------------
|
//---------- Select PCLK Buffer ------------------------
|
begin : pclk_i1_bufg
|
begin : pclk_i1_bufg
|
//---------- PCLK Buffer -------------------------------
|
//---------- PCLK Buffer -------------------------------
|
BUFG pclk_i1
|
BUFG pclk_i1
|
(
|
(
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.I (clk_125mhz),
|
.I (clk_125mhz),
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.O (clk_125mhz_buf)
|
.O (clk_125mhz_buf)
|
);
|
);
|
assign pclk_1 = clk_125mhz_buf;
|
assign pclk_1 = clk_125mhz_buf;
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- Generate RXOUTCLK Buffer for Debug --------------------------------
|
//---------- Generate RXOUTCLK Buffer for Debug --------------------------------
|
generate if ((PCIE_DEBUG_MODE == 1) || (PCIE_ASYNC_EN == "TRUE"))
|
generate if ((PCIE_DEBUG_MODE == 1) || (PCIE_ASYNC_EN == "TRUE"))
|
|
|
begin : rxoutclk_per_lane
|
begin : rxoutclk_per_lane
|
//---------- Generate per Lane -------------------------
|
//---------- Generate per Lane -------------------------
|
for (i=0; i<PCIE_LANE; i=i+1)
|
for (i=0; i<PCIE_LANE; i=i+1)
|
|
|
begin : rxoutclk_i
|
begin : rxoutclk_i
|
//---------- RXOUTCLK Buffer -----------------------
|
//---------- RXOUTCLK Buffer -----------------------
|
BUFG rxoutclk_i
|
BUFG rxoutclk_i
|
(
|
(
|
//---------- Input -----------------------------
|
//---------- Input -----------------------------
|
.I (CLK_RXOUTCLK_IN[i]),
|
.I (CLK_RXOUTCLK_IN[i]),
|
//---------- Output ----------------------------
|
//---------- Output ----------------------------
|
.O (CLK_RXOUTCLK_OUT[i])
|
.O (CLK_RXOUTCLK_OUT[i])
|
);
|
);
|
end
|
end
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- Disable RXOUTCLK Buffer for Normal Operation
|
//---------- Disable RXOUTCLK Buffer for Normal Operation
|
begin : rxoutclk_i_disable
|
begin : rxoutclk_i_disable
|
assign CLK_RXOUTCLK_OUT = {PCIE_LANE{1'd0}};
|
assign CLK_RXOUTCLK_OUT = {PCIE_LANE{1'd0}};
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
//---------- Generate DCLK Buffer ----------------------------------------------
|
//---------- Generate DCLK Buffer ----------------------------------------------
|
generate if (PCIE_LINK_SPEED != 1)
|
generate if (PCIE_LINK_SPEED != 1)
|
|
|
begin : dclk_i_bufg
|
begin : dclk_i_bufg
|
//---------- DCLK Buffer -------------------------------
|
//---------- DCLK Buffer -------------------------------
|
BUFG dclk_i
|
BUFG dclk_i
|
(
|
(
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.I (clk_125mhz),
|
.I (clk_125mhz),
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.O (CLK_DCLK)
|
.O (CLK_DCLK)
|
);
|
);
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- Disable DCLK Buffer -----------------------
|
//---------- Disable DCLK Buffer -----------------------
|
begin : dclk_i
|
begin : dclk_i
|
assign CLK_DCLK = clk_125mhz_buf; // always 125 MHz in Gen1
|
assign CLK_DCLK = clk_125mhz_buf; // always 125 MHz in Gen1
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- Generate USERCLK1 Buffer ------------------------------------------
|
//---------- Generate USERCLK1 Buffer ------------------------------------------
|
generate if (PCIE_USERCLK1_FREQ != 0)
|
generate if (PCIE_USERCLK1_FREQ != 0)
|
|
|
begin : userclk1_i1
|
begin : userclk1_i1
|
//---------- USERCLK1 Buffer ---------------------------
|
//---------- USERCLK1 Buffer ---------------------------
|
BUFG usrclk1_i1
|
BUFG usrclk1_i1
|
(
|
(
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.I (userclk1),
|
.I (userclk1),
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.O (userclk1_1)
|
.O (userclk1_1)
|
);
|
);
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- Disable USERCLK1 Buffer -------------------
|
//---------- Disable USERCLK1 Buffer -------------------
|
begin : disable_userclk1_i1
|
begin : disable_userclk1_i1
|
assign userclk1_1 = 1'd0;
|
assign userclk1_1 = 1'd0;
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- Generate USERCLK2 Buffer ------------------------------------------
|
//---------- Generate USERCLK2 Buffer ------------------------------------------
|
generate if (PCIE_USERCLK2_FREQ != 0)
|
generate if (PCIE_USERCLK2_FREQ != 0)
|
|
|
begin : userclk2_i1
|
begin : userclk2_i1
|
//---------- USERCLK2 Buffer ---------------------------
|
//---------- USERCLK2 Buffer ---------------------------
|
BUFG usrclk2_i1
|
BUFG usrclk2_i1
|
(
|
(
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.I (userclk2),
|
.I (userclk2),
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.O (userclk2_1)
|
.O (userclk2_1)
|
);
|
);
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- Disable USERCLK2 Buffer -------------------
|
//---------- Disable USERCLK2 Buffer -------------------
|
begin : userclk2_i1_disable
|
begin : userclk2_i1_disable
|
assign userclk2_1 = 1'd0;
|
assign userclk2_1 = 1'd0;
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- Generate OOBCLK Buffer --------------------------------------------
|
//---------- Generate OOBCLK Buffer --------------------------------------------
|
generate if (PCIE_OOBCLK_MODE == 2)
|
generate if (PCIE_OOBCLK_MODE == 2)
|
|
|
begin : oobclk_i1
|
begin : oobclk_i1
|
//---------- OOBCLK Buffer -----------------------------
|
//---------- OOBCLK Buffer -----------------------------
|
BUFG oobclk_i1
|
BUFG oobclk_i1
|
(
|
(
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.I (oobclk),
|
.I (oobclk),
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.O (CLK_OOBCLK)
|
.O (CLK_OOBCLK)
|
);
|
);
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- Disable OOBCLK Buffer ---------------------
|
//---------- Disable OOBCLK Buffer ---------------------
|
begin : oobclk_i1_disable
|
begin : oobclk_i1_disable
|
assign CLK_OOBCLK = pclk;
|
assign CLK_OOBCLK = pclk;
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- Generate 2nd Stage Buffers ----------------------------------------
|
//---------- Generate 2nd Stage Buffers ----------------------------------------
|
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_ASYNC_EN == "TRUE"))
|
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_ASYNC_EN == "TRUE"))
|
|
|
begin : second_stage_buf
|
begin : second_stage_buf
|
|
|
//---------- PCLK Buffer ---------------------------------------------------
|
//---------- PCLK Buffer ---------------------------------------------------
|
BUFG pclk_i2
|
BUFG pclk_i2
|
(
|
(
|
//---------- Input -------------------------------------
|
//---------- Input -------------------------------------
|
.I (pclk_1),
|
.I (pclk_1),
|
//---------- Output ------------------------------------
|
//---------- Output ------------------------------------
|
.O (pclk)
|
.O (pclk)
|
);
|
);
|
|
|
|
|
|
|
//---------- RXUSRCLK Mux --------------------------------------------------
|
//---------- RXUSRCLK Mux --------------------------------------------------
|
BUFGCTRL rxusrclk_i2
|
BUFGCTRL rxusrclk_i2
|
(
|
(
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.CE0 (1'b1),
|
.CE0 (1'b1),
|
.CE1 (1'b1),
|
.CE1 (1'b1),
|
.I0 (pclk_1),
|
.I0 (pclk_1),
|
.I1 (CLK_RXOUTCLK_IN[0]),
|
.I1 (CLK_RXOUTCLK_IN[0]),
|
.IGNORE0 (1'b0),
|
.IGNORE0 (1'b0),
|
.IGNORE1 (1'b0),
|
.IGNORE1 (1'b0),
|
.S0 (~gen3_reg2),
|
.S0 (~gen3_reg2),
|
.S1 ( gen3_reg2),
|
.S1 ( gen3_reg2),
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.O (CLK_RXUSRCLK)
|
.O (CLK_RXUSRCLK)
|
);
|
);
|
|
|
|
|
|
|
//---------- Generate USERCLK1 Buffer --------------------------------------
|
//---------- Generate USERCLK1 Buffer --------------------------------------
|
if (PCIE_USERCLK1_FREQ != 0)
|
if (PCIE_USERCLK1_FREQ != 0)
|
|
|
begin : userclk1_i2
|
begin : userclk1_i2
|
//---------- USERCLK1 Buffer -----------------------
|
//---------- USERCLK1 Buffer -----------------------
|
BUFG usrclk1_i2
|
BUFG usrclk1_i2
|
(
|
(
|
//---------- Input -----------------------------
|
//---------- Input -----------------------------
|
.I (userclk1_1),
|
.I (userclk1_1),
|
//---------- Output ----------------------------
|
//---------- Output ----------------------------
|
.O (CLK_USERCLK1)
|
.O (CLK_USERCLK1)
|
);
|
);
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- Disable USERCLK1 Buffer ---------------
|
//---------- Disable USERCLK1 Buffer ---------------
|
begin : userclk1_i2_disable
|
begin : userclk1_i2_disable
|
assign CLK_USERCLK1 = userclk1_1;
|
assign CLK_USERCLK1 = userclk1_1;
|
end
|
end
|
|
|
|
|
|
|
//---------- Generate USERCLK2 Buffer --------------------------------------
|
//---------- Generate USERCLK2 Buffer --------------------------------------
|
if (PCIE_USERCLK2_FREQ != 0)
|
if (PCIE_USERCLK2_FREQ != 0)
|
|
|
begin : userclk2_i2
|
begin : userclk2_i2
|
//---------- USERCLK2 Buffer -----------------------
|
//---------- USERCLK2 Buffer -----------------------
|
BUFG usrclk2_i2
|
BUFG usrclk2_i2
|
(
|
(
|
//---------- Input -----------------------------
|
//---------- Input -----------------------------
|
.I (userclk2_1),
|
.I (userclk2_1),
|
//---------- Output ----------------------------
|
//---------- Output ----------------------------
|
.O (CLK_USERCLK2)
|
.O (CLK_USERCLK2)
|
);
|
);
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- Disable USERCLK2 Buffer ---------------
|
//---------- Disable USERCLK2 Buffer ---------------
|
begin : userclk2_i2_disable
|
begin : userclk2_i2_disable
|
assign CLK_USERCLK2 = userclk2_1;
|
assign CLK_USERCLK2 = userclk2_1;
|
end
|
end
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- Disable 2nd Stage Buffer --------------------------------------
|
//---------- Disable 2nd Stage Buffer --------------------------------------
|
begin : second_stage_buf_disable
|
begin : second_stage_buf_disable
|
assign pclk = pclk_1;
|
assign pclk = pclk_1;
|
assign CLK_RXUSRCLK = pclk_1;
|
assign CLK_RXUSRCLK = pclk_1;
|
assign CLK_USERCLK1 = userclk1_1;
|
assign CLK_USERCLK1 = userclk1_1;
|
assign CLK_USERCLK2 = userclk2_1;
|
assign CLK_USERCLK2 = userclk2_1;
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- Select PCLK -------------------------------------------------------
|
//---------- Select PCLK -------------------------------------------------------
|
always @ (posedge pclk)
|
always @ (posedge pclk)
|
begin
|
begin
|
|
|
if (!CLK_RST_N)
|
if (!CLK_RST_N)
|
pclk_sel <= 1'd0;
|
pclk_sel <= 1'd0;
|
else
|
else
|
begin
|
begin
|
//---------- Select 250 MHz ------------------------
|
//---------- Select 250 MHz ------------------------
|
if (&pclk_sel_reg2)
|
if (&pclk_sel_reg2)
|
pclk_sel <= 1'd1;
|
pclk_sel <= 1'd1;
|
//---------- Select 125 MHz ------------------------
|
//---------- Select 125 MHz ------------------------
|
else if (&(~pclk_sel_reg2))
|
else if (&(~pclk_sel_reg2))
|
pclk_sel <= 1'd0;
|
pclk_sel <= 1'd0;
|
//---------- Hold PCLK -----------------------------
|
//---------- Hold PCLK -----------------------------
|
else
|
else
|
pclk_sel <= pclk_sel;
|
pclk_sel <= pclk_sel;
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- PIPE Clock Output -------------------------------------------------
|
//---------- PIPE Clock Output -------------------------------------------------
|
assign CLK_PCLK = pclk;
|
assign CLK_PCLK = pclk;
|
assign CLK_MMCM_LOCK = mmcm_lock;
|
assign CLK_MMCM_LOCK = mmcm_lock;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
