//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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//
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// This file contains confidential and proprietary information
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// international copyright and other intellectual property
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// laws.
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// laws.
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//
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//
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// DISCLAIMER
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// CRITICAL APPLICATIONS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_pipe_user.v
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// File : cl_a7pcie_x4_pipe_user.v
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// Version : 1.10
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// Version : 1.11
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : pipe_user.v
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// Filename : pipe_user.v
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// Description : PIPE User Module for 7 Series Transceiver
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// Description : PIPE User Module for 7 Series Transceiver
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// Version : 15.3.3
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// Version : 15.3.3
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//---------- PIPE User Module --------------------------------------------------
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//---------- PIPE User Module --------------------------------------------------
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module cl_a7pcie_x4_pipe_user #
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module cl_a7pcie_x4_pipe_user #
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(
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(
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parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
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parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
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parameter PCIE_USE_MODE = "3.0", // PCIe sim version
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parameter PCIE_USE_MODE = "3.0", // PCIe sim version
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parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
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parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
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parameter RXCDRLOCK_MAX = 4'd15, // RXCDRLOCK max count
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parameter RXCDRLOCK_MAX = 4'd15, // RXCDRLOCK max count
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parameter RXVALID_MAX = 4'd15, // RXVALID max count
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parameter RXVALID_MAX = 4'd15, // RXVALID max count
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parameter CONVERGE_MAX = 22'd3125000 // Convergence max count
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parameter CONVERGE_MAX = 22'd3125000 // Convergence max count
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)
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)
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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input USER_TXUSRCLK,
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input USER_TXUSRCLK,
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input USER_RXUSRCLK,
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input USER_RXUSRCLK,
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input USER_OOBCLK_IN,
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input USER_OOBCLK_IN,
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input USER_RST_N,
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input USER_RST_N,
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input USER_RXUSRCLK_RST_N,
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input USER_RXUSRCLK_RST_N,
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input USER_PCLK_SEL,
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input USER_PCLK_SEL,
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input USER_RESETOVRD_START,
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input USER_RESETOVRD_START,
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input USER_TXRESETDONE,
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input USER_TXRESETDONE,
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input USER_RXRESETDONE,
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input USER_RXRESETDONE,
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input USER_TXELECIDLE,
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input USER_TXELECIDLE,
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input USER_TXCOMPLIANCE,
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input USER_TXCOMPLIANCE,
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input USER_RXCDRLOCK_IN,
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input USER_RXCDRLOCK_IN,
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input USER_RXVALID_IN,
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input USER_RXVALID_IN,
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input USER_RXSTATUS_IN,
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input USER_RXSTATUS_IN,
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input USER_PHYSTATUS_IN,
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input USER_PHYSTATUS_IN,
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input USER_RATE_DONE,
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input USER_RATE_DONE,
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input USER_RST_IDLE,
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input USER_RST_IDLE,
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input USER_RATE_RXSYNC,
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input USER_RATE_RXSYNC,
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input USER_RATE_IDLE,
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input USER_RATE_IDLE,
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input USER_RATE_GEN3,
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input USER_RATE_GEN3,
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input USER_RXEQ_ADAPT_DONE,
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input USER_RXEQ_ADAPT_DONE,
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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output USER_OOBCLK,
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output USER_OOBCLK,
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output USER_RESETOVRD,
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output USER_RESETOVRD,
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output USER_TXPMARESET,
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output USER_TXPMARESET,
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output USER_RXPMARESET,
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output USER_RXPMARESET,
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output USER_RXCDRRESET,
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output USER_RXCDRRESET,
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output USER_RXCDRFREQRESET,
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output USER_RXCDRFREQRESET,
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output USER_RXDFELPMRESET,
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output USER_RXDFELPMRESET,
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output USER_EYESCANRESET,
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output USER_EYESCANRESET,
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output USER_TXPCSRESET,
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output USER_TXPCSRESET,
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output USER_RXPCSRESET,
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output USER_RXPCSRESET,
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output USER_RXBUFRESET,
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output USER_RXBUFRESET,
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output USER_RESETOVRD_DONE,
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output USER_RESETOVRD_DONE,
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output USER_RESETDONE,
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output USER_RESETDONE,
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output USER_ACTIVE_LANE,
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output USER_ACTIVE_LANE,
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output USER_RXCDRLOCK_OUT,
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output USER_RXCDRLOCK_OUT,
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output USER_RXVALID_OUT,
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output USER_RXVALID_OUT,
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output USER_PHYSTATUS_OUT,
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output USER_PHYSTATUS_OUT,
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output USER_PHYSTATUS_RST,
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output USER_PHYSTATUS_RST,
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output USER_GEN3_RDY,
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output USER_GEN3_RDY,
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output USER_RX_CONVERGE
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output USER_RX_CONVERGE
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);
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);
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//---------- Input Registers ---------------------------
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//---------- Input Registers ---------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2;
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//---------- Internal Signal ---------------------------
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//---------- Internal Signal ---------------------------
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reg [ 1:0] oobclk_cnt = 2'd0;
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reg [ 1:0] oobclk_cnt = 2'd0;
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reg [ 7:0] reset_cnt = 8'd127;
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reg [ 7:0] reset_cnt = 8'd127;
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reg [ 3:0] rxcdrlock_cnt = 4'd0;
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reg [ 3:0] rxcdrlock_cnt = 4'd0;
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reg [ 3:0] rxvalid_cnt = 4'd0;
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reg [ 3:0] rxvalid_cnt = 4'd0;
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reg [21:0] converge_cnt = 22'd0;
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reg [21:0] converge_cnt = 22'd0;
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reg converge_gen3 = 1'd0;
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reg converge_gen3 = 1'd0;
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//---------- Output Registers --------------------------
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//---------- Output Registers --------------------------
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reg oobclk = 1'd0;
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reg oobclk = 1'd0;
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reg [ 7:0] reset = 8'h00;
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reg [ 7:0] reset = 8'h00;
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reg gen3_rdy = 1'd0;
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reg gen3_rdy = 1'd0;
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reg [ 1:0] fsm = 2'd0;
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reg [ 1:0] fsm = 2'd0;
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//---------- FSM ---------------------------------------
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 2'd0;
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localparam FSM_IDLE = 2'd0;
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localparam FSM_RESETOVRD = 2'd1;
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localparam FSM_RESETOVRD = 2'd1;
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localparam FSM_RESET_INIT = 2'd2;
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localparam FSM_RESET_INIT = 2'd2;
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localparam FSM_RESET = 2'd3;
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localparam FSM_RESET = 2'd3;
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//---------- Simulation Speedup ------------------------
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//---------- Simulation Speedup ------------------------
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localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX;
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localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX;
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//---------- Input FF ----------------------------------------------------------
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge USER_TXUSRCLK)
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always @ (posedge USER_TXUSRCLK)
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begin
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begin
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if (!USER_RST_N)
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if (!USER_RST_N)
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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pclk_sel_reg1 <= 1'd0;
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pclk_sel_reg1 <= 1'd0;
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resetovrd_start_reg1 <= 1'd0;
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resetovrd_start_reg1 <= 1'd0;
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txresetdone_reg1 <= 1'd0;
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txresetdone_reg1 <= 1'd0;
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rxresetdone_reg1 <= 1'd0;
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rxresetdone_reg1 <= 1'd0;
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txelecidle_reg1 <= 1'd0;
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txelecidle_reg1 <= 1'd0;
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txcompliance_reg1 <= 1'd0;
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txcompliance_reg1 <= 1'd0;
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rxcdrlock_reg1 <= 1'd0;
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rxcdrlock_reg1 <= 1'd0;
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rxeq_adapt_done_reg1 <= 1'd0;
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rxeq_adapt_done_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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pclk_sel_reg2 <= 1'd0;
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pclk_sel_reg2 <= 1'd0;
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resetovrd_start_reg2 <= 1'd0;
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resetovrd_start_reg2 <= 1'd0;
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txresetdone_reg2 <= 1'd0;
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txresetdone_reg2 <= 1'd0;
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rxresetdone_reg2 <= 1'd0;
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rxresetdone_reg2 <= 1'd0;
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txelecidle_reg2 <= 1'd0;
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txelecidle_reg2 <= 1'd0;
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txcompliance_reg2 <= 1'd0;
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txcompliance_reg2 <= 1'd0;
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rxcdrlock_reg2 <= 1'd0;
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rxcdrlock_reg2 <= 1'd0;
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rxeq_adapt_done_reg2 <= 1'd0;
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rxeq_adapt_done_reg2 <= 1'd0;
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end
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end
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else
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else
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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pclk_sel_reg1 <= USER_PCLK_SEL;
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pclk_sel_reg1 <= USER_PCLK_SEL;
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resetovrd_start_reg1 <= USER_RESETOVRD_START;
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resetovrd_start_reg1 <= USER_RESETOVRD_START;
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txresetdone_reg1 <= USER_TXRESETDONE;
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txresetdone_reg1 <= USER_TXRESETDONE;
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rxresetdone_reg1 <= USER_RXRESETDONE;
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rxresetdone_reg1 <= USER_RXRESETDONE;
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txelecidle_reg1 <= USER_TXELECIDLE;
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txelecidle_reg1 <= USER_TXELECIDLE;
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txcompliance_reg1 <= USER_TXCOMPLIANCE;
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txcompliance_reg1 <= USER_TXCOMPLIANCE;
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rxcdrlock_reg1 <= USER_RXCDRLOCK_IN;
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rxcdrlock_reg1 <= USER_RXCDRLOCK_IN;
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rxeq_adapt_done_reg1 <= USER_RXEQ_ADAPT_DONE;
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rxeq_adapt_done_reg1 <= USER_RXEQ_ADAPT_DONE;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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pclk_sel_reg2 <= pclk_sel_reg1;
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pclk_sel_reg2 <= pclk_sel_reg1;
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resetovrd_start_reg2 <= resetovrd_start_reg1;
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resetovrd_start_reg2 <= resetovrd_start_reg1;
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txresetdone_reg2 <= txresetdone_reg1;
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txresetdone_reg2 <= txresetdone_reg1;
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rxresetdone_reg2 <= rxresetdone_reg1;
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rxresetdone_reg2 <= rxresetdone_reg1;
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txelecidle_reg2 <= txelecidle_reg1;
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txelecidle_reg2 <= txelecidle_reg1;
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txcompliance_reg2 <= txcompliance_reg1;
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txcompliance_reg2 <= txcompliance_reg1;
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rxcdrlock_reg2 <= rxcdrlock_reg1;
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rxcdrlock_reg2 <= rxcdrlock_reg1;
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rxeq_adapt_done_reg2 <= rxeq_adapt_done_reg1;
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rxeq_adapt_done_reg2 <= rxeq_adapt_done_reg1;
|
end
|
end
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|
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end
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end
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//---------- Input FF ----------------------------------------------------------
|
//---------- Input FF ----------------------------------------------------------
|
always @ (posedge USER_RXUSRCLK)
|
always @ (posedge USER_RXUSRCLK)
|
begin
|
begin
|
|
|
if (!USER_RXUSRCLK_RST_N)
|
if (!USER_RXUSRCLK_RST_N)
|
begin
|
begin
|
//---------- 1st Stage FF --------------------------
|
//---------- 1st Stage FF --------------------------
|
rxvalid_reg1 <= 1'd0;
|
rxvalid_reg1 <= 1'd0;
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rxstatus_reg1 <= 1'd0;
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rxstatus_reg1 <= 1'd0;
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rst_idle_reg1 <= 1'd0;
|
rst_idle_reg1 <= 1'd0;
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rate_done_reg1 <= 1'd0;
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rate_done_reg1 <= 1'd0;
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rate_rxsync_reg1 <= 1'd0;
|
rate_rxsync_reg1 <= 1'd0;
|
rate_idle_reg1 <= 1'd0;
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rate_idle_reg1 <= 1'd0;
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rate_gen3_reg1 <= 1'd0;
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rate_gen3_reg1 <= 1'd0;
|
//---------- 2nd Stage FF --------------------------
|
//---------- 2nd Stage FF --------------------------
|
rxvalid_reg2 <= 1'd0;
|
rxvalid_reg2 <= 1'd0;
|
rxstatus_reg2 <= 1'd0;
|
rxstatus_reg2 <= 1'd0;
|
rst_idle_reg2 <= 1'd0;
|
rst_idle_reg2 <= 1'd0;
|
rate_done_reg2 <= 1'd0;
|
rate_done_reg2 <= 1'd0;
|
rate_rxsync_reg2 <= 1'd0;
|
rate_rxsync_reg2 <= 1'd0;
|
rate_idle_reg2 <= 1'd0;
|
rate_idle_reg2 <= 1'd0;
|
rate_gen3_reg2 <= 1'd0;
|
rate_gen3_reg2 <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
//---------- 1st Stage FF --------------------------
|
//---------- 1st Stage FF --------------------------
|
rxvalid_reg1 <= USER_RXVALID_IN;
|
rxvalid_reg1 <= USER_RXVALID_IN;
|
rxstatus_reg1 <= USER_RXSTATUS_IN;
|
rxstatus_reg1 <= USER_RXSTATUS_IN;
|
rst_idle_reg1 <= USER_RST_IDLE;
|
rst_idle_reg1 <= USER_RST_IDLE;
|
rate_done_reg1 <= USER_RATE_DONE;
|
rate_done_reg1 <= USER_RATE_DONE;
|
rate_rxsync_reg1 <= USER_RATE_RXSYNC;
|
rate_rxsync_reg1 <= USER_RATE_RXSYNC;
|
rate_idle_reg1 <= USER_RATE_IDLE;
|
rate_idle_reg1 <= USER_RATE_IDLE;
|
rate_gen3_reg1 <= USER_RATE_GEN3;
|
rate_gen3_reg1 <= USER_RATE_GEN3;
|
//---------- 2nd Stage FF --------------------------
|
//---------- 2nd Stage FF --------------------------
|
rxvalid_reg2 <= rxvalid_reg1;
|
rxvalid_reg2 <= rxvalid_reg1;
|
rxstatus_reg2 <= rxstatus_reg1;
|
rxstatus_reg2 <= rxstatus_reg1;
|
rst_idle_reg2 <= rst_idle_reg1;
|
rst_idle_reg2 <= rst_idle_reg1;
|
rate_done_reg2 <= rate_done_reg1;
|
rate_done_reg2 <= rate_done_reg1;
|
rate_rxsync_reg2 <= rate_rxsync_reg1;
|
rate_rxsync_reg2 <= rate_rxsync_reg1;
|
rate_idle_reg2 <= rate_idle_reg1;
|
rate_idle_reg2 <= rate_idle_reg1;
|
rate_gen3_reg2 <= rate_gen3_reg1;
|
rate_gen3_reg2 <= rate_gen3_reg1;
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- Generate Reset Override -------------------------------------------
|
//---------- Generate Reset Override -------------------------------------------
|
generate if (PCIE_USE_MODE == "1.0")
|
generate if (PCIE_USE_MODE == "1.0")
|
|
|
begin : resetovrd
|
begin : resetovrd
|
|
|
//---------- Reset Counter -------------------------------------------------
|
//---------- Reset Counter -------------------------------------------------
|
always @ (posedge USER_TXUSRCLK)
|
always @ (posedge USER_TXUSRCLK)
|
begin
|
begin
|
|
|
if (!USER_RST_N)
|
if (!USER_RST_N)
|
reset_cnt <= 8'd127;
|
reset_cnt <= 8'd127;
|
else
|
else
|
|
|
//---------- Decrement Counter ---------------------
|
//---------- Decrement Counter ---------------------
|
if (((fsm == FSM_RESETOVRD) || (fsm == FSM_RESET)) && (reset_cnt != 8'd0))
|
if (((fsm == FSM_RESETOVRD) || (fsm == FSM_RESET)) && (reset_cnt != 8'd0))
|
reset_cnt <= reset_cnt - 8'd1;
|
reset_cnt <= reset_cnt - 8'd1;
|
|
|
//---------- Reset Counter -------------------------
|
//---------- Reset Counter -------------------------
|
else
|
else
|
|
|
case (reset)
|
case (reset)
|
8'b00000000 : reset_cnt <= 8'd127; // Programmable PMARESET time
|
8'b00000000 : reset_cnt <= 8'd127; // Programmable PMARESET time
|
8'b11111111 : reset_cnt <= 8'd127; // Programmable RXCDRRESET time
|
8'b11111111 : reset_cnt <= 8'd127; // Programmable RXCDRRESET time
|
8'b11111110 : reset_cnt <= 8'd127; // Programmable RXCDRFREQRESET time
|
8'b11111110 : reset_cnt <= 8'd127; // Programmable RXCDRFREQRESET time
|
8'b11111100 : reset_cnt <= 8'd127; // Programmable RXDFELPMRESET time
|
8'b11111100 : reset_cnt <= 8'd127; // Programmable RXDFELPMRESET time
|
8'b11111000 : reset_cnt <= 8'd127; // Programmable EYESCANRESET time
|
8'b11111000 : reset_cnt <= 8'd127; // Programmable EYESCANRESET time
|
8'b11110000 : reset_cnt <= 8'd127; // Programmable PCSRESET time
|
8'b11110000 : reset_cnt <= 8'd127; // Programmable PCSRESET time
|
8'b11100000 : reset_cnt <= 8'd127; // Programmable RXBUFRESET time
|
8'b11100000 : reset_cnt <= 8'd127; // Programmable RXBUFRESET time
|
8'b11000000 : reset_cnt <= 8'd127; // Programmable RESETOVRD deassertion time
|
8'b11000000 : reset_cnt <= 8'd127; // Programmable RESETOVRD deassertion time
|
8'b10000000 : reset_cnt <= 8'd127;
|
8'b10000000 : reset_cnt <= 8'd127;
|
default : reset_cnt <= 8'd127;
|
default : reset_cnt <= 8'd127;
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- Reset Shift Register ------------------------------------------
|
//---------- Reset Shift Register ------------------------------------------
|
always @ (posedge USER_TXUSRCLK)
|
always @ (posedge USER_TXUSRCLK)
|
begin
|
begin
|
|
|
if (!USER_RST_N)
|
if (!USER_RST_N)
|
reset <= 8'h00;
|
reset <= 8'h00;
|
else
|
else
|
|
|
//---------- Initialize Reset Register ---------
|
//---------- Initialize Reset Register ---------
|
if (fsm == FSM_RESET_INIT)
|
if (fsm == FSM_RESET_INIT)
|
reset <= 8'hFF;
|
reset <= 8'hFF;
|
//---------- Shift Reset Register --------------
|
//---------- Shift Reset Register --------------
|
else if ((fsm == FSM_RESET) && (reset_cnt == 8'd0))
|
else if ((fsm == FSM_RESET) && (reset_cnt == 8'd0))
|
reset <= {reset[6:0], 1'd0};
|
reset <= {reset[6:0], 1'd0};
|
//---------- Hold Reset Register ---------------
|
//---------- Hold Reset Register ---------------
|
else
|
else
|
reset <= reset;
|
reset <= reset;
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- Reset Override FSM --------------------------------------------
|
//---------- Reset Override FSM --------------------------------------------
|
always @ (posedge USER_TXUSRCLK)
|
always @ (posedge USER_TXUSRCLK)
|
begin
|
begin
|
|
|
if (!USER_RST_N)
|
if (!USER_RST_N)
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
|
|
else
|
else
|
|
|
begin
|
begin
|
|
|
case (fsm)
|
case (fsm)
|
//---------- Idle State ------------------------
|
//---------- Idle State ------------------------
|
FSM_IDLE : fsm <= resetovrd_start_reg2 ? FSM_RESETOVRD : FSM_IDLE;
|
FSM_IDLE : fsm <= resetovrd_start_reg2 ? FSM_RESETOVRD : FSM_IDLE;
|
//---------- Assert RESETOVRD ------------------
|
//---------- Assert RESETOVRD ------------------
|
FSM_RESETOVRD : fsm <= (reset_cnt == 8'd0) ? FSM_RESET_INIT : FSM_RESETOVRD;
|
FSM_RESETOVRD : fsm <= (reset_cnt == 8'd0) ? FSM_RESET_INIT : FSM_RESETOVRD;
|
//---------- Initialize Reset ------------------
|
//---------- Initialize Reset ------------------
|
FSM_RESET_INIT : fsm <= FSM_RESET;
|
FSM_RESET_INIT : fsm <= FSM_RESET;
|
//---------- Shift Reset -----------------------
|
//---------- Shift Reset -----------------------
|
FSM_RESET : fsm <= ((reset == 8'd0) && rxresetdone_reg2) ? FSM_IDLE : FSM_RESET;
|
FSM_RESET : fsm <= ((reset == 8'd0) && rxresetdone_reg2) ? FSM_IDLE : FSM_RESET;
|
//---------- Default State ---------------------
|
//---------- Default State ---------------------
|
default : fsm <= FSM_IDLE;
|
default : fsm <= FSM_IDLE;
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
//---------- Disable Reset Override --------------------------------------------
|
//---------- Disable Reset Override --------------------------------------------
|
else
|
else
|
|
|
begin : resetovrd_disble
|
begin : resetovrd_disble
|
|
|
//---------- Generate Default Signals --------------------------------------
|
//---------- Generate Default Signals --------------------------------------
|
always @ (posedge USER_TXUSRCLK)
|
always @ (posedge USER_TXUSRCLK)
|
begin
|
begin
|
|
|
if (!USER_RST_N)
|
if (!USER_RST_N)
|
begin
|
begin
|
reset_cnt <= 8'hFF;
|
reset_cnt <= 8'hFF;
|
reset <= 8'd0;
|
reset <= 8'd0;
|
fsm <= 2'd0;
|
fsm <= 2'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
reset_cnt <= 8'hFF;
|
reset_cnt <= 8'hFF;
|
reset <= 8'd0;
|
reset <= 8'd0;
|
fsm <= 2'd0;
|
fsm <= 2'd0;
|
end
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- Generate OOB Clock Divider ------------------------
|
//---------- Generate OOB Clock Divider ------------------------
|
generate if (PCIE_OOBCLK_MODE == 1)
|
generate if (PCIE_OOBCLK_MODE == 1)
|
|
|
begin : oobclk_div
|
begin : oobclk_div
|
|
|
//---------- OOB Clock Divider -----------------------------
|
//---------- OOB Clock Divider -----------------------------
|
always @ (posedge USER_OOBCLK_IN)
|
always @ (posedge USER_OOBCLK_IN)
|
begin
|
begin
|
|
|
if (!USER_RST_N)
|
if (!USER_RST_N)
|
begin
|
begin
|
oobclk_cnt <= 2'd0;
|
oobclk_cnt <= 2'd0;
|
oobclk <= 1'd0;
|
oobclk <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
oobclk_cnt <= oobclk_cnt + 2'd1;
|
oobclk_cnt <= oobclk_cnt + 2'd1;
|
oobclk <= pclk_sel_reg2 ? oobclk_cnt[1] : oobclk_cnt[0];
|
oobclk <= pclk_sel_reg2 ? oobclk_cnt[1] : oobclk_cnt[0];
|
end
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
begin : oobclk_div_disable
|
begin : oobclk_div_disable
|
|
|
//---------- OOB Clock Default -------------------------
|
//---------- OOB Clock Default -------------------------
|
always @ (posedge USER_OOBCLK_IN)
|
always @ (posedge USER_OOBCLK_IN)
|
begin
|
begin
|
|
|
if (!USER_RST_N)
|
if (!USER_RST_N)
|
begin
|
begin
|
oobclk_cnt <= 2'd0;
|
oobclk_cnt <= 2'd0;
|
oobclk <= 1'd0;
|
oobclk <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
oobclk_cnt <= 2'd0;
|
oobclk_cnt <= 2'd0;
|
oobclk <= 1'd0;
|
oobclk <= 1'd0;
|
end
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
//---------- RXCDRLOCK Filter --------------------------------------------------
|
//---------- RXCDRLOCK Filter --------------------------------------------------
|
always @ (posedge USER_TXUSRCLK)
|
always @ (posedge USER_TXUSRCLK)
|
begin
|
begin
|
|
|
if (!USER_RST_N)
|
if (!USER_RST_N)
|
rxcdrlock_cnt <= 4'd0;
|
rxcdrlock_cnt <= 4'd0;
|
else
|
else
|
|
|
//---------- Increment RXCDRLOCK Counter -----------
|
//---------- Increment RXCDRLOCK Counter -----------
|
if (rxcdrlock_reg2 && (rxcdrlock_cnt != RXCDRLOCK_MAX))
|
if (rxcdrlock_reg2 && (rxcdrlock_cnt != RXCDRLOCK_MAX))
|
rxcdrlock_cnt <= rxcdrlock_cnt + 4'd1;
|
rxcdrlock_cnt <= rxcdrlock_cnt + 4'd1;
|
|
|
//---------- Hold RXCDRLOCK Counter ----------------
|
//---------- Hold RXCDRLOCK Counter ----------------
|
else if (rxcdrlock_reg2 && (rxcdrlock_cnt == RXCDRLOCK_MAX))
|
else if (rxcdrlock_reg2 && (rxcdrlock_cnt == RXCDRLOCK_MAX))
|
rxcdrlock_cnt <= rxcdrlock_cnt;
|
rxcdrlock_cnt <= rxcdrlock_cnt;
|
|
|
//---------- Reset RXCDRLOCK Counter ---------------
|
//---------- Reset RXCDRLOCK Counter ---------------
|
else
|
else
|
rxcdrlock_cnt <= 4'd0;
|
rxcdrlock_cnt <= 4'd0;
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- RXVALID Filter ----------------------------------------------------
|
//---------- RXVALID Filter ----------------------------------------------------
|
always @ (posedge USER_RXUSRCLK)
|
always @ (posedge USER_RXUSRCLK)
|
begin
|
begin
|
|
|
if (!USER_RXUSRCLK_RST_N)
|
if (!USER_RXUSRCLK_RST_N)
|
rxvalid_cnt <= 4'd0;
|
rxvalid_cnt <= 4'd0;
|
else
|
else
|
|
|
//---------- Increment RXVALID Counter -------------
|
//---------- Increment RXVALID Counter -------------
|
if (rxvalid_reg2 && (rxvalid_cnt != RXVALID_MAX) && (!rxstatus_reg2))
|
if (rxvalid_reg2 && (rxvalid_cnt != RXVALID_MAX) && (!rxstatus_reg2))
|
rxvalid_cnt <= rxvalid_cnt + 4'd1;
|
rxvalid_cnt <= rxvalid_cnt + 4'd1;
|
|
|
//---------- Hold RXVALID Counter ------------------
|
//---------- Hold RXVALID Counter ------------------
|
else if (rxvalid_reg2 && (rxvalid_cnt == RXVALID_MAX))
|
else if (rxvalid_reg2 && (rxvalid_cnt == RXVALID_MAX))
|
rxvalid_cnt <= rxvalid_cnt;
|
rxvalid_cnt <= rxvalid_cnt;
|
|
|
//---------- Reset RXVALID Counter -----------------
|
//---------- Reset RXVALID Counter -----------------
|
else
|
else
|
rxvalid_cnt <= 4'd0;
|
rxvalid_cnt <= 4'd0;
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- Converge Counter --------------------------------------------------
|
//---------- Converge Counter --------------------------------------------------
|
always @ (posedge USER_TXUSRCLK)
|
always @ (posedge USER_TXUSRCLK)
|
begin
|
begin
|
|
|
if (!USER_RST_N)
|
if (!USER_RST_N)
|
converge_cnt <= 22'd0;
|
converge_cnt <= 22'd0;
|
else
|
else
|
|
|
//---------- Enter Gen1/Gen2 -----------------------
|
//---------- Enter Gen1/Gen2 -----------------------
|
if (rst_idle_reg2 && rate_idle_reg2 && !rate_gen3_reg2)
|
if (rst_idle_reg2 && rate_idle_reg2 && !rate_gen3_reg2)
|
begin
|
begin
|
|
|
//---------- Increment Converge Counter --------
|
//---------- Increment Converge Counter --------
|
if (converge_cnt < converge_max_cnt)
|
if (converge_cnt < converge_max_cnt)
|
converge_cnt <= converge_cnt + 22'd1;
|
converge_cnt <= converge_cnt + 22'd1;
|
//---------- Hold Converge Counter -------------
|
//---------- Hold Converge Counter -------------
|
else
|
else
|
converge_cnt <= converge_cnt;
|
converge_cnt <= converge_cnt;
|
|
|
end
|
end
|
|
|
//---------- Reset Converge Counter ----------------
|
//---------- Reset Converge Counter ----------------
|
else
|
else
|
converge_cnt <= 22'd0;
|
converge_cnt <= 22'd0;
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- Converge ----------------------------------------------------------
|
//---------- Converge ----------------------------------------------------------
|
always @ (posedge USER_TXUSRCLK)
|
always @ (posedge USER_TXUSRCLK)
|
begin
|
begin
|
|
|
if (!USER_RST_N)
|
if (!USER_RST_N)
|
converge_gen3 <= 1'd0;
|
converge_gen3 <= 1'd0;
|
else
|
else
|
|
|
//---------- Enter Gen3 ----------------------------
|
//---------- Enter Gen3 ----------------------------
|
if (rate_gen3_reg2)
|
if (rate_gen3_reg2)
|
|
|
//---------- Wait for RX equalization adapt done
|
//---------- Wait for RX equalization adapt done
|
if (rxeq_adapt_done_reg2)
|
if (rxeq_adapt_done_reg2)
|
converge_gen3 <= 1'd1;
|
converge_gen3 <= 1'd1;
|
else
|
else
|
converge_gen3 <= converge_gen3;
|
converge_gen3 <= converge_gen3;
|
|
|
//-------- Exit Gen3 -------------------------------
|
//-------- Exit Gen3 -------------------------------
|
else
|
else
|
|
|
converge_gen3 <= 1'd0;
|
converge_gen3 <= 1'd0;
|
|
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- GEN3_RDY Generator ------------------------------------------------
|
//---------- GEN3_RDY Generator ------------------------------------------------
|
always @ (posedge USER_RXUSRCLK)
|
always @ (posedge USER_RXUSRCLK)
|
begin
|
begin
|
|
|
if (!USER_RXUSRCLK_RST_N)
|
if (!USER_RXUSRCLK_RST_N)
|
gen3_rdy <= 1'd0;
|
gen3_rdy <= 1'd0;
|
else
|
else
|
gen3_rdy <= rate_idle_reg2 && rate_gen3_reg2;
|
gen3_rdy <= rate_idle_reg2 && rate_gen3_reg2;
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- PIPE User Override Reset Output -----------------------------------
|
//---------- PIPE User Override Reset Output -----------------------------------
|
assign USER_RESETOVRD = (fsm != FSM_IDLE);
|
assign USER_RESETOVRD = (fsm != FSM_IDLE);
|
assign USER_TXPMARESET = 1'd0;
|
assign USER_TXPMARESET = 1'd0;
|
assign USER_RXPMARESET = reset[0];
|
assign USER_RXPMARESET = reset[0];
|
assign USER_RXCDRRESET = reset[1];
|
assign USER_RXCDRRESET = reset[1];
|
assign USER_RXCDRFREQRESET = reset[2];
|
assign USER_RXCDRFREQRESET = reset[2];
|
assign USER_RXDFELPMRESET = reset[3];
|
assign USER_RXDFELPMRESET = reset[3];
|
assign USER_EYESCANRESET = reset[4];
|
assign USER_EYESCANRESET = reset[4];
|
assign USER_TXPCSRESET = 1'd0;
|
assign USER_TXPCSRESET = 1'd0;
|
assign USER_RXPCSRESET = reset[5];
|
assign USER_RXPCSRESET = reset[5];
|
assign USER_RXBUFRESET = reset[6];
|
assign USER_RXBUFRESET = reset[6];
|
assign USER_RESETOVRD_DONE = (fsm == FSM_IDLE);
|
assign USER_RESETOVRD_DONE = (fsm == FSM_IDLE);
|
|
|
//---------- PIPE User Output --------------------------------------------------
|
//---------- PIPE User Output --------------------------------------------------
|
assign USER_OOBCLK = oobclk;
|
assign USER_OOBCLK = oobclk;
|
assign USER_RESETDONE = (txresetdone_reg2 && rxresetdone_reg2);
|
assign USER_RESETDONE = (txresetdone_reg2 && rxresetdone_reg2);
|
assign USER_ACTIVE_LANE = !(txelecidle_reg2 && txcompliance_reg2);
|
assign USER_ACTIVE_LANE = !(txelecidle_reg2 && txcompliance_reg2);
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
assign USER_RXCDRLOCK_OUT = (USER_RXCDRLOCK_IN && (rxcdrlock_cnt == RXCDRLOCK_MAX)); // Filtered RXCDRLOCK
|
assign USER_RXCDRLOCK_OUT = (USER_RXCDRLOCK_IN && (rxcdrlock_cnt == RXCDRLOCK_MAX)); // Filtered RXCDRLOCK
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
assign USER_RXVALID_OUT = ((USER_RXVALID_IN && (rxvalid_cnt == RXVALID_MAX)) && // Filtered RXVALID
|
assign USER_RXVALID_OUT = ((USER_RXVALID_IN && (rxvalid_cnt == RXVALID_MAX)) && // Filtered RXVALID
|
rst_idle_reg2 && // Force RXVALID = 0 during reset
|
rst_idle_reg2 && // Force RXVALID = 0 during reset
|
rate_idle_reg2); // Force RXVALID = 0 during rate change
|
rate_idle_reg2); // Force RXVALID = 0 during rate change
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
assign USER_PHYSTATUS_OUT = (!rst_idle_reg2 || // Force PHYSTATUS = 1 during reset
|
assign USER_PHYSTATUS_OUT = (!rst_idle_reg2 || // Force PHYSTATUS = 1 during reset
|
((rate_idle_reg2 || rate_rxsync_reg2) && USER_PHYSTATUS_IN) || // Raw PHYSTATUS
|
((rate_idle_reg2 || rate_rxsync_reg2) && USER_PHYSTATUS_IN) || // Raw PHYSTATUS
|
rate_done_reg2); // Gated PHYSTATUS for rate change
|
rate_done_reg2); // Gated PHYSTATUS for rate change
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
assign USER_PHYSTATUS_RST = !rst_idle_reg2; // Filtered PHYSTATUS for reset
|
assign USER_PHYSTATUS_RST = !rst_idle_reg2; // Filtered PHYSTATUS for reset
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
assign USER_GEN3_RDY = 0;//gen3_rdy;
|
assign USER_GEN3_RDY = 0;//gen3_rdy;
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
assign USER_RX_CONVERGE = (converge_cnt == converge_max_cnt) || converge_gen3;
|
assign USER_RX_CONVERGE = (converge_cnt == converge_max_cnt) || converge_gen3;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
