//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//
|
//
|
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
|
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
|
//
|
//
|
// This file contains confidential and proprietary information
|
// This file contains confidential and proprietary information
|
// of Xilinx, Inc. and is protected under U.S. and
|
// of Xilinx, Inc. and is protected under U.S. and
|
// international copyright and other intellectual property
|
// international copyright and other intellectual property
|
// laws.
|
// laws.
|
//
|
//
|
// DISCLAIMER
|
// DISCLAIMER
|
// This disclaimer is not a license and does not grant any
|
// This disclaimer is not a license and does not grant any
|
// rights to the materials distributed herewith. Except as
|
// rights to the materials distributed herewith. Except as
|
// otherwise provided in a valid license issued to you by
|
// otherwise provided in a valid license issued to you by
|
// Xilinx, and to the maximum extent permitted by applicable
|
// Xilinx, and to the maximum extent permitted by applicable
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
// including negligence, or under any other theory of
|
// including negligence, or under any other theory of
|
// liability) for any loss or damage of any kind or nature
|
// liability) for any loss or damage of any kind or nature
|
// related to, arising under or in connection with these
|
// related to, arising under or in connection with these
|
// materials, including for any direct, or any indirect,
|
// materials, including for any direct, or any indirect,
|
// special, incidental, or consequential loss or damage
|
// special, incidental, or consequential loss or damage
|
// (including loss of data, profits, goodwill, or any type of
|
// (including loss of data, profits, goodwill, or any type of
|
// loss or damage suffered as a result of any action brought
|
// loss or damage suffered as a result of any action brought
|
// by a third party) even if such damage or loss was
|
// by a third party) even if such damage or loss was
|
// reasonably foreseeable or Xilinx had been advised of the
|
// reasonably foreseeable or Xilinx had been advised of the
|
// possibility of the same.
|
// possibility of the same.
|
//
|
//
|
// CRITICAL APPLICATIONS
|
// CRITICAL APPLICATIONS
|
// Xilinx products are not designed or intended to be fail-
|
// Xilinx products are not designed or intended to be fail-
|
// safe, or for use in any application requiring fail-safe
|
// safe, or for use in any application requiring fail-safe
|
// performance, such as life-support or safety devices or
|
// performance, such as life-support or safety devices or
|
// systems, Class III medical devices, nuclear facilities,
|
// systems, Class III medical devices, nuclear facilities,
|
// applications related to the deployment of airbags, or any
|
// applications related to the deployment of airbags, or any
|
// other applications that could lead to death, personal
|
// other applications that could lead to death, personal
|
// injury, or severe property or environmental damage
|
// injury, or severe property or environmental damage
|
// (individually and collectively, "Critical
|
// (individually and collectively, "Critical
|
// Applications"). Customer assumes the sole risk and
|
// Applications"). Customer assumes the sole risk and
|
// liability of any use of Xilinx products in Critical
|
// liability of any use of Xilinx products in Critical
|
// Applications, subject only to applicable laws and
|
// Applications, subject only to applicable laws and
|
// regulations governing limitations on product liability.
|
// regulations governing limitations on product liability.
|
//
|
//
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
// PART OF THIS FILE AT ALL TIMES.
|
// PART OF THIS FILE AT ALL TIMES.
|
//
|
//
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Project : Series-7 Integrated Block for PCI Express
|
// Project : Series-7 Integrated Block for PCI Express
|
// File : cl_a7pcie_x4_pipe_wrapper.v
|
// File : cl_a7pcie_x4_pipe_wrapper.v
|
// Version : 1.9
|
// Version : 1.10
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
// Filename : pipe_wrapper.v
|
// Filename : pipe_wrapper.v
|
// Description : PIPE Wrapper for 7 Series Transceiver
|
// Description : PIPE Wrapper for 7 Series Transceiver
|
// Version : 20.1
|
// Version : 20.2
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
|
|
//---------- PIPE Wrapper Hierarchy --------------------------------------------
|
//---------- PIPE Wrapper Hierarchy --------------------------------------------
|
// pipe_wrapper.v
|
// pipe_wrapper.v
|
// pipe_clock.v
|
// pipe_clock.v
|
// pipe_reset.v or gtp_pipe_reset.v
|
// pipe_reset.v or gtp_pipe_reset.v
|
// qpll_reset.v
|
// qpll_reset.v
|
// * Generate GTXE2_CHANNEL for every lane.
|
// * Generate GTXE2_CHANNEL for every lane.
|
// pipe_user.v
|
// pipe_user.v
|
// pipe_rate.v or gtp_pipe_rate.v
|
// pipe_rate.v or gtp_pipe_rate.v
|
// pipe_sync.v
|
// pipe_sync.v
|
// pipe_drp.v or gtp_pipe_drp.v
|
// pipe_drp.v or gtp_pipe_drp.v
|
// pipe_eq.v
|
// pipe_eq.v
|
// rxeq_scan.v
|
// rxeq_scan.v
|
// gt_wrapper.v
|
// gt_wrapper.v
|
// GTXE2_CHANNEL or GTHE2_CHANNEL or GTPE2_CHANNEL
|
// GTXE2_CHANNEL or GTHE2_CHANNEL or GTPE2_CHANNEL
|
// GTXE2_COMMON or GTHE2_COMMON or GTPE2_CHANNEL
|
// GTXE2_COMMON or GTHE2_COMMON or GTPE2_CHANNEL
|
// * Generate GTXE2_COMMON for every quad.
|
// * Generate GTXE2_COMMON for every quad.
|
// qpll_drp.v
|
// qpll_drp.v
|
// qpll_wrapper.v
|
// qpll_wrapper.v
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
|
|
//---------- PIPE Wrapper Parameter Encoding -----------------------------------
|
//---------- PIPE Wrapper Parameter Encoding -----------------------------------
|
// PCIE_SIM_MODE : "FALSE" = Normal mode (default)
|
// PCIE_SIM_MODE : "FALSE" = Normal mode (default)
|
// : "TRUE" = Simulation only
|
// : "TRUE" = Simulation only
|
// PCIE_SIM_TX_EIDLE_DRIVE_LEVEL : "0", "1" (default), "X" simulation TX electrical idle drive level
|
// PCIE_SIM_TX_EIDLE_DRIVE_LEVEL : "0", "1" (default), "X" simulation TX electrical idle drive level
|
// PCIE_GT_DEVICE : "GTX" (default)
|
// PCIE_GT_DEVICE : "GTX" (default)
|
// : "GTH"
|
// : "GTH"
|
// : "GTP"
|
// : "GTP"
|
// PCIE_USE_MODE : "1.0" = GTX IES 325T or GTP IES/GES use mode.
|
// PCIE_USE_MODE : "1.0" = GTX IES 325T or GTP IES/GES use mode.
|
// : "1.1" = GTX IES 485T use mode.
|
// : "1.1" = GTX IES 485T use mode.
|
// : "2.0" = GTH IES 690T use mode for 1.0 silicon.
|
// : "2.0" = GTH IES 690T use mode for 1.0 silicon.
|
// : "2.1" = GTH GES 690T use mode for 1.2 and 2.0 silicon. SW model use "2.0"
|
// : "2.1" = GTH GES 690T use mode for 1.2 and 2.0 silicon. SW model use "2.0"
|
// : "3.0" = GTX GES 325T or 485T use mode (default).
|
// : "3.0" = GTX GES 325T or 485T use mode (default).
|
// PCIE_PLL_SEL : "CPLL" (default)
|
// PCIE_PLL_SEL : "CPLL" (default)
|
// : "QPLL"
|
// : "QPLL"
|
// PCIE_AUX_CDR_GEN3_EN : "FALSE" Use Primary CDR for Gen3 only (GTH 2.0)
|
// PCIE_AUX_CDR_GEN3_EN : "FALSE" Use Primary CDR for Gen3 only (GTH 2.0)
|
// : "TRUE" Use AUX CDR for Gen3 only (default) (GTH 2.0)
|
// : "TRUE" Use AUX CDR for Gen3 only (default) (GTH 2.0)
|
// PCIE_LPM_DFE : "DFE" for Gen1/Gen2 only (GTX, GTH)
|
// PCIE_LPM_DFE : "DFE" for Gen1/Gen2 only (GTX, GTH)
|
// : "LPM" for Gen1/Gen2 only (default) (GTX, GTH)
|
// : "LPM" for Gen1/Gen2 only (default) (GTX, GTH)
|
// PCIE_LPM_DFE_GEN3 : "DFE" for Gen3 only (GTX, GTH)
|
// PCIE_LPM_DFE_GEN3 : "DFE" for Gen3 only (GTX, GTH)
|
// : "LPM" for Gen3 only (default) (GTX, GTH)
|
// : "LPM" for Gen3 only (default) (GTX, GTH)
|
// PCIE_EXT_CLK : "FALSE" = Use internal clock module(default)
|
// PCIE_EXT_CLK : "FALSE" = Use internal clock module(default)
|
// : "TRUE" = Use external clock module
|
// : "TRUE" = Use external clock module
|
// PCIE_POWER_SAVING : "FALSE" = Disable PLL power saving
|
// PCIE_POWER_SAVING : "FALSE" = Disable PLL power saving
|
// : "TRUE" = Enable PLL power saving (default)
|
// : "TRUE" = Enable PLL power saving (default)
|
// PCIE_ASYNC_EN : "FALSE" = Synchronous mode (default)
|
// PCIE_ASYNC_EN : "FALSE" = Synchronous mode (default)
|
// : "TRUE" = Asynchronous mode.
|
// : "TRUE" = Asynchronous mode.
|
// PCIE_TXBUF_EN : "FALSE" = TX buffer bypass for Gen1/Gen2 only (default)
|
// PCIE_TXBUF_EN : "FALSE" = TX buffer bypass for Gen1/Gen2 only (default)
|
// : "TRUE" = TX buffer use for Gen1/Gen2 only (for debug only)
|
// : "TRUE" = TX buffer use for Gen1/Gen2 only (for debug only)
|
// PCIE_RXBUF_EN : "FALSE" = RX buffer bypass for Gen3 only (not supported)
|
// PCIE_RXBUF_EN : "FALSE" = RX buffer bypass for Gen3 only (not supported)
|
// : "TRUE" = RX buffer use for Gen3 only (default)
|
// : "TRUE" = RX buffer use for Gen3 only (default)
|
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default) (GTX, GTH)
|
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default) (GTX, GTH)
|
// : 1 = Auto TX sync (GTH)
|
// : 1 = Auto TX sync (GTH)
|
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default) (GTX, GTH)
|
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default) (GTX, GTH)
|
// : 1 = Auto RX sync (GTH)
|
// : 1 = Auto RX sync (GTH)
|
// PCIE_CHAN_BOND : 0 = One-Hop (default)
|
// PCIE_CHAN_BOND : 0 = One-Hop (default)
|
// : 1 = Daisy-Chain
|
// : 1 = Daisy-Chain
|
// : 2 = Binary-Tree
|
// : 2 = Binary-Tree
|
// PCIE_CHAN_BOND_EN : "FALSE" = Channel bonding disable for Gen1/Gen2 only
|
// PCIE_CHAN_BOND_EN : "FALSE" = Channel bonding disable for Gen1/Gen2 only
|
// : "TRUE" = Channel bonding enable for Gen1/Gen2 only
|
// : "TRUE" = Channel bonding enable for Gen1/Gen2 only
|
// PCIE_LANE : 1 (default), 2, 4, or 8
|
// PCIE_LANE : 1 (default), 2, 4, or 8
|
// PCIE_LINK_SPEED : 1 = PCIe Gen1 Mode
|
// PCIE_LINK_SPEED : 1 = PCIe Gen1 Mode
|
// : 2 = PCIe Gen1/Gen2 Mode (default)
|
// : 2 = PCIe Gen1/Gen2 Mode (default)
|
// : 3 = PCIe Gen1/Gen2/Gen3 Mode
|
// : 3 = PCIe Gen1/Gen2/Gen3 Mode
|
// PCIE_REFCLK_FREQ : 0 = 100 MHz (default)
|
// PCIE_REFCLK_FREQ : 0 = 100 MHz (default)
|
// : 1 = 125 MHz
|
// : 1 = 125 MHz
|
// : 2 = 250 MHz
|
// : 2 = 250 MHz
|
// PCIE_USERCLK[1/2]_FREQ : 0 = Disable user clock
|
// PCIE_USERCLK[1/2]_FREQ : 0 = Disable user clock
|
// : 1 = 31.25 MHz
|
// : 1 = 31.25 MHz
|
// : 2 = 62.50 MHz (default)
|
// : 2 = 62.50 MHz (default)
|
// : 3 = 125.00 MHz
|
// : 3 = 125.00 MHz
|
// : 4 = 250.00 MHz
|
// : 4 = 250.00 MHz
|
// : 5 = 500.00 MHz
|
// : 5 = 500.00 MHz
|
// PCIE_TX_EIDLE_ASSERT_DELAY : 3'd0 to 3'd7 (default = 3'd4)
|
// PCIE_TX_EIDLE_ASSERT_DELAY : 3'd0 to 3'd7 (default = 3'd4)
|
// PCIE_RXEQ_MODE_GEN3 : 0 = Return same TX coefficients
|
// PCIE_RXEQ_MODE_GEN3 : 0 = Return same TX coefficients
|
// : 1 = Return TX preset #5
|
// : 1 = Return TX preset #5
|
// PCIE_OOBCLK_MODE : 0 = Reference clock
|
// PCIE_OOBCLK_MODE : 0 = Reference clock
|
// : 1 = 62.50 MHz (default)
|
// : 1 = 62.50 MHz (default)
|
// : 2 = 50.00 MHz (requires 1 BUFG)
|
// : 2 = 50.00 MHz (requires 1 BUFG)
|
// PCIE_JTAG_MODE : 0 = Normal operation (default)
|
// PCIE_JTAG_MODE : 0 = Normal operation (default)
|
// : 1 = JTAG mode (for debug only)
|
// : 1 = JTAG mode (for debug only)
|
// PCIE_DEBUG_MODE : 0 = Normal operation (default)
|
// PCIE_DEBUG_MODE : 0 = Normal operation (default)
|
// : 1 = Debug mode (for debug only)
|
// : 1 = Debug mode (for debug only)
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
|
|
//---------- Notes -------------------------------------------------------------
|
//---------- Notes -------------------------------------------------------------
|
// Notes within the PIPE Wrapper RTL files are for internal use only.
|
// Notes within the PIPE Wrapper RTL files are for internal use only.
|
// Data Width : This PIPE Wrapper supports a 32-bit [TX/RX]DATA interface.
|
// Data Width : This PIPE Wrapper supports a 32-bit [TX/RX]DATA interface.
|
// In Gen1/Gen2 modes, only 16-bits [15:0] are used.
|
// In Gen1/Gen2 modes, only 16-bits [15:0] are used.
|
// In Gen3 mode, all 32-bits are used.
|
// In Gen3 mode, all 32-bits are used.
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
|
|
|
|
|
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
|
|
|
|
|
|
//---------- PIPE Wrapper ------------------------------------------------------
|
//---------- PIPE Wrapper ------------------------------------------------------
|
module cl_a7pcie_x4_pipe_wrapper #
|
module cl_a7pcie_x4_pipe_wrapper #
|
(
|
(
|
|
|
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
|
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
|
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
|
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
|
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
|
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
|
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
|
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
|
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
|
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
|
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 (GTX/GTH) only
|
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 (GTX/GTH) only
|
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR for Gen3 (GTH 2.0) only
|
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR for Gen3 (GTH 2.0) only
|
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
|
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
|
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
|
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
|
parameter PCIE_EXT_CLK = "FALSE", // PCIe external clock
|
parameter PCIE_EXT_CLK = "FALSE", // PCIe external clock
|
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
|
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
|
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
|
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
|
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
|
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
|
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
|
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
|
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
|
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
|
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
|
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
|
parameter PCIE_CHAN_BOND = 1, // PCIe channel bonding mode
|
parameter PCIE_CHAN_BOND = 1, // PCIe channel bonding mode
|
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
|
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
|
parameter PCIE_LANE = 1, // PCIe number of lanes
|
parameter PCIE_LANE = 1, // PCIe number of lanes
|
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
|
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
|
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
|
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
|
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
|
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
|
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
|
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
|
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
|
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
|
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
|
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
|
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
|
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
|
parameter PCIE_JTAG_MODE = 0, // PCIe JTAG mode
|
parameter PCIE_JTAG_MODE = 0, // PCIe JTAG mode
|
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
|
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
|
|
|
)
|
)
|
//--------------------------------------
|
//--------------------------------------
|
( // Gen1/Gen2 | Gen3
|
( // Gen1/Gen2 | Gen3
|
//--------------------------------------
|
//--------------------------------------
|
//---------- PIPE Clock & Reset Ports ------------------
|
//---------- PIPE Clock & Reset Ports ------------------
|
input PIPE_CLK, // Reference clock that drives MMCM
|
input PIPE_CLK, // Reference clock that drives MMCM
|
input PIPE_RESET_N, // PCLK | PCLK
|
input PIPE_RESET_N, // PCLK | PCLK
|
|
|
output PIPE_PCLK, // Drives [TX/RX]USRCLK in Gen1/Gen2
|
output PIPE_PCLK, // Drives [TX/RX]USRCLK in Gen1/Gen2
|
// Drives TXUSRCLK in Gen3
|
// Drives TXUSRCLK in Gen3
|
// Drives RXUSRCLK in Gen3 async mode only
|
// Drives RXUSRCLK in Gen3 async mode only
|
//---------- PIPE TX Data Ports ------------------------
|
//---------- PIPE TX Data Ports ------------------------
|
input [(PCIE_LANE*32)-1:0]PIPE_TXDATA, // PCLK | PCLK
|
input [(PCIE_LANE*32)-1:0]PIPE_TXDATA, // PCLK | PCLK
|
input [(PCIE_LANE*4)-1:0] PIPE_TXDATAK, // PCLK | PCLK
|
input [(PCIE_LANE*4)-1:0] PIPE_TXDATAK, // PCLK | PCLK
|
|
|
output [PCIE_LANE-1:0] PIPE_TXP, // Serial data
|
output [PCIE_LANE-1:0] PIPE_TXP, // Serial data
|
output [PCIE_LANE-1:0] PIPE_TXN, // Serial data
|
output [PCIE_LANE-1:0] PIPE_TXN, // Serial data
|
|
|
//---------- PIPE RX Data Ports ------------------------
|
//---------- PIPE RX Data Ports ------------------------
|
input [PCIE_LANE-1:0] PIPE_RXP, // Serial data
|
input [PCIE_LANE-1:0] PIPE_RXP, // Serial data
|
input [PCIE_LANE-1:0] PIPE_RXN, // Serial data
|
input [PCIE_LANE-1:0] PIPE_RXN, // Serial data
|
|
|
output [(PCIE_LANE*32)-1:0]PIPE_RXDATA, // PCLK | RXUSRCLK
|
output [(PCIE_LANE*32)-1:0]PIPE_RXDATA, // PCLK | RXUSRCLK
|
output [(PCIE_LANE*4)-1:0] PIPE_RXDATAK, // PCLK | RXUSRCLK
|
output [(PCIE_LANE*4)-1:0] PIPE_RXDATAK, // PCLK | RXUSRCLK
|
|
|
//---------- PIPE Command Ports ------------------------
|
//---------- PIPE Command Ports ------------------------
|
input PIPE_TXDETECTRX, // PCLK | PCLK
|
input PIPE_TXDETECTRX, // PCLK | PCLK
|
input [PCIE_LANE-1:0] PIPE_TXELECIDLE, // PCLK | PCLK
|
input [PCIE_LANE-1:0] PIPE_TXELECIDLE, // PCLK | PCLK
|
input [PCIE_LANE-1:0] PIPE_TXCOMPLIANCE, // PCLK | PCLK
|
input [PCIE_LANE-1:0] PIPE_TXCOMPLIANCE, // PCLK | PCLK
|
input [PCIE_LANE-1:0] PIPE_RXPOLARITY, // PCLK | RXUSRCLK
|
input [PCIE_LANE-1:0] PIPE_RXPOLARITY, // PCLK | RXUSRCLK
|
input [(PCIE_LANE*2)-1:0] PIPE_POWERDOWN, // PCLK | PCLK
|
input [(PCIE_LANE*2)-1:0] PIPE_POWERDOWN, // PCLK | PCLK
|
input [ 1:0] PIPE_RATE, // PCLK | PCLK
|
input [ 1:0] PIPE_RATE, // PCLK | PCLK
|
|
|
//---------- PIPE Electrical Command Ports -------------
|
//---------- PIPE Electrical Command Ports -------------
|
input [ 2:0] PIPE_TXMARGIN, // Async | Async
|
input [ 2:0] PIPE_TXMARGIN, // Async | Async
|
input PIPE_TXSWING, // Async | Async
|
input PIPE_TXSWING, // Async | Async
|
input [PCIE_LANE-1:0] PIPE_TXDEEMPH, // Async/PCLK | Async/PCLK
|
input [PCIE_LANE-1:0] PIPE_TXDEEMPH, // Async/PCLK | Async/PCLK
|
input [(PCIE_LANE*2)-1:0] PIPE_TXEQ_CONTROL, // PCLK | PCLK
|
input [(PCIE_LANE*2)-1:0] PIPE_TXEQ_CONTROL, // PCLK | PCLK
|
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET, // PCLK | PCLK
|
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET, // PCLK | PCLK
|
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET_DEFAULT,// PCLK | PCLK
|
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET_DEFAULT,// PCLK | PCLK
|
input [(PCIE_LANE*6)-1:0] PIPE_TXEQ_DEEMPH, // PCLK | PCLK
|
input [(PCIE_LANE*6)-1:0] PIPE_TXEQ_DEEMPH, // PCLK | PCLK
|
|
|
input [(PCIE_LANE*2)-1:0] PIPE_RXEQ_CONTROL, // PCLK | PCLK
|
input [(PCIE_LANE*2)-1:0] PIPE_RXEQ_CONTROL, // PCLK | PCLK
|
input [(PCIE_LANE*3)-1:0] PIPE_RXEQ_PRESET, // PCLK | PCLK
|
input [(PCIE_LANE*3)-1:0] PIPE_RXEQ_PRESET, // PCLK | PCLK
|
input [(PCIE_LANE*6)-1:0] PIPE_RXEQ_LFFS, // PCLK | PCLK
|
input [(PCIE_LANE*6)-1:0] PIPE_RXEQ_LFFS, // PCLK | PCLK
|
input [(PCIE_LANE*4)-1:0] PIPE_RXEQ_TXPRESET, // PCLK | PCLK
|
input [(PCIE_LANE*4)-1:0] PIPE_RXEQ_TXPRESET, // PCLK | PCLK
|
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_EN, // PCLK | PCLK
|
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_EN, // PCLK | PCLK
|
input [(PCIE_LANE*18)-1:0]PIPE_RXEQ_USER_TXCOEFF, // PCLK | PCLK
|
input [(PCIE_LANE*18)-1:0]PIPE_RXEQ_USER_TXCOEFF, // PCLK | PCLK
|
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_MODE, // PCLK | PCLK
|
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_MODE, // PCLK | PCLK
|
|
|
output [ 5:0] PIPE_TXEQ_FS, // Async | Async
|
output [ 5:0] PIPE_TXEQ_FS, // Async | Async
|
output [ 5:0] PIPE_TXEQ_LF, // Async | Async
|
output [ 5:0] PIPE_TXEQ_LF, // Async | Async
|
output [(PCIE_LANE*18)-1:0]PIPE_TXEQ_COEFF, // PCLK | PCLK
|
output [(PCIE_LANE*18)-1:0]PIPE_TXEQ_COEFF, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_TXEQ_DONE, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_TXEQ_DONE, // PCLK | PCLK
|
|
|
output [(PCIE_LANE*18)-1:0]PIPE_RXEQ_NEW_TXCOEFF, // PCLK | PCLK
|
output [(PCIE_LANE*18)-1:0]PIPE_RXEQ_NEW_TXCOEFF, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_RXEQ_LFFS_SEL, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_RXEQ_LFFS_SEL, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_RXEQ_ADAPT_DONE, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_RXEQ_ADAPT_DONE, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_RXEQ_DONE, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_RXEQ_DONE, // PCLK | PCLK
|
// output [PCIE_LANE-1:0] PIPE_RXEQ_CONVERGE, // PCLK | PCLK
|
// output [PCIE_LANE-1:0] PIPE_RXEQ_CONVERGE, // PCLK | PCLK
|
|
|
//---------- PIPE Status Ports -------------------------
|
//---------- PIPE Status Ports -------------------------
|
output [PCIE_LANE-1:0] PIPE_RXVALID, // PCLK | RXUSRCLK
|
output [PCIE_LANE-1:0] PIPE_RXVALID, // PCLK | RXUSRCLK
|
output [PCIE_LANE-1:0] PIPE_PHYSTATUS, // PCLK | RXUSRCLK
|
output [PCIE_LANE-1:0] PIPE_PHYSTATUS, // PCLK | RXUSRCLK
|
output [PCIE_LANE-1:0] PIPE_PHYSTATUS_RST, // PCLK | RXUSRCLK
|
output [PCIE_LANE-1:0] PIPE_PHYSTATUS_RST, // PCLK | RXUSRCLK
|
output [PCIE_LANE-1:0] PIPE_RXELECIDLE, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_RXELECIDLE, // Async | Async
|
output [(PCIE_LANE*3)-1:0] PIPE_RXSTATUS, // PCLK | RXUSRCLK
|
output [(PCIE_LANE*3)-1:0] PIPE_RXSTATUS, // PCLK | RXUSRCLK
|
output [(PCIE_LANE*3)-1:0] PIPE_RXBUFSTATUS, // PCLK | RXUSRCLK
|
output [(PCIE_LANE*3)-1:0] PIPE_RXBUFSTATUS, // PCLK | RXUSRCLK
|
|
|
//---------- PIPE User Ports ---------------------------
|
//---------- PIPE User Ports ---------------------------
|
input PIPE_MMCM_RST_N, // Async | Async
|
input PIPE_MMCM_RST_N, // Async | Async
|
input [PCIE_LANE-1:0] PIPE_RXSLIDE, // PCLK | RXUSRCLK
|
input [PCIE_LANE-1:0] PIPE_RXSLIDE, // PCLK | RXUSRCLK
|
|
|
output [PCIE_LANE-1:0] PIPE_CPLL_LOCK, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_CPLL_LOCK, // Async | Async
|
output [(PCIE_LANE-1)>>2:0]PIPE_QPLL_LOCK, // Async | Async
|
output [(PCIE_LANE-1)>>2:0]PIPE_QPLL_LOCK, // Async | Async
|
output PIPE_PCLK_LOCK, // Async | Async
|
output PIPE_PCLK_LOCK, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_RXCDRLOCK, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_RXCDRLOCK, // Async | Async
|
output PIPE_USERCLK1, // Optional user clock
|
output PIPE_USERCLK1, // Optional user clock
|
output PIPE_USERCLK2, // Optional user clock
|
output PIPE_USERCLK2, // Optional user clock
|
output PIPE_RXUSRCLK, // RXUSRCLK
|
output PIPE_RXUSRCLK, // RXUSRCLK
|
// Equivalent to PCLK in Gen1/Gen2
|
// Equivalent to PCLK in Gen1/Gen2
|
// Equivalent to RXOUTCLK[0] in Gen3
|
// Equivalent to RXOUTCLK[0] in Gen3
|
output [PCIE_LANE-1:0] PIPE_RXOUTCLK, // RX recovered clock (for debug only)
|
output [PCIE_LANE-1:0] PIPE_RXOUTCLK, // RX recovered clock (for debug only)
|
output [PCIE_LANE-1:0] PIPE_TXSYNC_DONE, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_TXSYNC_DONE, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_RXSYNC_DONE, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_RXSYNC_DONE, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_GEN3_RDY, // PCLK | RXUSRCLK
|
output [PCIE_LANE-1:0] PIPE_GEN3_RDY, // PCLK | RXUSRCLK
|
output [PCIE_LANE-1:0] PIPE_RXCHANISALIGNED,
|
output [PCIE_LANE-1:0] PIPE_RXCHANISALIGNED,
|
output [PCIE_LANE-1:0] PIPE_ACTIVE_LANE,
|
output [PCIE_LANE-1:0] PIPE_ACTIVE_LANE,
|
|
|
//---------- External Clock Ports ----------------------
|
//---------- External Clock Ports ----------------------
|
input PIPE_PCLK_IN, // PCLK | PCLK
|
input PIPE_PCLK_IN, // PCLK | PCLK
|
input PIPE_RXUSRCLK_IN, // RXUSERCLK
|
input PIPE_RXUSRCLK_IN, // RXUSERCLK
|
// Equivalent to PCLK in Gen1/Gen2
|
// Equivalent to PCLK in Gen1/Gen2
|
// Equivalent to RXOUTCLK[0] in Gen3
|
// Equivalent to RXOUTCLK[0] in Gen3
|
input [PCIE_LANE-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock
|
input [PCIE_LANE-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock
|
input PIPE_DCLK_IN, // DCLK | DCLK
|
input PIPE_DCLK_IN, // DCLK | DCLK
|
input PIPE_USERCLK1_IN, // Optional user clock
|
input PIPE_USERCLK1_IN, // Optional user clock
|
input PIPE_USERCLK2_IN, // Optional user clock
|
input PIPE_USERCLK2_IN, // Optional user clock
|
input PIPE_OOBCLK_IN, // OOB | OOB
|
input PIPE_OOBCLK_IN, // OOB | OOB
|
input PIPE_MMCM_LOCK_IN, // Async | Async
|
input PIPE_MMCM_LOCK_IN, // Async | Async
|
|
|
output PIPE_TXOUTCLK_OUT, // PCLK | PCLK
|
output PIPE_TXOUTCLK_OUT, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only)
|
output [PCIE_LANE-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only)
|
output [PCIE_LANE-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK
|
output PIPE_GEN3_OUT, // PCLK | PCLK
|
output PIPE_GEN3_OUT, // PCLK | PCLK
|
|
|
//---------- PRBS/Loopback Ports -----------------------
|
//---------- PRBS/Loopback Ports -----------------------
|
input [ 2:0] PIPE_TXPRBSSEL, // PCLK | PCLK
|
input [ 2:0] PIPE_TXPRBSSEL, // PCLK | PCLK
|
input [ 2:0] PIPE_RXPRBSSEL, // PCLK | PCLK
|
input [ 2:0] PIPE_RXPRBSSEL, // PCLK | PCLK
|
input PIPE_TXPRBSFORCEERR, // PCLK | PCLK
|
input PIPE_TXPRBSFORCEERR, // PCLK | PCLK
|
input PIPE_RXPRBSCNTRESET, // PCLK | PCLK
|
input PIPE_RXPRBSCNTRESET, // PCLK | PCLK
|
input [ 2:0] PIPE_LOOPBACK, // PCLK | PCLK
|
input [ 2:0] PIPE_LOOPBACK, // PCLK | PCLK
|
|
|
output [PCIE_LANE-1:0] PIPE_RXPRBSERR, // PCLK | PCLK
|
output [PCIE_LANE-1:0] PIPE_RXPRBSERR, // PCLK | PCLK
|
|
|
//---------- FSM Ports ---------------------------------
|
//---------- FSM Ports ---------------------------------
|
output [10:0] PIPE_RST_FSM, // PCLK | PCLK
|
output [10:0] PIPE_RST_FSM, // PCLK | PCLK
|
output [11:0] PIPE_QRST_FSM, // PCLK | PCLK
|
output [11:0] PIPE_QRST_FSM, // PCLK | PCLK
|
output [(PCIE_LANE*31)-1:0]PIPE_RATE_FSM, // PCLK | PCLK
|
output [(PCIE_LANE*31)-1:0]PIPE_RATE_FSM, // PCLK | PCLK
|
output [(PCIE_LANE*6)-1:0] PIPE_SYNC_FSM_TX, // PCLK | PCLK
|
output [(PCIE_LANE*6)-1:0] PIPE_SYNC_FSM_TX, // PCLK | PCLK
|
output [(PCIE_LANE*7)-1:0] PIPE_SYNC_FSM_RX, // PCLK | PCLK
|
output [(PCIE_LANE*7)-1:0] PIPE_SYNC_FSM_RX, // PCLK | PCLK
|
output [(PCIE_LANE*7)-1:0] PIPE_DRP_FSM, // DCLK | DCLK
|
output [(PCIE_LANE*7)-1:0] PIPE_DRP_FSM, // DCLK | DCLK
|
output [(PCIE_LANE*6)-1:0] PIPE_TXEQ_FSM, // PCLK | PCLK
|
output [(PCIE_LANE*6)-1:0] PIPE_TXEQ_FSM, // PCLK | PCLK
|
output [(PCIE_LANE*6)-1:0] PIPE_RXEQ_FSM, // PCLK | PCLK
|
output [(PCIE_LANE*6)-1:0] PIPE_RXEQ_FSM, // PCLK | PCLK
|
output [((((PCIE_LANE-1)>>2)+1)*9)-1:0]PIPE_QDRP_FSM, // DCLK | DCLK
|
output [((((PCIE_LANE-1)>>2)+1)*9)-1:0]PIPE_QDRP_FSM, // DCLK | DCLK
|
|
|
output PIPE_RST_IDLE, // PCLK | PCLK
|
output PIPE_RST_IDLE, // PCLK | PCLK
|
output PIPE_QRST_IDLE, // PCLK | PCLK
|
output PIPE_QRST_IDLE, // PCLK | PCLK
|
output PIPE_RATE_IDLE, // PCLK | PCLK
|
output PIPE_RATE_IDLE, // PCLK | PCLK
|
|
|
//---------- JTAG Ports --------------------------------
|
//---------- JTAG Ports --------------------------------
|
input PIPE_JTAG_EN, // DCLK | DCLK
|
input PIPE_JTAG_EN, // DCLK | DCLK
|
output [PCIE_LANE-1:0] PIPE_JTAG_RDY, // DCLK | DCLK
|
output [PCIE_LANE-1:0] PIPE_JTAG_RDY, // DCLK | DCLK
|
|
|
//---------- Debug Ports -------------------------------
|
//---------- Debug Ports -------------------------------
|
output [PCIE_LANE-1:0] PIPE_DEBUG_0, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_0, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_1, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_1, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_2, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_2, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_3, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_3, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_4, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_4, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_5, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_5, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_6, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_6, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_7, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_7, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_8, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_8, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_9, // Async | Async
|
output [PCIE_LANE-1:0] PIPE_DEBUG_9, // Async | Async
|
output [31:0] PIPE_DEBUG, // Async | Async
|
output [31:0] PIPE_DEBUG, // Async | Async
|
|
|
output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK
|
output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK
|
|
|
);
|
);
|
|
|
//---------- Input Registers ---------------------------
|
//---------- Input Registers ---------------------------
|
reg reset_n_reg1;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg1;
|
reg reset_n_reg2;
|
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg2;
|
|
|
//---------- PIPE Clock Module Output ------------------
|
//---------- PIPE Clock Module Output ------------------
|
wire clk_pclk;
|
wire clk_pclk;
|
wire clk_rxusrclk;
|
wire clk_rxusrclk;
|
wire [PCIE_LANE-1:0] clk_rxoutclk;
|
wire [PCIE_LANE-1:0] clk_rxoutclk;
|
wire clk_dclk;
|
wire clk_dclk;
|
wire clk_oobclk;
|
wire clk_oobclk;
|
wire clk_mmcm_lock;
|
wire clk_mmcm_lock;
|
|
|
//---------- PIPE Reset Module Output ------------------
|
//---------- PIPE Reset Module Output ------------------
|
wire rst_cpllreset;
|
wire rst_cpllreset;
|
wire rst_cpllpd;
|
wire rst_cpllpd;
|
wire rst_rxusrclk_reset;
|
wire rst_rxusrclk_reset;
|
wire rst_dclk_reset;
|
wire rst_dclk_reset;
|
wire rst_gtreset;
|
wire rst_gtreset;
|
wire rst_drp_start;
|
wire rst_drp_start;
|
wire rst_drp_x16x20_mode;
|
wire rst_drp_x16x20_mode;
|
wire rst_drp_x16;
|
wire rst_drp_x16;
|
wire rst_userrdy;
|
wire rst_userrdy;
|
wire rst_txsync_start;
|
wire rst_txsync_start;
|
wire rst_idle;
|
wire rst_idle;
|
wire [ 4:0] rst_fsm;
|
wire [ 4:0] rst_fsm;
|
|
|
//------------------------------------------------------
|
//------------------------------------------------------
|
wire gtp_rst_qpllreset; // GTP
|
wire gtp_rst_qpllreset; // GTP
|
wire gtp_rst_qpllpd; // GTP
|
wire gtp_rst_qpllpd; // GTP
|
|
|
//------------------------------------------------------
|
//------------------------------------------------------
|
wire [(PCIE_LANE-1)>>2:0]qpllreset;
|
wire [(PCIE_LANE-1)>>2:0]qpllreset;
|
wire qpllpd;
|
wire qpllpd;
|
|
|
//---------- QPLL Reset Module Output ------------------
|
//---------- QPLL Reset Module Output ------------------
|
wire qrst_ovrd;
|
wire qrst_ovrd;
|
wire qrst_drp_start;
|
wire qrst_drp_start;
|
wire qrst_qpllreset;
|
wire qrst_qpllreset;
|
wire qrst_qpllpd;
|
wire qrst_qpllpd;
|
wire qrst_idle;
|
wire qrst_idle;
|
wire [ 3:0] qrst_fsm;
|
wire [ 3:0] qrst_fsm;
|
|
|
//---------- PIPE_JTAG Master Module Output ------------
|
//---------- PIPE_JTAG Master Module Output ------------
|
wire [(PCIE_LANE*37)-1:0] jtag_sl_iport;
|
wire [(PCIE_LANE*37)-1:0] jtag_sl_iport;
|
wire [(PCIE_LANE*17)-1:0] jtag_sl_oport;
|
wire [(PCIE_LANE*17)-1:0] jtag_sl_oport;
|
|
|
//---------- PIPE User Module Output -------------------
|
//---------- PIPE User Module Output -------------------
|
wire [PCIE_LANE-1:0] user_oobclk;
|
wire [PCIE_LANE-1:0] user_oobclk;
|
wire [PCIE_LANE-1:0] user_resetovrd;
|
wire [PCIE_LANE-1:0] user_resetovrd;
|
wire [PCIE_LANE-1:0] user_txpmareset;
|
wire [PCIE_LANE-1:0] user_txpmareset;
|
wire [PCIE_LANE-1:0] user_rxpmareset;
|
wire [PCIE_LANE-1:0] user_rxpmareset;
|
wire [PCIE_LANE-1:0] user_rxcdrreset;
|
wire [PCIE_LANE-1:0] user_rxcdrreset;
|
wire [PCIE_LANE-1:0] user_rxcdrfreqreset;
|
wire [PCIE_LANE-1:0] user_rxcdrfreqreset;
|
wire [PCIE_LANE-1:0] user_rxdfelpmreset;
|
wire [PCIE_LANE-1:0] user_rxdfelpmreset;
|
wire [PCIE_LANE-1:0] user_eyescanreset;
|
wire [PCIE_LANE-1:0] user_eyescanreset;
|
wire [PCIE_LANE-1:0] user_txpcsreset;
|
wire [PCIE_LANE-1:0] user_txpcsreset;
|
wire [PCIE_LANE-1:0] user_rxpcsreset;
|
wire [PCIE_LANE-1:0] user_rxpcsreset;
|
wire [PCIE_LANE-1:0] user_rxbufreset;
|
wire [PCIE_LANE-1:0] user_rxbufreset;
|
wire [PCIE_LANE-1:0] user_resetovrd_done;
|
wire [PCIE_LANE-1:0] user_resetovrd_done;
|
wire [PCIE_LANE-1:0] user_active_lane;
|
wire [PCIE_LANE-1:0] user_active_lane;
|
wire [PCIE_LANE-1:0] user_resetdone /* synthesis syn_keep=1 */;
|
wire [PCIE_LANE-1:0] user_resetdone /* synthesis syn_keep=1 */;
|
wire [PCIE_LANE-1:0] user_rxcdrlock;
|
wire [PCIE_LANE-1:0] user_rxcdrlock;
|
wire [PCIE_LANE-1:0] user_rx_converge;
|
wire [PCIE_LANE-1:0] user_rx_converge;
|
|
|
//---------- PIPE Rate Module Output -------------------
|
//---------- PIPE Rate Module Output -------------------
|
wire [PCIE_LANE-1:0] rate_cpllpd;
|
wire [PCIE_LANE-1:0] rate_cpllpd;
|
wire [PCIE_LANE-1:0] rate_qpllpd;
|
wire [PCIE_LANE-1:0] rate_qpllpd;
|
wire [PCIE_LANE-1:0] rate_cpllreset;
|
wire [PCIE_LANE-1:0] rate_cpllreset;
|
wire [PCIE_LANE-1:0] rate_qpllreset;
|
wire [PCIE_LANE-1:0] rate_qpllreset;
|
wire [PCIE_LANE-1:0] rate_txpmareset;
|
wire [PCIE_LANE-1:0] rate_txpmareset;
|
wire [PCIE_LANE-1:0] rate_rxpmareset;
|
wire [PCIE_LANE-1:0] rate_rxpmareset;
|
wire [(PCIE_LANE*2)-1:0] rate_sysclksel;
|
wire [(PCIE_LANE*2)-1:0] rate_sysclksel;
|
wire [PCIE_LANE-1:0] rate_pclk_sel;
|
wire [PCIE_LANE-1:0] rate_pclk_sel;
|
wire [PCIE_LANE-1:0] rate_drp_start;
|
wire [PCIE_LANE-1:0] rate_drp_start;
|
wire [PCIE_LANE-1:0] rate_drp_x16x20_mode;
|
wire [PCIE_LANE-1:0] rate_drp_x16x20_mode;
|
wire [PCIE_LANE-1:0] rate_drp_x16;
|
wire [PCIE_LANE-1:0] rate_drp_x16;
|
wire [PCIE_LANE-1:0] rate_gen3;
|
wire [PCIE_LANE-1:0] rate_gen3;
|
wire [(PCIE_LANE*3)-1:0] rate_rate;
|
wire [(PCIE_LANE*3)-1:0] rate_rate;
|
wire [PCIE_LANE-1:0] rate_resetovrd_start;
|
wire [PCIE_LANE-1:0] rate_resetovrd_start;
|
wire [PCIE_LANE-1:0] rate_txsync_start;
|
wire [PCIE_LANE-1:0] rate_txsync_start;
|
wire [PCIE_LANE-1:0] rate_done;
|
wire [PCIE_LANE-1:0] rate_done;
|
wire [PCIE_LANE-1:0] rate_rxsync_start;
|
wire [PCIE_LANE-1:0] rate_rxsync_start;
|
wire [PCIE_LANE-1:0] rate_rxsync;
|
wire [PCIE_LANE-1:0] rate_rxsync;
|
wire [PCIE_LANE-1:0] rate_idle;
|
wire [PCIE_LANE-1:0] rate_idle;
|
wire [(PCIE_LANE*5)-1:0]rate_fsm;
|
wire [(PCIE_LANE*5)-1:0]rate_fsm;
|
|
|
//---------- PIPE Sync Module Output -------------------
|
//---------- PIPE Sync Module Output -------------------
|
wire [PCIE_LANE-1:0] sync_txphdlyreset;
|
wire [PCIE_LANE-1:0] sync_txphdlyreset;
|
wire [PCIE_LANE-1:0] sync_txphalign;
|
wire [PCIE_LANE-1:0] sync_txphalign;
|
wire [PCIE_LANE-1:0] sync_txphalignen;
|
wire [PCIE_LANE-1:0] sync_txphalignen;
|
wire [PCIE_LANE-1:0] sync_txphinit;
|
wire [PCIE_LANE-1:0] sync_txphinit;
|
wire [PCIE_LANE-1:0] sync_txdlybypass;
|
wire [PCIE_LANE-1:0] sync_txdlybypass;
|
wire [PCIE_LANE-1:0] sync_txdlysreset;
|
wire [PCIE_LANE-1:0] sync_txdlysreset;
|
wire [PCIE_LANE-1:0] sync_txdlyen;
|
wire [PCIE_LANE-1:0] sync_txdlyen;
|
wire [PCIE_LANE-1:0] sync_txsync_done;
|
wire [PCIE_LANE-1:0] sync_txsync_done;
|
wire [(PCIE_LANE*6)-1:0] sync_fsm_tx;
|
wire [(PCIE_LANE*6)-1:0] sync_fsm_tx;
|
|
|
wire [PCIE_LANE-1:0] sync_rxphalign;
|
wire [PCIE_LANE-1:0] sync_rxphalign;
|
wire [PCIE_LANE-1:0] sync_rxphalignen;
|
wire [PCIE_LANE-1:0] sync_rxphalignen;
|
wire [PCIE_LANE-1:0] sync_rxdlybypass;
|
wire [PCIE_LANE-1:0] sync_rxdlybypass;
|
wire [PCIE_LANE-1:0] sync_rxdlysreset;
|
wire [PCIE_LANE-1:0] sync_rxdlysreset;
|
wire [PCIE_LANE-1:0] sync_rxdlyen;
|
wire [PCIE_LANE-1:0] sync_rxdlyen;
|
wire [PCIE_LANE-1:0] sync_rxddien;
|
wire [PCIE_LANE-1:0] sync_rxddien;
|
wire [PCIE_LANE-1:0] sync_rxsync_done;
|
wire [PCIE_LANE-1:0] sync_rxsync_done;
|
wire [PCIE_LANE-1:0] sync_rxsync_donem;
|
wire [PCIE_LANE-1:0] sync_rxsync_donem;
|
wire [(PCIE_LANE*7)-1:0] sync_fsm_rx;
|
wire [(PCIE_LANE*7)-1:0] sync_fsm_rx;
|
|
|
wire [PCIE_LANE-1:0] txdlysresetdone;
|
wire [PCIE_LANE-1:0] txdlysresetdone;
|
wire [PCIE_LANE-1:0] txphaligndone;
|
wire [PCIE_LANE-1:0] txphaligndone;
|
wire [PCIE_LANE-1:0] rxdlysresetdone;
|
wire [PCIE_LANE-1:0] rxdlysresetdone;
|
wire [PCIE_LANE-1:0] rxphaligndone_s;
|
wire [PCIE_LANE-1:0] rxphaligndone_s;
|
|
|
wire txsyncallin; // GTH
|
wire txsyncallin; // GTH
|
wire rxsyncallin; // GTH
|
wire rxsyncallin; // GTH
|
|
|
//---------- PIPE DRP Module Output --------------------
|
//---------- PIPE DRP Module Output --------------------
|
wire [(PCIE_LANE*9)-1:0] drp_addr;
|
wire [(PCIE_LANE*9)-1:0] drp_addr;
|
wire [PCIE_LANE-1:0] drp_en;
|
wire [PCIE_LANE-1:0] drp_en;
|
wire [(PCIE_LANE*16)-1:0]drp_di;
|
wire [(PCIE_LANE*16)-1:0]drp_di;
|
wire [PCIE_LANE-1:0] drp_we;
|
wire [PCIE_LANE-1:0] drp_we;
|
wire [PCIE_LANE-1:0] drp_done;
|
wire [PCIE_LANE-1:0] drp_done;
|
wire [(PCIE_LANE*3)-1:0] drp_fsm;
|
wire [(PCIE_LANE*3)-1:0] drp_fsm;
|
|
|
//---------- PIPE JTAG Slave Module Output--------------
|
//---------- PIPE JTAG Slave Module Output--------------
|
wire [(PCIE_LANE*17)-1:0]jtag_sl_addr;
|
wire [(PCIE_LANE*17)-1:0]jtag_sl_addr;
|
wire [PCIE_LANE-1:0] jtag_sl_den;
|
wire [PCIE_LANE-1:0] jtag_sl_den;
|
wire [PCIE_LANE-1:0] jtag_sl_en;
|
wire [PCIE_LANE-1:0] jtag_sl_en;
|
wire [(PCIE_LANE*16)-1:0]jtag_sl_di;
|
wire [(PCIE_LANE*16)-1:0]jtag_sl_di;
|
wire [PCIE_LANE-1:0] jtag_sl_we;
|
wire [PCIE_LANE-1:0] jtag_sl_we;
|
|
|
//---------- PIPE DRP MUX Output -----------------------
|
//---------- PIPE DRP MUX Output -----------------------
|
wire [(PCIE_LANE*9)-1:0] drp_mux_addr;
|
wire [(PCIE_LANE*9)-1:0] drp_mux_addr;
|
wire [PCIE_LANE-1:0] drp_mux_en;
|
wire [PCIE_LANE-1:0] drp_mux_en;
|
wire [(PCIE_LANE*16)-1:0]drp_mux_di;
|
wire [(PCIE_LANE*16)-1:0]drp_mux_di;
|
wire [PCIE_LANE-1:0] drp_mux_we;
|
wire [PCIE_LANE-1:0] drp_mux_we;
|
|
|
//---------- PIPE EQ Module Output ---------------------
|
//---------- PIPE EQ Module Output ---------------------
|
wire [PCIE_LANE-1:0] eq_txeq_deemph;
|
wire [PCIE_LANE-1:0] eq_txeq_deemph;
|
wire [(PCIE_LANE*5)-1:0] eq_txeq_precursor;
|
wire [(PCIE_LANE*5)-1:0] eq_txeq_precursor;
|
wire [(PCIE_LANE*7)-1:0] eq_txeq_maincursor;
|
wire [(PCIE_LANE*7)-1:0] eq_txeq_maincursor;
|
wire [(PCIE_LANE*5)-1:0] eq_txeq_postcursor;
|
wire [(PCIE_LANE*5)-1:0] eq_txeq_postcursor;
|
|
|
wire [PCIE_LANE-1:0] eq_rxeq_adapt_done;
|
wire [PCIE_LANE-1:0] eq_rxeq_adapt_done;
|
|
|
//---------- PIPE DRP Module Output --------------------
|
//---------- PIPE DRP Module Output --------------------
|
wire [((((PCIE_LANE-1)>>2)+1)*8)-1:0] qdrp_addr;
|
wire [((((PCIE_LANE-1)>>2)+1)*8)-1:0] qdrp_addr;
|
wire [(PCIE_LANE-1)>>2:0] qdrp_en;
|
wire [(PCIE_LANE-1)>>2:0] qdrp_en;
|
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qdrp_di;
|
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qdrp_di;
|
wire [(PCIE_LANE-1)>>2:0] qdrp_we;
|
wire [(PCIE_LANE-1)>>2:0] qdrp_we;
|
wire [(PCIE_LANE-1)>>2:0] qdrp_done;
|
wire [(PCIE_LANE-1)>>2:0] qdrp_done;
|
wire [(PCIE_LANE-1)>>2:0] qdrp_qpllreset;
|
wire [(PCIE_LANE-1)>>2:0] qdrp_qpllreset;
|
wire [((((PCIE_LANE-1)>>2)+1)*6)-1:0] qdrp_crscode;
|
wire [((((PCIE_LANE-1)>>2)+1)*6)-1:0] qdrp_crscode;
|
wire [((((PCIE_LANE-1)>>2)+1)*9)-1:0] qdrp_fsm;
|
wire [((((PCIE_LANE-1)>>2)+1)*9)-1:0] qdrp_fsm;
|
|
|
//---------- QPLL Wrapper Output -----------------------
|
//---------- QPLL Wrapper Output -----------------------
|
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutclk;
|
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutclk;
|
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutrefclk;
|
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutrefclk;
|
wire [(PCIE_LANE-1)>>2:0] qpll_qplllock;
|
wire [(PCIE_LANE-1)>>2:0] qpll_qplllock;
|
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qpll_do;
|
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qpll_do;
|
wire [(PCIE_LANE-1)>>2:0] qpll_rdy;
|
wire [(PCIE_LANE-1)>>2:0] qpll_rdy;
|
|
|
//---------- GTX Wrapper Output ------------------------
|
//---------- GTX Wrapper Output ------------------------
|
wire [PCIE_LANE-1:0] gt_txoutclk;
|
wire [PCIE_LANE-1:0] gt_txoutclk;
|
wire [PCIE_LANE-1:0] gt_rxoutclk;
|
wire [PCIE_LANE-1:0] gt_rxoutclk;
|
wire [PCIE_LANE-1:0] gt_cplllock;
|
wire [PCIE_LANE-1:0] gt_cplllock;
|
wire [PCIE_LANE-1:0] gt_rxcdrlock;
|
wire [PCIE_LANE-1:0] gt_rxcdrlock;
|
wire [PCIE_LANE-1:0] gt_txresetdone;
|
wire [PCIE_LANE-1:0] gt_txresetdone;
|
wire [PCIE_LANE-1:0] gt_rxresetdone;
|
wire [PCIE_LANE-1:0] gt_rxresetdone;
|
wire [PCIE_LANE-1:0] gt_rxpmaresetdone;
|
wire [PCIE_LANE-1:0] gt_rxpmaresetdone;
|
wire [PCIE_LANE-1:0] gt_rxvalid;
|
wire [PCIE_LANE-1:0] gt_rxvalid;
|
wire [PCIE_LANE-1:0] gt_phystatus;
|
wire [PCIE_LANE-1:0] gt_phystatus;
|
wire [(PCIE_LANE*3)-1:0] gt_rxstatus;
|
wire [(PCIE_LANE*3)-1:0] gt_rxstatus;
|
wire [(PCIE_LANE*3)-1:0] gt_rxbufstatus;
|
wire [(PCIE_LANE*3)-1:0] gt_rxbufstatus;
|
wire [PCIE_LANE-1:0] gt_rxelecidle;
|
wire [PCIE_LANE-1:0] gt_rxelecidle;
|
wire [PCIE_LANE-1:0] gt_txratedone;
|
wire [PCIE_LANE-1:0] gt_txratedone;
|
wire [PCIE_LANE-1:0] gt_rxratedone;
|
wire [PCIE_LANE-1:0] gt_rxratedone;
|
wire [(PCIE_LANE*16)-1:0]gt_do;
|
wire [(PCIE_LANE*16)-1:0]gt_do;
|
wire [PCIE_LANE-1:0] gt_rdy;
|
wire [PCIE_LANE-1:0] gt_rdy;
|
wire [PCIE_LANE-1:0] gt_txphinitdone;
|
wire [PCIE_LANE-1:0] gt_txphinitdone;
|
wire [PCIE_LANE-1:0] gt_txdlysresetdone;
|
wire [PCIE_LANE-1:0] gt_txdlysresetdone;
|
wire [PCIE_LANE-1:0] gt_txphaligndone;
|
wire [PCIE_LANE-1:0] gt_txphaligndone;
|
wire [PCIE_LANE-1:0] gt_rxdlysresetdone;
|
wire [PCIE_LANE-1:0] gt_rxdlysresetdone;
|
wire [PCIE_LANE:0] gt_rxphaligndone; // Custom width for calculation
|
wire [PCIE_LANE:0] gt_rxphaligndone; // Custom width for calculation
|
wire [PCIE_LANE-1:0] gt_txsyncout; // GTH
|
wire [PCIE_LANE-1:0] gt_txsyncout; // GTH
|
wire [PCIE_LANE-1:0] gt_txsyncdone; // GTH
|
wire [PCIE_LANE-1:0] gt_txsyncdone; // GTH
|
wire [PCIE_LANE-1:0] gt_rxsyncout; // GTH
|
wire [PCIE_LANE-1:0] gt_rxsyncout; // GTH
|
wire [PCIE_LANE-1:0] gt_rxsyncdone; // GTH
|
wire [PCIE_LANE-1:0] gt_rxsyncdone; // GTH
|
wire [PCIE_LANE-1:0] gt_rxcommadet;
|
wire [PCIE_LANE-1:0] gt_rxcommadet;
|
wire [(PCIE_LANE*4)-1:0] gt_rxchariscomma;
|
wire [(PCIE_LANE*4)-1:0] gt_rxchariscomma;
|
wire [PCIE_LANE-1:0] gt_rxbyteisaligned;
|
wire [PCIE_LANE-1:0] gt_rxbyteisaligned;
|
wire [PCIE_LANE-1:0] gt_rxbyterealign;
|
wire [PCIE_LANE-1:0] gt_rxbyterealign;
|
wire [ 4:0] gt_rxchbondi [PCIE_LANE:0];
|
wire [ 4:0] gt_rxchbondi [PCIE_LANE:0];
|
wire [(PCIE_LANE*3)-1:0] gt_rxchbondlevel;
|
wire [(PCIE_LANE*3)-1:0] gt_rxchbondlevel;
|
wire [ 4:0] gt_rxchbondo [PCIE_LANE:0];
|
wire [ 4:0] gt_rxchbondo [PCIE_LANE:0];
|
|
|
wire [PCIE_LANE-1:0] rxchbonden;
|
wire [PCIE_LANE-1:0] rxchbonden;
|
wire [PCIE_LANE-1:0] rxchbondmaster;
|
wire [PCIE_LANE-1:0] rxchbondmaster;
|
wire [PCIE_LANE-1:0] rxchbondslave;
|
wire [PCIE_LANE-1:0] rxchbondslave;
|
wire [PCIE_LANE-1:0] oobclk;
|
wire [PCIE_LANE-1:0] oobclk;
|
|
|
//---------- TX EQ -------------------------------------
|
//---------- TX EQ -------------------------------------
|
localparam TXEQ_FS = 6'd40; // TX equalization full swing
|
localparam TXEQ_FS = 6'd40; // TX equalization full swing
|
localparam TXEQ_LF = 6'd15; // TX equalization low frequency
|
localparam TXEQ_LF = 6'd15; // TX equalization low frequency
|
|
|
//---------- Select JTAG Slave Type ----------------------------------------
|
//---------- Select JTAG Slave Type ----------------------------------------
|
localparam GC_XSDB_SLAVE_TYPE = (PCIE_GT_DEVICE == "GTP") ? 16'h0400 : (PCIE_GT_DEVICE == "GTH") ? 16'h004A : 16'h0046;
|
localparam GC_XSDB_SLAVE_TYPE = (PCIE_GT_DEVICE == "GTP") ? 16'h0400 : (PCIE_GT_DEVICE == "GTH") ? 16'h004A : 16'h0046;
|
|
|
//---------- Generate Per-Lane Signals -----------------
|
//---------- Generate Per-Lane Signals -----------------
|
genvar i; // Index for per-lane signals
|
genvar i; // Index for per-lane signals
|
|
|
|
|
|
|
//---------- Assignments -------------------------------------------------------
|
//---------- Assignments -------------------------------------------------------
|
assign gt_rxchbondo[0] = 5'd0; // Initialize rxchbond for lane 0
|
assign gt_rxchbondo[0] = 5'd0; // Initialize rxchbond for lane 0
|
assign gt_rxphaligndone[PCIE_LANE] = 1'd1; // Mot used
|
assign gt_rxphaligndone[PCIE_LANE] = 1'd1; // Mot used
|
assign txsyncallin = &(gt_txphaligndone | (~user_active_lane));
|
assign txsyncallin = &(gt_txphaligndone | (~user_active_lane));
|
assign rxsyncallin = &(gt_rxphaligndone | (~user_active_lane));
|
assign rxsyncallin = &(gt_rxphaligndone | (~user_active_lane));
|
|
|
//---------- Reset Synchronizer ------------------------------------------------
|
//---------- Reset Synchronizer ------------------------------------------------
|
always @ (posedge clk_pclk or negedge PIPE_RESET_N)
|
always @ (posedge clk_pclk or negedge PIPE_RESET_N)
|
begin
|
begin
|
|
|
if (!PIPE_RESET_N)
|
if (!PIPE_RESET_N)
|
begin
|
begin
|
reset_n_reg1 <= 1'd0;
|
reset_n_reg1 <= 1'd0;
|
reset_n_reg2 <= 1'd0;
|
reset_n_reg2 <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
reset_n_reg1 <= 1'd1;
|
reset_n_reg1 <= 1'd1;
|
reset_n_reg2 <= reset_n_reg1;
|
reset_n_reg2 <= reset_n_reg1;
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- PIPE Clock Module -------------------------------------------------
|
//---------- PIPE Clock Module -------------------------------------------------
|
generate
|
generate
|
|
|
if (PCIE_EXT_CLK == "FALSE")
|
if (PCIE_EXT_CLK == "FALSE")
|
|
|
begin : pipe_clock_int
|
begin : pipe_clock_int
|
|
|
cl_a7pcie_x4_pipe_clock #
|
cl_a7pcie_x4_pipe_clock #
|
(
|
(
|
|
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_LANE (PCIE_LANE), // PCIe number of lanes
|
.PCIE_LANE (PCIE_LANE), // PCIe number of lanes
|
.PCIE_LINK_SPEED (PCIE_LINK_SPEED), // PCIe link speed
|
.PCIE_LINK_SPEED (PCIE_LINK_SPEED), // PCIe link speed
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
|
.PCIE_USERCLK1_FREQ (PCIE_USERCLK1_FREQ), // PCIe user clock 1 frequency
|
.PCIE_USERCLK1_FREQ (PCIE_USERCLK1_FREQ), // PCIe user clock 1 frequency
|
.PCIE_USERCLK2_FREQ (PCIE_USERCLK2_FREQ), // PCIe user clock 2 frequency
|
.PCIE_USERCLK2_FREQ (PCIE_USERCLK2_FREQ), // PCIe user clock 2 frequency
|
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
|
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
|
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
|
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
|
|
|
)
|
)
|
pipe_clock_i
|
pipe_clock_i
|
(
|
(
|
|
|
//---------- Input -------------------------------------
|
//---------- Input -------------------------------------
|
.CLK_CLK (PIPE_CLK),
|
.CLK_CLK (PIPE_CLK),
|
.CLK_TXOUTCLK (gt_txoutclk[0]), // Reference clock from lane 0
|
.CLK_TXOUTCLK (gt_txoutclk[0]), // Reference clock from lane 0
|
.CLK_RXOUTCLK_IN (gt_rxoutclk),
|
.CLK_RXOUTCLK_IN (gt_rxoutclk),
|
//.CLK_RST_N (1'b1),
|
//.CLK_RST_N (1'b1),
|
.CLK_RST_N (PIPE_MMCM_RST_N), // Allow system reset for error recovery
|
.CLK_RST_N (PIPE_MMCM_RST_N), // Allow system reset for error recovery
|
.CLK_PCLK_SEL (rate_pclk_sel),
|
.CLK_PCLK_SEL (rate_pclk_sel),
|
.CLK_GEN3 (rate_gen3[0]),
|
.CLK_GEN3 (rate_gen3[0]),
|
|
|
//---------- Output ------------------------------------
|
//---------- Output ------------------------------------
|
.CLK_PCLK (clk_pclk),
|
.CLK_PCLK (clk_pclk),
|
.CLK_RXUSRCLK (clk_rxusrclk),
|
.CLK_RXUSRCLK (clk_rxusrclk),
|
.CLK_RXOUTCLK_OUT (clk_rxoutclk),
|
.CLK_RXOUTCLK_OUT (clk_rxoutclk),
|
.CLK_DCLK (clk_dclk),
|
.CLK_DCLK (clk_dclk),
|
.CLK_USERCLK1 (PIPE_USERCLK1),
|
.CLK_USERCLK1 (PIPE_USERCLK1),
|
.CLK_USERCLK2 (PIPE_USERCLK2),
|
.CLK_USERCLK2 (PIPE_USERCLK2),
|
.CLK_OOBCLK (clk_oobclk),
|
.CLK_OOBCLK (clk_oobclk),
|
.CLK_MMCM_LOCK (clk_mmcm_lock)
|
.CLK_MMCM_LOCK (clk_mmcm_lock)
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- PIPE Clock External ---------------------------------------
|
//---------- PIPE Clock External ---------------------------------------
|
begin : pipe_clock_int_disable
|
begin : pipe_clock_int_disable
|
assign clk_pclk = PIPE_PCLK_IN;
|
assign clk_pclk = PIPE_PCLK_IN;
|
assign clk_rxusrclk = PIPE_RXUSRCLK_IN;
|
assign clk_rxusrclk = PIPE_RXUSRCLK_IN;
|
assign clk_rxoutclk = PIPE_RXOUTCLK_IN;
|
assign clk_rxoutclk = PIPE_RXOUTCLK_IN;
|
assign clk_dclk = PIPE_DCLK_IN;
|
assign clk_dclk = PIPE_DCLK_IN;
|
assign PIPE_USERCLK1 = PIPE_USERCLK1_IN;
|
assign PIPE_USERCLK1 = PIPE_USERCLK1_IN;
|
assign PIPE_USERCLK2 = PIPE_USERCLK2_IN;
|
assign PIPE_USERCLK2 = PIPE_USERCLK2_IN;
|
assign clk_oobclk = PIPE_OOBCLK_IN;
|
assign clk_oobclk = PIPE_OOBCLK_IN;
|
assign clk_mmcm_lock = PIPE_MMCM_LOCK_IN;
|
assign clk_mmcm_lock = PIPE_MMCM_LOCK_IN;
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- PIPE Reset Module -------------------------------------------------
|
//---------- PIPE Reset Module -------------------------------------------------
|
generate
|
generate
|
|
|
if (PCIE_GT_DEVICE == "GTP")
|
if (PCIE_GT_DEVICE == "GTP")
|
|
|
begin : gtp_pipe_reset
|
begin : gtp_pipe_reset
|
|
|
//---------- GTP PIPE Reset Module -------------------------------------
|
//---------- GTP PIPE Reset Module -------------------------------------
|
cl_a7pcie_x4_gtp_pipe_reset #
|
cl_a7pcie_x4_gtp_pipe_reset #
|
(
|
(
|
|
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
|
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
|
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
|
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
|
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
|
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
|
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
|
|
|
)
|
)
|
gtp_pipe_reset_i
|
gtp_pipe_reset_i
|
(
|
(
|
|
|
//---------- Input -----------------------------
|
//---------- Input -----------------------------
|
.RST_CLK (clk_pclk),
|
.RST_CLK (clk_pclk),
|
.RST_RXUSRCLK (clk_rxusrclk),
|
.RST_RXUSRCLK (clk_rxusrclk),
|
.RST_DCLK (clk_dclk),
|
.RST_DCLK (clk_dclk),
|
.RST_RST_N (reset_n_reg2),
|
.RST_RST_N (reset_n_reg2),
|
.RST_DRP_DONE (drp_done),
|
.RST_DRP_DONE (drp_done),
|
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
|
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
|
.RST_PLLLOCK (&qpll_qplllock),
|
.RST_PLLLOCK (&qpll_qplllock),
|
//.RST_QPLL_IDLE (qrst_idle), // removed for GTP
|
//.RST_QPLL_IDLE (qrst_idle), // removed for GTP
|
.RST_RATE_IDLE (rate_idle),
|
.RST_RATE_IDLE (rate_idle),
|
.RST_RXCDRLOCK (user_rxcdrlock),
|
.RST_RXCDRLOCK (user_rxcdrlock),
|
.RST_MMCM_LOCK (clk_mmcm_lock),
|
.RST_MMCM_LOCK (clk_mmcm_lock),
|
.RST_RESETDONE (user_resetdone),
|
.RST_RESETDONE (user_resetdone),
|
.RST_PHYSTATUS (gt_phystatus),
|
.RST_PHYSTATUS (gt_phystatus),
|
.RST_TXSYNC_DONE (sync_txsync_done),
|
.RST_TXSYNC_DONE (sync_txsync_done),
|
|
|
//---------- Output ----------------------------
|
//---------- Output ----------------------------
|
.RST_CPLLRESET (rst_cpllreset),
|
.RST_CPLLRESET (rst_cpllreset),
|
.RST_CPLLPD (rst_cpllpd),
|
.RST_CPLLPD (rst_cpllpd),
|
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
|
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
|
.RST_DCLK_RESET (rst_dclk_reset),
|
.RST_DCLK_RESET (rst_dclk_reset),
|
.RST_GTRESET (rst_gtreset),
|
.RST_GTRESET (rst_gtreset),
|
.RST_DRP_START (rst_drp_start),
|
.RST_DRP_START (rst_drp_start),
|
.RST_DRP_X16 (rst_drp_x16),
|
.RST_DRP_X16 (rst_drp_x16),
|
.RST_USERRDY (rst_userrdy),
|
.RST_USERRDY (rst_userrdy),
|
.RST_TXSYNC_START (rst_txsync_start),
|
.RST_TXSYNC_START (rst_txsync_start),
|
.RST_IDLE (rst_idle),
|
.RST_IDLE (rst_idle),
|
.RST_FSM (rst_fsm)
|
.RST_FSM (rst_fsm)
|
|
|
);
|
);
|
|
|
//---------- Default ---------------------------------------------------
|
//---------- Default ---------------------------------------------------
|
assign gtp_rst_qpllreset = rst_cpllreset;
|
assign gtp_rst_qpllreset = rst_cpllreset;
|
assign gtp_rst_qpllpd = rst_cpllpd;
|
assign gtp_rst_qpllpd = rst_cpllpd;
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
begin : pipe_reset
|
begin : pipe_reset
|
|
|
//---------- PIPE Reset Module -----------------------------------------
|
//---------- PIPE Reset Module -----------------------------------------
|
cl_a7pcie_x4_pipe_reset #
|
cl_a7pcie_x4_pipe_reset #
|
(
|
(
|
|
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // PCIe power saving
|
.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // PCIe power saving
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
|
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
|
|
|
)
|
)
|
pipe_reset_i
|
pipe_reset_i
|
(
|
(
|
|
|
//---------- Input -----------------------------
|
//---------- Input -----------------------------
|
.RST_CLK (clk_pclk),
|
.RST_CLK (clk_pclk),
|
.RST_RXUSRCLK (clk_rxusrclk),
|
.RST_RXUSRCLK (clk_rxusrclk),
|
.RST_DCLK (clk_dclk),
|
.RST_DCLK (clk_dclk),
|
.RST_RST_N (reset_n_reg2),
|
.RST_RST_N (reset_n_reg2),
|
.RST_DRP_DONE (drp_done),
|
.RST_DRP_DONE (drp_done),
|
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
|
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
|
.RST_CPLLLOCK (gt_cplllock),
|
.RST_CPLLLOCK (gt_cplllock),
|
.RST_QPLL_IDLE (qrst_idle),
|
.RST_QPLL_IDLE (qrst_idle),
|
.RST_RATE_IDLE (rate_idle),
|
.RST_RATE_IDLE (rate_idle),
|
.RST_RXCDRLOCK (user_rxcdrlock),
|
.RST_RXCDRLOCK (user_rxcdrlock),
|
.RST_MMCM_LOCK (clk_mmcm_lock),
|
.RST_MMCM_LOCK (clk_mmcm_lock),
|
.RST_RESETDONE (user_resetdone),
|
.RST_RESETDONE (user_resetdone),
|
.RST_PHYSTATUS (gt_phystatus),
|
.RST_PHYSTATUS (gt_phystatus),
|
.RST_TXSYNC_DONE (sync_txsync_done),
|
.RST_TXSYNC_DONE (sync_txsync_done),
|
|
|
//---------- Output ----------------------------
|
//---------- Output ----------------------------
|
.RST_CPLLRESET (rst_cpllreset),
|
.RST_CPLLRESET (rst_cpllreset),
|
.RST_CPLLPD (rst_cpllpd),
|
.RST_CPLLPD (rst_cpllpd),
|
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
|
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
|
.RST_DCLK_RESET (rst_dclk_reset),
|
.RST_DCLK_RESET (rst_dclk_reset),
|
.RST_GTRESET (rst_gtreset),
|
.RST_GTRESET (rst_gtreset),
|
.RST_DRP_START (rst_drp_start),
|
.RST_DRP_START (rst_drp_start),
|
.RST_DRP_X16X20_MODE (rst_drp_x16x20_mode),
|
.RST_DRP_X16X20_MODE (rst_drp_x16x20_mode),
|
.RST_DRP_X16 (rst_drp_x16),
|
.RST_DRP_X16 (rst_drp_x16),
|
.RST_USERRDY (rst_userrdy),
|
.RST_USERRDY (rst_userrdy),
|
.RST_TXSYNC_START (rst_txsync_start),
|
.RST_TXSYNC_START (rst_txsync_start),
|
.RST_IDLE (rst_idle),
|
.RST_IDLE (rst_idle),
|
.RST_FSM (rst_fsm)
|
.RST_FSM (rst_fsm[4:0])
|
|
|
);
|
);
|
|
|
//---------- Default ---------------------------------------------------
|
//---------- Default ---------------------------------------------------
|
assign gtp_rst_qpllreset = 1'd0;
|
assign gtp_rst_qpllreset = 1'd0;
|
assign gtp_rst_qpllpd = 1'd0;
|
assign gtp_rst_qpllpd = 1'd0;
|
|
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- QPLL Reset Module -------------------------------------------------
|
//---------- QPLL Reset Module -------------------------------------------------
|
generate
|
generate
|
|
|
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL"))
|
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL"))
|
|
|
begin : qpll_reset
|
begin : qpll_reset
|
|
|
cl_a7pcie_x4_qpll_reset #
|
cl_a7pcie_x4_qpll_reset #
|
(
|
(
|
|
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
|
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
|
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
|
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
|
|
|
)
|
)
|
qpll_reset_i
|
qpll_reset_i
|
(
|
(
|
|
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.QRST_CLK (clk_pclk),
|
.QRST_CLK (clk_pclk),
|
.QRST_RST_N (reset_n_reg2),
|
.QRST_RST_N (reset_n_reg2),
|
.QRST_MMCM_LOCK (clk_mmcm_lock),
|
.QRST_MMCM_LOCK (clk_mmcm_lock),
|
.QRST_CPLLLOCK (gt_cplllock),
|
.QRST_CPLLLOCK (gt_cplllock),
|
.QRST_DRP_DONE (qdrp_done),
|
.QRST_DRP_DONE (qdrp_done),
|
.QRST_QPLLLOCK (qpll_qplllock),
|
.QRST_QPLLLOCK (qpll_qplllock),
|
.QRST_RATE (PIPE_RATE),
|
.QRST_RATE (PIPE_RATE),
|
.QRST_QPLLRESET_IN (rate_qpllreset),
|
.QRST_QPLLRESET_IN (rate_qpllreset),
|
.QRST_QPLLPD_IN (rate_qpllpd),
|
.QRST_QPLLPD_IN (rate_qpllpd),
|
|
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.QRST_OVRD (qrst_ovrd),
|
.QRST_OVRD (qrst_ovrd),
|
.QRST_DRP_START (qrst_drp_start),
|
.QRST_DRP_START (qrst_drp_start),
|
.QRST_QPLLRESET_OUT (qrst_qpllreset),
|
.QRST_QPLLRESET_OUT (qrst_qpllreset),
|
.QRST_QPLLPD_OUT (qrst_qpllpd),
|
.QRST_QPLLPD_OUT (qrst_qpllpd),
|
.QRST_IDLE (qrst_idle),
|
.QRST_IDLE (qrst_idle),
|
.QRST_FSM (qrst_fsm)
|
.QRST_FSM (qrst_fsm)
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- QPLL Reset Defaults ---------------------------------------
|
//---------- QPLL Reset Defaults ---------------------------------------
|
begin : qpll_reset_disable
|
begin : qpll_reset_disable
|
assign qrst_ovrd = 1'd0;
|
assign qrst_ovrd = 1'd0;
|
assign qrst_drp_start = 1'd0;
|
assign qrst_drp_start = 1'd0;
|
assign qrst_qpllreset = 1'd0;
|
assign qrst_qpllreset = 1'd0;
|
assign qrst_qpllpd = 1'd0;
|
assign qrst_qpllpd = 1'd0;
|
assign qrst_idle = 1'd0;
|
assign qrst_idle = 1'd0;
|
assign qrst_fsm = 1;
|
assign qrst_fsm = 4'd1;
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- Generate PIPE JTAG Master -----------------------------------------
|
//---------- Generate PIPE JTAG Master -----------------------------------------
|
generate
|
generate
|
|
|
if (PCIE_JTAG_MODE == 1)
|
if (PCIE_JTAG_MODE == 1)
|
|
|
begin : pipe_jtag_m
|
begin : pipe_jtag_m
|
|
|
//-------------PIPE JTAG Master Module ---------------------------------
|
//-------------PIPE JTAG Master Module ---------------------------------
|
pipe_jtag_m #
|
pipe_jtag_m #
|
(
|
(
|
.PCIE_LANE (PCIE_LANE)
|
.PCIE_LANE (PCIE_LANE)
|
)
|
)
|
pipe_jtag_m_i
|
pipe_jtag_m_i
|
(
|
(
|
|
|
//---------- Connect to JTAG Slave -------------
|
//---------- Connect to JTAG Slave -------------
|
.JTAG_SL_IPORT (jtag_sl_iport), //
|
.JTAG_SL_IPORT (jtag_sl_iport), //
|
.JTAG_SL_OPORT (jtag_sl_oport),
|
.JTAG_SL_OPORT (jtag_sl_oport),
|
|
|
//---------- Input -----------------------------
|
//---------- Input -----------------------------
|
.JTAG_M_CLK (clk_dclk)
|
.JTAG_M_CLK (clk_dclk)
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
begin : pipe_jtag_m_disable
|
begin : pipe_jtag_m_disable
|
assign jtag_sl_iport = {PCIE_LANE{37'd0}};
|
assign jtag_sl_iport = {PCIE_LANE{37'd0}};
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- Generate PIPE Lane ------------------------------------------------
|
//---------- Generate PIPE Lane ------------------------------------------------
|
generate for (i=0; i<PCIE_LANE; i=i+1)
|
generate for (i=0; i<PCIE_LANE; i=i+1)
|
|
|
begin : pipe_lane
|
begin : pipe_lane
|
|
|
//---------- PIPE User Module ----------------------------------------------
|
//---------- PIPE User Module ----------------------------------------------
|
cl_a7pcie_x4_pipe_user #
|
cl_a7pcie_x4_pipe_user #
|
(
|
(
|
|
|
.PCIE_USE_MODE (PCIE_USE_MODE),
|
.PCIE_USE_MODE (PCIE_USE_MODE),
|
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE)
|
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE)
|
|
|
)
|
)
|
pipe_user_i
|
pipe_user_i
|
(
|
(
|
|
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.USER_TXUSRCLK (clk_pclk),
|
.USER_TXUSRCLK (clk_pclk),
|
.USER_RXUSRCLK (clk_rxusrclk),
|
.USER_RXUSRCLK (clk_rxusrclk),
|
.USER_OOBCLK_IN (clk_oobclk),
|
.USER_OOBCLK_IN (clk_oobclk),
|
.USER_RST_N (!rst_cpllreset),
|
.USER_RST_N (!rst_cpllreset),
|
.USER_RXUSRCLK_RST_N (!rst_rxusrclk_reset),
|
.USER_RXUSRCLK_RST_N (!rst_rxusrclk_reset),
|
.USER_PCLK_SEL (rate_pclk_sel[i]),
|
.USER_PCLK_SEL (rate_pclk_sel[i]),
|
.USER_RESETOVRD_START (rate_resetovrd_start[i]),
|
.USER_RESETOVRD_START (rate_resetovrd_start[i]),
|
.USER_TXRESETDONE (gt_txresetdone[i]),
|
.USER_TXRESETDONE (gt_txresetdone[i]),
|
.USER_RXRESETDONE (gt_rxresetdone[i]),
|
.USER_RXRESETDONE (gt_rxresetdone[i]),
|
.USER_TXELECIDLE (PIPE_TXELECIDLE[i]),
|
.USER_TXELECIDLE (PIPE_TXELECIDLE[i]),
|
.USER_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
|
.USER_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
|
.USER_RXCDRLOCK_IN (gt_rxcdrlock[i]),
|
.USER_RXCDRLOCK_IN (gt_rxcdrlock[i]),
|
.USER_RXVALID_IN (gt_rxvalid[i]),
|
.USER_RXVALID_IN (gt_rxvalid[i]),
|
.USER_RXSTATUS_IN (gt_rxstatus[(3*i)+2]),
|
.USER_RXSTATUS_IN (gt_rxstatus[(3*i)+2]),
|
.USER_PHYSTATUS_IN (gt_phystatus[i]),
|
.USER_PHYSTATUS_IN (gt_phystatus[i]),
|
.USER_RATE_DONE (rate_done[i]),
|
.USER_RATE_DONE (rate_done[i]),
|
.USER_RST_IDLE (rst_idle),
|
.USER_RST_IDLE (rst_idle),
|
.USER_RATE_RXSYNC (rate_rxsync[i]),
|
.USER_RATE_RXSYNC (rate_rxsync[i]),
|
.USER_RATE_IDLE (rate_idle[i]),
|
.USER_RATE_IDLE (rate_idle[i]),
|
.USER_RATE_GEN3 (rate_gen3[i]),
|
.USER_RATE_GEN3 (rate_gen3[i]),
|
.USER_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
|
.USER_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
|
|
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.USER_OOBCLK (user_oobclk[i]),
|
.USER_OOBCLK (user_oobclk[i]),
|
.USER_RESETOVRD (user_resetovrd[i]),
|
.USER_RESETOVRD (user_resetovrd[i]),
|
.USER_TXPMARESET (user_txpmareset[i]),
|
.USER_TXPMARESET (user_txpmareset[i]),
|
.USER_RXPMARESET (user_rxpmareset[i]),
|
.USER_RXPMARESET (user_rxpmareset[i]),
|
.USER_RXCDRRESET (user_rxcdrreset[i]),
|
.USER_RXCDRRESET (user_rxcdrreset[i]),
|
.USER_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
|
.USER_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
|
.USER_RXDFELPMRESET (user_rxdfelpmreset[i]),
|
.USER_RXDFELPMRESET (user_rxdfelpmreset[i]),
|
.USER_EYESCANRESET (user_eyescanreset[i]),
|
.USER_EYESCANRESET (user_eyescanreset[i]),
|
.USER_TXPCSRESET (user_txpcsreset[i]),
|
.USER_TXPCSRESET (user_txpcsreset[i]),
|
.USER_RXPCSRESET (user_rxpcsreset[i]),
|
.USER_RXPCSRESET (user_rxpcsreset[i]),
|
.USER_RXBUFRESET (user_rxbufreset[i]),
|
.USER_RXBUFRESET (user_rxbufreset[i]),
|
.USER_RESETOVRD_DONE (user_resetovrd_done[i]),
|
.USER_RESETOVRD_DONE (user_resetovrd_done[i]),
|
.USER_RESETDONE (user_resetdone[i]),
|
.USER_RESETDONE (user_resetdone[i]),
|
.USER_ACTIVE_LANE (user_active_lane[i]),
|
.USER_ACTIVE_LANE (user_active_lane[i]),
|
.USER_RXCDRLOCK_OUT (user_rxcdrlock[i]),
|
.USER_RXCDRLOCK_OUT (user_rxcdrlock[i]),
|
.USER_RXVALID_OUT (PIPE_RXVALID[i]),
|
.USER_RXVALID_OUT (PIPE_RXVALID[i]),
|
.USER_PHYSTATUS_OUT (PIPE_PHYSTATUS[i]),
|
.USER_PHYSTATUS_OUT (PIPE_PHYSTATUS[i]),
|
.USER_PHYSTATUS_RST (PIPE_PHYSTATUS_RST[i]),
|
.USER_PHYSTATUS_RST (PIPE_PHYSTATUS_RST[i]),
|
.USER_GEN3_RDY (PIPE_GEN3_RDY[i]),
|
.USER_GEN3_RDY (PIPE_GEN3_RDY[i]),
|
.USER_RX_CONVERGE (user_rx_converge[i])
|
.USER_RX_CONVERGE (user_rx_converge[i])
|
|
|
);
|
);
|
|
|
|
|
|
|
//---------- GTP PIPE Rate Module ------------------------------------------
|
//---------- GTP PIPE Rate Module ------------------------------------------
|
if (PCIE_GT_DEVICE == "GTP")
|
if (PCIE_GT_DEVICE == "GTP")
|
|
|
begin : gtp_pipe_rate
|
begin : gtp_pipe_rate
|
|
|
cl_a7pcie_x4_gtp_pipe_rate #
|
cl_a7pcie_x4_gtp_pipe_rate #
|
(
|
(
|
|
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP) // PCIe sim speedup
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP) // PCIe sim speedup
|
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
|
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
|
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
|
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
|
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
|
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
|
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
|
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
|
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
|
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
|
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // removed for GTP
|
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // removed for GTP
|
|
|
)
|
)
|
gtp_pipe_rate_i
|
gtp_pipe_rate_i
|
(
|
(
|
|
|
//---------- Input -----------------------------
|
//---------- Input -----------------------------
|
.RATE_CLK (clk_pclk),
|
.RATE_CLK (clk_pclk),
|
.RATE_RST_N (!rst_cpllreset),
|
.RATE_RST_N (!rst_cpllreset),
|
//.RATE_RST_IDLE (rst_idle), // removed for GTP
|
//.RATE_RST_IDLE (rst_idle), // removed for GTP
|
//.RATE_ACTIVE_LANE (user_active_lane[i]), // removed for GTP
|
//.RATE_ACTIVE_LANE (user_active_lane[i]), // removed for GTP
|
.RATE_RATE_IN (PIPE_RATE),
|
.RATE_RATE_IN (PIPE_RATE),
|
//.RATE_CPLLLOCK (gt_cplllock[i]), // removed for GTP
|
//.RATE_CPLLLOCK (gt_cplllock[i]), // removed for GTP
|
//.RATE_QPLLLOCK (qpll_qplllock[i>>2]) // removed for GTP
|
//.RATE_QPLLLOCK (qpll_qplllock[i>>2]) // removed for GTP
|
//.RATE_MMCM_LOCK (clk_mmcm_lock), // removed for GTP
|
//.RATE_MMCM_LOCK (clk_mmcm_lock), // removed for GTP
|
.RATE_DRP_DONE (drp_done[i]),
|
.RATE_DRP_DONE (drp_done[i]),
|
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
|
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
|
//.RATE_TXRESETDONE (gt_txresetdone[i]), // removed for GTP
|
//.RATE_TXRESETDONE (gt_txresetdone[i]), // removed for GTP
|
//.RATE_RXRESETDONE (gt_rxresetdone[i]), // removed for GTP
|
//.RATE_RXRESETDONE (gt_rxresetdone[i]), // removed for GTP
|
.RATE_TXRATEDONE (gt_txratedone[i]),
|
.RATE_TXRATEDONE (gt_txratedone[i]),
|
.RATE_RXRATEDONE (gt_rxratedone[i]),
|
.RATE_RXRATEDONE (gt_rxratedone[i]),
|
.RATE_PHYSTATUS (gt_phystatus[i]),
|
.RATE_PHYSTATUS (gt_phystatus[i]),
|
//.RATE_RESETOVRD_DONE (user_resetovrd_done[i]), // removed for GTP
|
//.RATE_RESETOVRD_DONE (user_resetovrd_done[i]), // removed for GTP
|
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
|
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
|
//.RATE_RXSYNC_DONE (sync_rxsync_done[i]), // removed for GTP
|
//.RATE_RXSYNC_DONE (sync_rxsync_done[i]), // removed for GTP
|
|
|
//---------- Output ----------------------------
|
//---------- Output ----------------------------
|
//.RATE_CPLLPD (rate_cpllpd[i]), // removed for GTP
|
//.RATE_CPLLPD (rate_cpllpd[i]), // removed for GTP
|
//.RATE_QPLLPD (rate_qpllpd[i]), // removed for GTP
|
//.RATE_QPLLPD (rate_qpllpd[i]), // removed for GTP
|
//.RATE_CPLLRESET (rate_cpllreset[i]), // removed for GTP
|
//.RATE_CPLLRESET (rate_cpllreset[i]), // removed for GTP
|
//.RATE_QPLLRESET (rate_qpllreset[i]), // removed for GTP
|
//.RATE_QPLLRESET (rate_qpllreset[i]), // removed for GTP
|
//.RATE_TXPMARESET (rate_txpmareset[i]), // removed for GTP
|
//.RATE_TXPMARESET (rate_txpmareset[i]), // removed for GTP
|
//.RATE_RXPMARESET (rate_rxpmareset[i]), // removed for GTP
|
//.RATE_RXPMARESET (rate_rxpmareset[i]), // removed for GTP
|
//.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), // removed for GTP
|
//.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), // removed for GTP
|
.RATE_DRP_START (rate_drp_start[i]),
|
.RATE_DRP_START (rate_drp_start[i]),
|
.RATE_DRP_X16 (rate_drp_x16[i]),
|
.RATE_DRP_X16 (rate_drp_x16[i]),
|
.RATE_PCLK_SEL (rate_pclk_sel[i]),
|
.RATE_PCLK_SEL (rate_pclk_sel[i]),
|
//.RATE_GEN3 (rate_gen3[i]), // removed for GTP
|
//.RATE_GEN3 (rate_gen3[i]), // removed for GTP
|
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
|
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
|
//.RATE_RESETOVRD_START (rate_resetovrd_start[i]), // removed for GTP
|
//.RATE_RESETOVRD_START (rate_resetovrd_start[i]), // removed for GTP
|
.RATE_TXSYNC_START (rate_txsync_start[i]),
|
.RATE_TXSYNC_START (rate_txsync_start[i]),
|
.RATE_DONE (rate_done[i]),
|
.RATE_DONE (rate_done[i]),
|
//.RATE_RXSYNC_START (rate_rxsync_start[i]), // removed for GTP
|
//.RATE_RXSYNC_START (rate_rxsync_start[i]), // removed for GTP
|
//.RATE_RXSYNC (rate_rxsync[i]), // removed for GTP
|
//.RATE_RXSYNC (rate_rxsync[i]), // removed for GTP
|
.RATE_IDLE (rate_idle[i]),
|
.RATE_IDLE (rate_idle[i]),
|
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
|
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
|
);
|
);
|
|
|
//---------- Default for GTP -----------------------
|
//---------- Default for GTP -----------------------
|
assign rate_cpllpd[i] = 1'd0;
|
assign rate_cpllpd[i] = 1'd0;
|
assign rate_qpllpd[i] = 1'd0;
|
assign rate_qpllpd[i] = 1'd0;
|
assign rate_cpllreset[i] = 1'd0;
|
assign rate_cpllreset[i] = 1'd0;
|
assign rate_qpllreset[i] = 1'd0;
|
assign rate_qpllreset[i] = 1'd0;
|
assign rate_txpmareset[i] = 1'd0;
|
assign rate_txpmareset[i] = 1'd0;
|
assign rate_rxpmareset[i] = 1'd0;
|
assign rate_rxpmareset[i] = 1'd0;
|
assign rate_sysclksel[(2*i)+1:(2*i)] = 2'b0;
|
assign rate_sysclksel[(2*i)+1:(2*i)] = 2'b0;
|
assign rate_gen3[i] = 1'd0;
|
assign rate_gen3[i] = 1'd0;
|
assign rate_resetovrd_start[i] = 1'd0;
|
assign rate_resetovrd_start[i] = 1'd0;
|
assign rate_rxsync_start[i] = 1'd0;
|
assign rate_rxsync_start[i] = 1'd0;
|
assign rate_rxsync[i] = 1'd0;
|
assign rate_rxsync[i] = 1'd0;
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
begin : pipe_rate
|
begin : pipe_rate
|
|
|
//---------- PIPE Rate Module ----------------------------------------------
|
//---------- PIPE Rate Module ----------------------------------------------
|
cl_a7pcie_x4_pipe_rate #
|
cl_a7pcie_x4_pipe_rate #
|
(
|
(
|
|
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
|
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // PCIe RX buffer enable for Gen3 only
|
.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // PCIe RX buffer enable for Gen3 only
|
|
|
)
|
)
|
pipe_rate_i
|
pipe_rate_i
|
(
|
(
|
|
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.RATE_CLK (clk_pclk),
|
.RATE_CLK (clk_pclk),
|
.RATE_RST_N (!rst_cpllreset),
|
.RATE_RST_N (!rst_cpllreset),
|
.RATE_RST_IDLE (rst_idle),
|
.RATE_RST_IDLE (rst_idle),
|
.RATE_ACTIVE_LANE (user_active_lane[i]),
|
.RATE_ACTIVE_LANE (user_active_lane[i]),
|
.RATE_RATE_IN (PIPE_RATE),
|
.RATE_RATE_IN (PIPE_RATE),
|
.RATE_CPLLLOCK (gt_cplllock[i]),
|
.RATE_CPLLLOCK (gt_cplllock[i]),
|
.RATE_QPLLLOCK (qpll_qplllock[i>>2]),
|
.RATE_QPLLLOCK (qpll_qplllock[i>>2]),
|
.RATE_MMCM_LOCK (clk_mmcm_lock),
|
.RATE_MMCM_LOCK (clk_mmcm_lock),
|
.RATE_DRP_DONE (drp_done[i]),
|
.RATE_DRP_DONE (drp_done[i]),
|
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
|
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
|
.RATE_TXRESETDONE (gt_txresetdone[i]),
|
.RATE_TXRESETDONE (gt_txresetdone[i]),
|
.RATE_RXRESETDONE (gt_rxresetdone[i]),
|
.RATE_RXRESETDONE (gt_rxresetdone[i]),
|
.RATE_TXRATEDONE (gt_txratedone[i]),
|
.RATE_TXRATEDONE (gt_txratedone[i]),
|
.RATE_RXRATEDONE (gt_rxratedone[i]),
|
.RATE_RXRATEDONE (gt_rxratedone[i]),
|
.RATE_PHYSTATUS (gt_phystatus[i]),
|
.RATE_PHYSTATUS (gt_phystatus[i]),
|
.RATE_RESETOVRD_DONE (user_resetovrd_done[i]),
|
.RATE_RESETOVRD_DONE (user_resetovrd_done[i]),
|
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
|
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
|
.RATE_RXSYNC_DONE (sync_rxsync_done[i]),
|
.RATE_RXSYNC_DONE (sync_rxsync_done[i]),
|
|
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.RATE_CPLLPD (rate_cpllpd[i]),
|
.RATE_CPLLPD (rate_cpllpd[i]),
|
.RATE_QPLLPD (rate_qpllpd[i]),
|
.RATE_QPLLPD (rate_qpllpd[i]),
|
.RATE_CPLLRESET (rate_cpllreset[i]),
|
.RATE_CPLLRESET (rate_cpllreset[i]),
|
.RATE_QPLLRESET (rate_qpllreset[i]),
|
.RATE_QPLLRESET (rate_qpllreset[i]),
|
.RATE_TXPMARESET (rate_txpmareset[i]),
|
.RATE_TXPMARESET (rate_txpmareset[i]),
|
.RATE_RXPMARESET (rate_rxpmareset[i]),
|
.RATE_RXPMARESET (rate_rxpmareset[i]),
|
.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
|
.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
|
.RATE_DRP_START (rate_drp_start[i]),
|
.RATE_DRP_START (rate_drp_start[i]),
|
.RATE_DRP_X16X20_MODE (rate_drp_x16x20_mode[i]),
|
.RATE_DRP_X16X20_MODE (rate_drp_x16x20_mode[i]),
|
.RATE_DRP_X16 (rate_drp_x16[i]),
|
.RATE_DRP_X16 (rate_drp_x16[i]),
|
.RATE_PCLK_SEL (rate_pclk_sel[i]),
|
.RATE_PCLK_SEL (rate_pclk_sel[i]),
|
.RATE_GEN3 (rate_gen3[i]),
|
.RATE_GEN3 (rate_gen3[i]),
|
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
|
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
|
.RATE_RESETOVRD_START (rate_resetovrd_start[i]),
|
.RATE_RESETOVRD_START (rate_resetovrd_start[i]),
|
.RATE_TXSYNC_START (rate_txsync_start[i]),
|
.RATE_TXSYNC_START (rate_txsync_start[i]),
|
.RATE_DONE (rate_done[i]),
|
.RATE_DONE (rate_done[i]),
|
.RATE_RXSYNC_START (rate_rxsync_start[i]),
|
.RATE_RXSYNC_START (rate_rxsync_start[i]),
|
.RATE_RXSYNC (rate_rxsync[i]),
|
.RATE_RXSYNC (rate_rxsync[i]),
|
.RATE_IDLE (rate_idle[i]),
|
.RATE_IDLE (rate_idle[i]),
|
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
|
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- PIPE Sync Module ----------------------------------------------
|
//---------- PIPE Sync Module ----------------------------------------------
|
cl_a7pcie_x4_pipe_sync #
|
cl_a7pcie_x4_pipe_sync #
|
(
|
(
|
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
|
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
|
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
|
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
|
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
|
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
|
.PCIE_LANE (PCIE_LANE), // PCIe lane
|
.PCIE_LANE (PCIE_LANE), // PCIe lane
|
.PCIE_LINK_SPEED (PCIE_LINK_SPEED) // PCIe link speed
|
.PCIE_LINK_SPEED (PCIE_LINK_SPEED) // PCIe link speed
|
|
|
)
|
)
|
pipe_sync_i
|
pipe_sync_i
|
(
|
(
|
|
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.SYNC_CLK (clk_pclk),
|
.SYNC_CLK (clk_pclk),
|
.SYNC_RST_N (!rst_cpllreset),
|
.SYNC_RST_N (!rst_cpllreset),
|
.SYNC_SLAVE (i > 0),
|
.SYNC_SLAVE (i > 0),
|
.SYNC_GEN3 (rate_gen3[i]),
|
.SYNC_GEN3 (rate_gen3[i]),
|
.SYNC_RATE_IDLE (rate_idle[i]),
|
.SYNC_RATE_IDLE (rate_idle[i]),
|
.SYNC_MMCM_LOCK (clk_mmcm_lock),
|
.SYNC_MMCM_LOCK (clk_mmcm_lock),
|
.SYNC_RXELECIDLE (gt_rxelecidle[i]),
|
.SYNC_RXELECIDLE (gt_rxelecidle[i]),
|
.SYNC_RXCDRLOCK (user_rxcdrlock[i]),
|
.SYNC_RXCDRLOCK (user_rxcdrlock[i]),
|
.SYNC_ACTIVE_LANE (user_active_lane[i]),
|
.SYNC_ACTIVE_LANE (user_active_lane[i]),
|
|
|
.SYNC_TXSYNC_START (rate_txsync_start[i] || rst_txsync_start),
|
.SYNC_TXSYNC_START (rate_txsync_start[i] || rst_txsync_start),
|
.SYNC_TXPHINITDONE (&(gt_txphinitdone | (~user_active_lane))),
|
.SYNC_TXPHINITDONE (&(gt_txphinitdone | (~user_active_lane))),
|
.SYNC_TXDLYSRESETDONE (txdlysresetdone[i]),
|
.SYNC_TXDLYSRESETDONE (txdlysresetdone[i]),
|
.SYNC_TXPHALIGNDONE (txphaligndone[i]),
|
.SYNC_TXPHALIGNDONE (txphaligndone[i]),
|
.SYNC_TXSYNCDONE (gt_txsyncdone[i]), // GTH
|
.SYNC_TXSYNCDONE (gt_txsyncdone[i]), // GTH
|
|
|
.SYNC_RXSYNC_START (rate_rxsync_start[i]),
|
.SYNC_RXSYNC_START (rate_rxsync_start[i]),
|
.SYNC_RXDLYSRESETDONE (rxdlysresetdone[i]),
|
.SYNC_RXDLYSRESETDONE (rxdlysresetdone[i]),
|
.SYNC_RXPHALIGNDONE_M (gt_rxphaligndone[0]),
|
.SYNC_RXPHALIGNDONE_M (gt_rxphaligndone[0]),
|
.SYNC_RXPHALIGNDONE_S (rxphaligndone_s[i]),
|
.SYNC_RXPHALIGNDONE_S (rxphaligndone_s[i]),
|
.SYNC_RXSYNC_DONEM_IN (sync_rxsync_donem[0]),
|
.SYNC_RXSYNC_DONEM_IN (sync_rxsync_donem[0]),
|
.SYNC_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
|
.SYNC_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
|
|
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.SYNC_TXPHDLYRESET (sync_txphdlyreset[i]),
|
.SYNC_TXPHDLYRESET (sync_txphdlyreset[i]),
|
.SYNC_TXPHALIGN (sync_txphalign[i]),
|
.SYNC_TXPHALIGN (sync_txphalign[i]),
|
.SYNC_TXPHALIGNEN (sync_txphalignen[i]),
|
.SYNC_TXPHALIGNEN (sync_txphalignen[i]),
|
.SYNC_TXPHINIT (sync_txphinit[i]),
|
.SYNC_TXPHINIT (sync_txphinit[i]),
|
.SYNC_TXDLYBYPASS (sync_txdlybypass[i]),
|
.SYNC_TXDLYBYPASS (sync_txdlybypass[i]),
|
.SYNC_TXDLYSRESET (sync_txdlysreset[i]),
|
.SYNC_TXDLYSRESET (sync_txdlysreset[i]),
|
.SYNC_TXDLYEN (sync_txdlyen[i]),
|
.SYNC_TXDLYEN (sync_txdlyen[i]),
|
.SYNC_TXSYNC_DONE (sync_txsync_done[i]),
|
.SYNC_TXSYNC_DONE (sync_txsync_done[i]),
|
.SYNC_FSM_TX (sync_fsm_tx[(6*i)+5:(6*i)]),
|
.SYNC_FSM_TX (sync_fsm_tx[(6*i)+5:(6*i)]),
|
|
|
.SYNC_RXPHALIGN (sync_rxphalign[i]),
|
.SYNC_RXPHALIGN (sync_rxphalign[i]),
|
.SYNC_RXPHALIGNEN (sync_rxphalignen[i]),
|
.SYNC_RXPHALIGNEN (sync_rxphalignen[i]),
|
.SYNC_RXDLYBYPASS (sync_rxdlybypass[i]),
|
.SYNC_RXDLYBYPASS (sync_rxdlybypass[i]),
|
.SYNC_RXDLYSRESET (sync_rxdlysreset[i]),
|
.SYNC_RXDLYSRESET (sync_rxdlysreset[i]),
|
.SYNC_RXDLYEN (sync_rxdlyen[i]),
|
.SYNC_RXDLYEN (sync_rxdlyen[i]),
|
.SYNC_RXDDIEN (sync_rxddien[i]),
|
.SYNC_RXDDIEN (sync_rxddien[i]),
|
.SYNC_RXSYNC_DONEM_OUT (sync_rxsync_donem[i]),
|
.SYNC_RXSYNC_DONEM_OUT (sync_rxsync_donem[i]),
|
.SYNC_RXSYNC_DONE (sync_rxsync_done[i]),
|
.SYNC_RXSYNC_DONE (sync_rxsync_done[i]),
|
.SYNC_FSM_RX (sync_fsm_rx[(7*i)+6:(7*i)])
|
.SYNC_FSM_RX (sync_fsm_rx[(7*i)+6:(7*i)])
|
|
|
);
|
);
|
|
|
//---------- PIPE Sync Assignments -----------------------------------------
|
//---------- PIPE Sync Assignments -----------------------------------------
|
assign txdlysresetdone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txdlysresetdone[i] : >_txdlysresetdone;
|
assign txdlysresetdone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txdlysresetdone[i] : >_txdlysresetdone;
|
assign txphaligndone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txphaligndone[i] : &(gt_txphaligndone | (~user_active_lane));
|
assign txphaligndone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txphaligndone[i] : &(gt_txphaligndone | (~user_active_lane));
|
assign rxdlysresetdone[i] = (PCIE_RXSYNC_MODE == 1) ? gt_rxdlysresetdone[i] : >_rxdlysresetdone;
|
assign rxdlysresetdone[i] = (PCIE_RXSYNC_MODE == 1) ? gt_rxdlysresetdone[i] : >_rxdlysresetdone;
|
assign rxphaligndone_s[i] = (PCIE_LANE == 1) ? 1'd0 : >_rxphaligndone[PCIE_LANE:1];
|
assign rxphaligndone_s[i] = (PCIE_LANE == 1) ? 1'd0 : >_rxphaligndone[PCIE_LANE:1];
|
|
|
|
|
//---------- GTP PIPE DRP Module -------------------------------------------
|
//---------- GTP PIPE DRP Module -------------------------------------------
|
if (PCIE_GT_DEVICE == "GTP")
|
if (PCIE_GT_DEVICE == "GTP")
|
|
|
begin : gtp_pipe_drp
|
begin : gtp_pipe_drp
|
|
|
//---------- GTP PIPE DRP Module ---------------------------------------
|
//---------- GTP PIPE DRP Module ---------------------------------------
|
cl_a7pcie_x4_gtp_pipe_drp
|
cl_a7pcie_x4_gtp_pipe_drp
|
//(
|
//(
|
|
|
//.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // removed for GTP
|
//.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // removed for GTP
|
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
|
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
|
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
|
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
|
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
|
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
|
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
|
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
|
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // removed for GTP
|
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // removed for GTP
|
//.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // removed for GTP
|
//.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // removed for GTP
|
//.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // removed for GTP
|
//.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // removed for GTP
|
|
|
//)
|
//)
|
gtp_pipe_drp_i
|
gtp_pipe_drp_i
|
(
|
(
|
|
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.DRP_CLK (clk_dclk),
|
.DRP_CLK (clk_dclk),
|
.DRP_RST_N (!rst_dclk_reset),
|
.DRP_RST_N (!rst_dclk_reset),
|
//.DRP_GTXRESET (rst_gtreset), // removed for GTP
|
//.DRP_GTXRESET (rst_gtreset), // removed for GTP
|
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
|
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
|
//.DRP_RATE (PIPE_RATE), // removed for GTP
|
//.DRP_RATE (PIPE_RATE), // removed for GTP
|
.DRP_START (rst_drp_start || rate_drp_start[i]),
|
.DRP_START (rst_drp_start || rate_drp_start[i]),
|
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
|
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
|
.DRP_RDY (gt_rdy[i]),
|
.DRP_RDY (gt_rdy[i]),
|
|
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
|
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
|
.DRP_EN (drp_en[i]),
|
.DRP_EN (drp_en[i]),
|
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
|
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
|
.DRP_WE (drp_we[i]),
|
.DRP_WE (drp_we[i]),
|
.DRP_DONE (drp_done[i]),
|
.DRP_DONE (drp_done[i]),
|
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
|
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
begin : pipe_drp
|
begin : pipe_drp
|
|
|
//---------- PIPE DRP Module -------------------------------------------
|
//---------- PIPE DRP Module -------------------------------------------
|
cl_a7pcie_x4_pipe_drp #
|
cl_a7pcie_x4_pipe_drp #
|
(
|
(
|
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_AUX_CDR_GEN3_EN (PCIE_AUX_CDR_GEN3_EN), // PCIe AUX CDR Gen3 enable
|
.PCIE_AUX_CDR_GEN3_EN (PCIE_AUX_CDR_GEN3_EN), // PCIe AUX CDR Gen3 enable
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
|
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
|
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
|
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
|
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // PCIe RX sync mode
|
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // PCIe RX sync mode
|
|
|
)
|
)
|
pipe_drp_i
|
pipe_drp_i
|
(
|
(
|
|
|
//---------- Input ---------------------------------
|
//---------- Input ---------------------------------
|
.DRP_CLK (clk_dclk),
|
.DRP_CLK (clk_dclk),
|
.DRP_RST_N (!rst_dclk_reset),
|
.DRP_RST_N (!rst_dclk_reset),
|
.DRP_GTXRESET (rst_gtreset),
|
.DRP_GTXRESET (rst_gtreset),
|
.DRP_RATE (PIPE_RATE),
|
.DRP_RATE (PIPE_RATE),
|
.DRP_X16X20_MODE (rst_drp_x16x20_mode || rate_drp_x16x20_mode[i]),
|
.DRP_X16X20_MODE (rst_drp_x16x20_mode || rate_drp_x16x20_mode[i]),
|
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
|
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
|
.DRP_START (rst_drp_start || rate_drp_start[i]),
|
.DRP_START (rst_drp_start || rate_drp_start[i]),
|
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
|
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
|
.DRP_RDY (gt_rdy[i]),
|
.DRP_RDY (gt_rdy[i]),
|
|
|
//---------- Output --------------------------------
|
//---------- Output --------------------------------
|
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
|
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
|
.DRP_EN (drp_en[i]),
|
.DRP_EN (drp_en[i]),
|
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
|
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
|
.DRP_WE (drp_we[i]),
|
.DRP_WE (drp_we[i]),
|
.DRP_DONE (drp_done[i]),
|
.DRP_DONE (drp_done[i]),
|
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
|
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- Generate PIPE JTAG Slave --------------------------------------
|
//---------- Generate PIPE JTAG Slave --------------------------------------
|
if (PCIE_JTAG_MODE == 1)
|
if (PCIE_JTAG_MODE == 1)
|
|
|
begin : pipe_jtag_s
|
begin : pipe_jtag_s
|
|
|
//-------------PIPE JTAG Slave Module ----------------------------------
|
//-------------PIPE JTAG Slave Module ----------------------------------
|
pipe_jtag_s #
|
pipe_jtag_s #
|
(
|
(
|
|
|
.GC_XSDB_SLAVE_TYPE (GC_XSDB_SLAVE_TYPE)
|
.GC_XSDB_SLAVE_TYPE (GC_XSDB_SLAVE_TYPE)
|
|
|
)
|
)
|
pipe_jtag_s_i
|
pipe_jtag_s_i
|
(
|
(
|
|
|
//---------- Connect to JTAG Master ------------
|
//---------- Connect to JTAG Master ------------
|
.JTAG_SL_I_PORT (jtag_sl_iport[((i+1)*37)-1 : (i*37)]),
|
.JTAG_SL_I_PORT (jtag_sl_iport[((i+1)*37)-1 : (i*37)]),
|
.JTAG_SL_O_PORT (jtag_sl_oport[((i+1)*17)-1 : (i*17)]),
|
.JTAG_SL_O_PORT (jtag_sl_oport[((i+1)*17)-1 : (i*17)]),
|
|
|
//---------- Input -----------------------------
|
//---------- Input -----------------------------
|
.JTAG_SL_DRDY (gt_rdy[i]),
|
.JTAG_SL_DRDY (gt_rdy[i]),
|
.JTAG_SL_DO (gt_do[(16*i)+15:(16*i)]),
|
.JTAG_SL_DO (gt_do[(16*i)+15:(16*i)]),
|
|
|
//---------- Output ----------------------------
|
//---------- Output ----------------------------
|
.JTAG_SL_DCLK (),
|
.JTAG_SL_DCLK (),
|
.JTAG_SL_ADDR (jtag_sl_addr[(17*i)+16:(17*i)]),
|
.JTAG_SL_ADDR (jtag_sl_addr[(17*i)+16:(17*i)]),
|
.JTAG_SL_DEN (jtag_sl_den[i]),
|
.JTAG_SL_DEN (jtag_sl_den[i]),
|
.JTAG_SL_DI (jtag_sl_di[(16*i)+15:(16*i)]),
|
.JTAG_SL_DI (jtag_sl_di[(16*i)+15:(16*i)]),
|
.JTAG_SL_DWE (jtag_sl_we[i])
|
.JTAG_SL_DWE (jtag_sl_we[i])
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- PIPE JTAG Slave Default ----------------------------------
|
//---------- PIPE JTAG Slave Default ----------------------------------
|
begin : pipe_jtag_s_disable
|
begin : pipe_jtag_s_disable
|
assign jtag_sl_oport[((i+1)*17)-1 : (i*17)] = 17'd0;
|
assign jtag_sl_oport[((i+1)*17)-1 : (i*17)] = 17'd0;
|
assign jtag_sl_addr[(17*i)+16:(17*i)] = 17'd0;
|
assign jtag_sl_addr[(17*i)+16:(17*i)] = 17'd0;
|
assign jtag_sl_den[i] = 1'd0;
|
assign jtag_sl_den[i] = 1'd0;
|
assign jtag_sl_di[(16*i)+15:(16*i)] = 16'd0;
|
assign jtag_sl_di[(16*i)+15:(16*i)] = 16'd0;
|
assign jtag_sl_we[i] = 1'd0;
|
assign jtag_sl_we[i] = 1'd0;
|
end
|
end
|
|
|
//---------- Generate DRP MUX ----------------------------------------------
|
//---------- Generate DRP MUX ----------------------------------------------
|
assign PIPE_JTAG_RDY[i] = drp_fsm[3*i];
|
assign PIPE_JTAG_RDY[i] = drp_fsm[3*i];
|
assign jtag_sl_en[i] = (jtag_sl_addr[(17*i)+16:(17*i)+9] == 8'd0) ? jtag_sl_den[i] : 1'd0;
|
assign jtag_sl_en[i] = (jtag_sl_addr[(17*i)+16:(17*i)+9] == 8'd0) ? jtag_sl_den[i] : 1'd0;
|
|
|
assign drp_mux_addr[(9*i)+8:(9*i)] = PIPE_JTAG_EN ? jtag_sl_addr[(17*i)+8:(17*i)] : drp_addr[(9*i)+8:(9*i)];
|
assign drp_mux_addr[(9*i)+8:(9*i)] = PIPE_JTAG_EN ? jtag_sl_addr[(17*i)+8:(17*i)] : drp_addr[(9*i)+8:(9*i)];
|
assign drp_mux_en[i] = PIPE_JTAG_EN ? jtag_sl_en[i] : drp_en[i];
|
assign drp_mux_en[i] = PIPE_JTAG_EN ? jtag_sl_en[i] : drp_en[i];
|
assign drp_mux_di[(16*i)+15:(16*i)] = PIPE_JTAG_EN ? jtag_sl_di[(16*i)+15:(16*i)] : drp_di[(16*i)+15:(16*i)];
|
assign drp_mux_di[(16*i)+15:(16*i)] = PIPE_JTAG_EN ? jtag_sl_di[(16*i)+15:(16*i)] : drp_di[(16*i)+15:(16*i)];
|
assign drp_mux_we[i] = PIPE_JTAG_EN ? jtag_sl_we[i] : drp_we[i];
|
assign drp_mux_we[i] = PIPE_JTAG_EN ? jtag_sl_we[i] : drp_we[i];
|
|
|
|
|
|
|
//---------- Generate PIPE EQ ----------------------------------------------
|
//---------- Generate PIPE EQ ----------------------------------------------
|
if (PCIE_LINK_SPEED == 3)
|
if (PCIE_LINK_SPEED == 3)
|
|
|
begin : pipe_eq
|
begin : pipe_eq
|
|
|
//---------- PIPE EQ Module --------------------------------------------
|
//---------- PIPE EQ Module --------------------------------------------
|
cl_a7pcie_x4_pipe_eq #
|
cl_a7pcie_x4_pipe_eq #
|
(
|
(
|
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
|
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
|
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3) // PCIe RX equalization mode
|
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3) // PCIe RX equalization mode
|
)
|
)
|
pipe_eq_i
|
pipe_eq_i
|
(
|
(
|
|
|
//---------- Input -----------------------------
|
//---------- Input -----------------------------
|
.EQ_CLK (clk_pclk),
|
.EQ_CLK (clk_pclk),
|
.EQ_RST_N (!rst_cpllreset),
|
.EQ_RST_N (!rst_cpllreset),
|
.EQ_GEN3 (rate_gen3[i]),
|
.EQ_GEN3 (rate_gen3[i]),
|
|
|
.EQ_TXEQ_CONTROL (PIPE_TXEQ_CONTROL[(2*i)+1:(2*i)]),
|
.EQ_TXEQ_CONTROL (PIPE_TXEQ_CONTROL[(2*i)+1:(2*i)]),
|
.EQ_TXEQ_PRESET (PIPE_TXEQ_PRESET[(4*i)+3:(4*i)]),
|
.EQ_TXEQ_PRESET (PIPE_TXEQ_PRESET[(4*i)+3:(4*i)]),
|
.EQ_TXEQ_PRESET_DEFAULT (PIPE_TXEQ_PRESET_DEFAULT[(4*i)+3:(4*i)]),
|
.EQ_TXEQ_PRESET_DEFAULT (PIPE_TXEQ_PRESET_DEFAULT[(4*i)+3:(4*i)]),
|
.EQ_TXEQ_DEEMPH_IN (PIPE_TXEQ_DEEMPH[(6*i)+5:(6*i)]), // renamed
|
.EQ_TXEQ_DEEMPH_IN (PIPE_TXEQ_DEEMPH[(6*i)+5:(6*i)]), // renamed
|
|
|
.EQ_RXEQ_CONTROL (PIPE_RXEQ_CONTROL[(2*i)+1:(2*i)]),
|
.EQ_RXEQ_CONTROL (PIPE_RXEQ_CONTROL[(2*i)+1:(2*i)]),
|
.EQ_RXEQ_PRESET (PIPE_RXEQ_PRESET[(3*i)+2:(3*i)]),
|
.EQ_RXEQ_PRESET (PIPE_RXEQ_PRESET[(3*i)+2:(3*i)]),
|
.EQ_RXEQ_LFFS (PIPE_RXEQ_LFFS[(6*i)+5:(6*i)]),
|
.EQ_RXEQ_LFFS (PIPE_RXEQ_LFFS[(6*i)+5:(6*i)]),
|
.EQ_RXEQ_TXPRESET (PIPE_RXEQ_TXPRESET[(4*i)+3:(4*i)]),
|
.EQ_RXEQ_TXPRESET (PIPE_RXEQ_TXPRESET[(4*i)+3:(4*i)]),
|
.EQ_RXEQ_USER_EN (PIPE_RXEQ_USER_EN[i]),
|
.EQ_RXEQ_USER_EN (PIPE_RXEQ_USER_EN[i]),
|
.EQ_RXEQ_USER_TXCOEFF (PIPE_RXEQ_USER_TXCOEFF[(18*i)+17:(18*i)]),
|
.EQ_RXEQ_USER_TXCOEFF (PIPE_RXEQ_USER_TXCOEFF[(18*i)+17:(18*i)]),
|
.EQ_RXEQ_USER_MODE (PIPE_RXEQ_USER_MODE[i]),
|
.EQ_RXEQ_USER_MODE (PIPE_RXEQ_USER_MODE[i]),
|
|
|
//---------- Output ----------------------------
|
//---------- Output ----------------------------
|
.EQ_TXEQ_DEEMPH (eq_txeq_deemph[i]),
|
.EQ_TXEQ_DEEMPH (eq_txeq_deemph[i]),
|
.EQ_TXEQ_PRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
|
.EQ_TXEQ_PRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
|
.EQ_TXEQ_MAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
|
.EQ_TXEQ_MAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
|
.EQ_TXEQ_POSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
|
.EQ_TXEQ_POSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
|
.EQ_TXEQ_DEEMPH_OUT (PIPE_TXEQ_COEFF[(18*i)+17:(18*i)]),// renamed
|
.EQ_TXEQ_DEEMPH_OUT (PIPE_TXEQ_COEFF[(18*i)+17:(18*i)]),// renamed
|
.EQ_TXEQ_DONE (PIPE_TXEQ_DONE[i]),
|
.EQ_TXEQ_DONE (PIPE_TXEQ_DONE[i]),
|
.EQ_TXEQ_FSM (PIPE_TXEQ_FSM[(6*i)+5:(6*i)]),
|
.EQ_TXEQ_FSM (PIPE_TXEQ_FSM[(6*i)+5:(6*i)]),
|
|
|
.EQ_RXEQ_NEW_TXCOEFF (PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)]),
|
.EQ_RXEQ_NEW_TXCOEFF (PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)]),
|
.EQ_RXEQ_LFFS_SEL (PIPE_RXEQ_LFFS_SEL[i]),
|
.EQ_RXEQ_LFFS_SEL (PIPE_RXEQ_LFFS_SEL[i]),
|
.EQ_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
|
.EQ_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
|
.EQ_RXEQ_DONE (PIPE_RXEQ_DONE[i]),
|
.EQ_RXEQ_DONE (PIPE_RXEQ_DONE[i]),
|
.EQ_RXEQ_FSM (PIPE_RXEQ_FSM[(6*i)+5:(6*i)])
|
.EQ_RXEQ_FSM (PIPE_RXEQ_FSM[(6*i)+5:(6*i)])
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- PIPE EQ Defaults ------------------------------------------
|
//---------- PIPE EQ Defaults ------------------------------------------
|
begin : pipe_eq_disable
|
begin : pipe_eq_disable
|
assign eq_txeq_deemph[i] = 1'd0;
|
assign eq_txeq_deemph[i] = 1'd0;
|
assign eq_txeq_precursor[(5*i)+4:(5*i)] = 5'h00;
|
assign eq_txeq_precursor[(5*i)+4:(5*i)] = 5'h00;
|
assign eq_txeq_maincursor[(7*i)+6:(7*i)] = 7'h00;
|
assign eq_txeq_maincursor[(7*i)+6:(7*i)] = 7'h00;
|
assign eq_txeq_postcursor[(5*i)+4:(5*i)] = 5'h00;
|
assign eq_txeq_postcursor[(5*i)+4:(5*i)] = 5'h00;
|
assign eq_rxeq_adapt_done[i] = 1'd0;
|
assign eq_rxeq_adapt_done[i] = 1'd0;
|
assign PIPE_TXEQ_COEFF[(18*i)+17:(18*i)] = 18'd0;
|
assign PIPE_TXEQ_COEFF[(18*i)+17:(18*i)] = 18'd0;
|
assign PIPE_TXEQ_DONE[i] = 1'd0;
|
assign PIPE_TXEQ_DONE[i] = 1'd0;
|
assign PIPE_TXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
|
assign PIPE_TXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
|
|
|
assign PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)] = 18'd0;
|
assign PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)] = 18'd0;
|
assign PIPE_RXEQ_LFFS_SEL[i] = 1'd0;
|
assign PIPE_RXEQ_LFFS_SEL[i] = 1'd0;
|
assign PIPE_RXEQ_ADAPT_DONE[i] = 1'd0;
|
assign PIPE_RXEQ_ADAPT_DONE[i] = 1'd0;
|
assign PIPE_RXEQ_DONE[i] = 1'd0;
|
assign PIPE_RXEQ_DONE[i] = 1'd0;
|
assign PIPE_RXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
|
assign PIPE_RXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
|
end
|
end
|
|
|
|
|
|
|
//---------- Generate PIPE Common Per Quad for Gen3 ------------------------
|
//---------- Generate PIPE Common Per Quad for Gen3 ------------------------
|
if ((i%4)==0)
|
if ((i%4)==0)
|
|
|
begin : pipe_quad
|
begin : pipe_quad
|
|
|
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL") || (PCIE_GT_DEVICE == "GTP"))
|
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL") || (PCIE_GT_DEVICE == "GTP"))
|
|
|
begin : pipe_common
|
begin : pipe_common
|
|
|
//---------- QPLL DRP Module ---------------------------------------
|
//---------- QPLL DRP Module ---------------------------------------
|
cl_a7pcie_x4_qpll_drp #
|
cl_a7pcie_x4_qpll_drp #
|
(
|
(
|
|
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
|
|
|
)
|
)
|
qpll_drp_i
|
qpll_drp_i
|
(
|
(
|
|
|
//---------- Input -------------------------
|
//---------- Input -------------------------
|
.DRP_CLK (clk_dclk),
|
.DRP_CLK (clk_dclk),
|
.DRP_RST_N (!rst_dclk_reset),
|
.DRP_RST_N (!rst_dclk_reset),
|
.DRP_OVRD (qrst_ovrd),
|
.DRP_OVRD (qrst_ovrd),
|
.DRP_GEN3 (&rate_gen3),
|
.DRP_GEN3 (&rate_gen3),
|
.DRP_QPLLLOCK (qpll_qplllock[i>>2]),
|
.DRP_QPLLLOCK (qpll_qplllock[i>>2]),
|
.DRP_START (qrst_drp_start),
|
.DRP_START (qrst_drp_start),
|
.DRP_DO (qpll_do[(16*(i>>2))+15:(16*(i>>2))]),
|
.DRP_DO (qpll_do[(16*(i>>2))+15:(16*(i>>2))]),
|
.DRP_RDY (qpll_rdy[i>>2]),
|
.DRP_RDY (qpll_rdy[i>>2]),
|
|
|
//---------- Output ------------------------
|
//---------- Output ------------------------
|
.DRP_ADDR (qdrp_addr[(8*(i>>2))+7:(8*(i>>2))]),
|
.DRP_ADDR (qdrp_addr[(8*(i>>2))+7:(8*(i>>2))]),
|
.DRP_EN (qdrp_en[i>>2]),
|
.DRP_EN (qdrp_en[i>>2]),
|
.DRP_DI (qdrp_di[(16*(i>>2))+15:(16*(i>>2))]),
|
.DRP_DI (qdrp_di[(16*(i>>2))+15:(16*(i>>2))]),
|
.DRP_WE (qdrp_we[i>>2]),
|
.DRP_WE (qdrp_we[i>>2]),
|
.DRP_DONE (qdrp_done[i>>2]),
|
.DRP_DONE (qdrp_done[i>>2]),
|
.DRP_QPLLRESET (qdrp_qpllreset[i>>2]),
|
.DRP_QPLLRESET (qdrp_qpllreset[i>>2]),
|
.DRP_CRSCODE (qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))]),
|
.DRP_CRSCODE (qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))]),
|
.DRP_FSM (qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))])
|
.DRP_FSM (qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))])
|
|
|
);
|
);
|
|
|
|
|
|
|
//---------- QPLL Wrapper ------------------------------------------
|
//---------- QPLL Wrapper ------------------------------------------
|
cl_a7pcie_x4_qpll_wrapper #
|
cl_a7pcie_x4_qpll_wrapper #
|
(
|
(
|
|
|
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
|
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
|
|
|
)
|
)
|
qpll_wrapper_i
|
qpll_wrapper_i
|
(
|
(
|
|
|
//---------- QPLL Clock Ports --------------
|
//---------- QPLL Clock Ports --------------
|
.QPLL_GTGREFCLK (PIPE_CLK),
|
.QPLL_GTGREFCLK (PIPE_CLK),
|
.QPLL_QPLLLOCKDETCLK (1'd0),
|
.QPLL_QPLLLOCKDETCLK (1'd0),
|
|
|
.QPLL_QPLLOUTCLK (qpll_qplloutclk[i>>2]),
|
.QPLL_QPLLOUTCLK (qpll_qplloutclk[i>>2]),
|
.QPLL_QPLLOUTREFCLK (qpll_qplloutrefclk[i>>2]),
|
.QPLL_QPLLOUTREFCLK (qpll_qplloutrefclk[i>>2]),
|
.QPLL_QPLLLOCK (qpll_qplllock[i>>2]),
|
.QPLL_QPLLLOCK (qpll_qplllock[i>>2]),
|
|
|
//---------- QPLL Reset Ports --------------
|
//---------- QPLL Reset Ports --------------
|
.QPLL_QPLLPD (qpllpd),
|
.QPLL_QPLLPD (qpllpd),
|
.QPLL_QPLLRESET (qpllreset[i>>2]),
|
.QPLL_QPLLRESET (qpllreset[i>>2]),
|
|
|
//---------- QPLL DRP Ports ----------------
|
//---------- QPLL DRP Ports ----------------
|
.QPLL_DRPCLK (clk_dclk),
|
.QPLL_DRPCLK (clk_dclk),
|
.QPLL_DRPADDR (qdrp_addr[(8*(i>>2))+7:(8*(i>>2))]),
|
.QPLL_DRPADDR (qdrp_addr[(8*(i>>2))+7:(8*(i>>2))]),
|
.QPLL_DRPEN (qdrp_en[i>>2]),
|
.QPLL_DRPEN (qdrp_en[i>>2]),
|
.QPLL_DRPDI (qdrp_di[(16*(i>>2))+15:(16*(i>>2))]),
|
.QPLL_DRPDI (qdrp_di[(16*(i>>2))+15:(16*(i>>2))]),
|
.QPLL_DRPWE (qdrp_we[i>>2]),
|
.QPLL_DRPWE (qdrp_we[i>>2]),
|
|
|
.QPLL_DRPDO (qpll_do[(16*(i>>2))+15:(16*(i>>2))]),
|
.QPLL_DRPDO (qpll_do[(16*(i>>2))+15:(16*(i>>2))]),
|
.QPLL_DRPRDY (qpll_rdy[i>>2])
|
.QPLL_DRPRDY (qpll_rdy[i>>2])
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- PIPE Common Defaults ----------------------------------
|
//---------- PIPE Common Defaults ----------------------------------
|
begin : pipe_common_disable
|
begin : pipe_common_disable
|
assign qdrp_addr[(8*(i>>2))+7:(8*(i>>2))] = 8'd0;
|
assign qdrp_addr[(8*(i>>2))+7:(8*(i>>2))] = 8'd0;
|
assign qdrp_en[i>>2] = 1'd0;
|
assign qdrp_en[i>>2] = 1'd0;
|
assign qdrp_di[(16*(i>>2))+15:(16*(i>>2))] = 16'd0;
|
assign qdrp_di[(16*(i>>2))+15:(16*(i>>2))] = 16'd0;
|
assign qdrp_we[i>>2] = 1'd0;
|
assign qdrp_we[i>>2] = 1'd0;
|
assign qdrp_done[i>>2] = 1'd0;
|
assign qdrp_done[i>>2] = 1'd0;
|
assign qdrp_qpllreset[i>>2] = 1'd0;
|
assign qdrp_qpllreset[i>>2] = 1'd0;
|
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = 6'd0;
|
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = 6'd0;
|
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = 7'd0;
|
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = 7'd0;
|
|
|
assign qpll_qplloutclk[i>>2] = 1'd0;
|
assign qpll_qplloutclk[i>>2] = 1'd0;
|
assign qpll_qplloutrefclk[i>>2] = 1'd0;
|
assign qpll_qplloutrefclk[i>>2] = 1'd0;
|
assign qpll_qplllock[i>>2] = 1'd0;
|
assign qpll_qplllock[i>>2] = 1'd0;
|
assign qpll_do[(16*(i>>2))+15:(16*(i>>2))] = 16'd0;
|
assign qpll_do[(16*(i>>2))+15:(16*(i>>2))] = 16'd0;
|
assign qpll_rdy[i>>2] = 1'd0;
|
assign qpll_rdy[i>>2] = 1'd0;
|
end
|
end
|
|
|
|
|
//---------- Generate QPLL Powerdown and Reset -------------------------
|
//---------- Generate QPLL Powerdown and Reset -------------------------
|
assign qpllpd = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllpd : qrst_qpllpd;
|
assign qpllpd = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllpd : qrst_qpllpd;
|
assign qpllreset[i>>2] = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllreset : (qrst_qpllreset || qdrp_qpllreset[i>>2]);
|
assign qpllreset[i>>2] = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllreset : (qrst_qpllreset || qdrp_qpllreset[i>>2]);
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- GT Wrapper ----------------------------------------------------
|
//---------- GT Wrapper ----------------------------------------------------
|
cl_a7pcie_x4_gt_wrapper #
|
cl_a7pcie_x4_gt_wrapper #
|
(
|
(
|
|
|
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
|
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
|
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
|
.PCIE_SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // PCIe sim TX electrical idle drive level
|
.PCIE_SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // PCIe sim TX electrical idle drive level
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
|
.PCIE_LPM_DFE (PCIE_LPM_DFE), // PCIe LPM or DFE mode for Gen1/Gen2 only
|
.PCIE_LPM_DFE (PCIE_LPM_DFE), // PCIe LPM or DFE mode for Gen1/Gen2 only
|
.PCIE_LPM_DFE_GEN3 (PCIE_LPM_DFE_GEN3), // PCIe LPM or DFE mode for Gen3 only
|
.PCIE_LPM_DFE_GEN3 (PCIE_LPM_DFE_GEN3), // PCIe LPM or DFE mode for Gen3 only
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
|
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
|
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
|
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
|
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
|
.PCIE_CHAN_BOND (PCIE_CHAN_BOND), // PCIe Channel bonding mode
|
.PCIE_CHAN_BOND (PCIE_CHAN_BOND), // PCIe Channel bonding mode
|
.PCIE_CHAN_BOND_EN (PCIE_CHAN_BOND_EN), // PCIe Channel bonding enable for Gen1/Gen2 only
|
.PCIE_CHAN_BOND_EN (PCIE_CHAN_BOND_EN), // PCIe Channel bonding enable for Gen1/Gen2 only
|
.PCIE_LANE (PCIE_LANE), // PCIe number of lane
|
.PCIE_LANE (PCIE_LANE), // PCIe number of lane
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
|
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
|
.PCIE_TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // PCIe TX electrical idle assert delay
|
.PCIE_TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // PCIe TX electrical idle assert delay
|
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
|
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
|
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
|
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
|
|
|
)
|
)
|
gt_wrapper_i
|
gt_wrapper_i
|
(
|
(
|
|
|
//---------- GT User Ports -------------------------
|
//---------- GT User Ports -------------------------
|
.GT_MASTER (i == 0),
|
.GT_MASTER (i == 0),
|
.GT_GEN3 (rate_gen3[i]),
|
.GT_GEN3 (rate_gen3[i]),
|
.GT_RX_CONVERGE (&user_rx_converge),
|
.GT_RX_CONVERGE (&user_rx_converge),
|
|
|
//---------- GT Clock Ports ------------------------
|
//---------- GT Clock Ports ------------------------
|
.GT_GTREFCLK0 (PIPE_CLK),
|
.GT_GTREFCLK0 (PIPE_CLK),
|
.GT_QPLLCLK (qpll_qplloutclk[i>>2]),
|
.GT_QPLLCLK (qpll_qplloutclk[i>>2]),
|
.GT_QPLLREFCLK (qpll_qplloutrefclk[i>>2]),
|
.GT_QPLLREFCLK (qpll_qplloutrefclk[i>>2]),
|
.GT_TXUSRCLK (clk_pclk),
|
.GT_TXUSRCLK (clk_pclk),
|
.GT_RXUSRCLK (clk_rxusrclk),
|
.GT_RXUSRCLK (clk_rxusrclk),
|
.GT_TXUSRCLK2 (clk_pclk),
|
.GT_TXUSRCLK2 (clk_pclk),
|
.GT_RXUSRCLK2 (clk_rxusrclk),
|
.GT_RXUSRCLK2 (clk_rxusrclk),
|
.GT_OOBCLK (oobclk[i]),
|
.GT_OOBCLK (oobclk[i]),
|
.GT_TXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
|
.GT_TXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
|
.GT_RXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
|
.GT_RXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
|
|
|
.GT_TXOUTCLK (gt_txoutclk[i]),
|
.GT_TXOUTCLK (gt_txoutclk[i]),
|
.GT_RXOUTCLK (gt_rxoutclk[i]),
|
.GT_RXOUTCLK (gt_rxoutclk[i]),
|
.GT_CPLLLOCK (gt_cplllock[i]),
|
.GT_CPLLLOCK (gt_cplllock[i]),
|
.GT_RXCDRLOCK (gt_rxcdrlock[i]),
|
.GT_RXCDRLOCK (gt_rxcdrlock[i]),
|
|
|
//---------- GT Reset Ports ------------------------
|
//---------- GT Reset Ports ------------------------
|
.GT_CPLLPD (rst_cpllpd || rate_cpllpd[i]),
|
.GT_CPLLPD (rst_cpllpd || rate_cpllpd[i]),
|
.GT_CPLLRESET (rst_cpllreset || rate_cpllreset[i]),
|
.GT_CPLLRESET (rst_cpllreset || rate_cpllreset[i]),
|
.GT_TXUSERRDY (rst_userrdy),
|
.GT_TXUSERRDY (rst_userrdy),
|
.GT_RXUSERRDY (rst_userrdy),
|
.GT_RXUSERRDY (rst_userrdy),
|
.GT_RESETOVRD (user_resetovrd[i]),
|
.GT_RESETOVRD (user_resetovrd[i]),
|
.GT_GTTXRESET (rst_gtreset),
|
.GT_GTTXRESET (rst_gtreset),
|
.GT_GTRXRESET (rst_gtreset),
|
.GT_GTRXRESET (rst_gtreset),
|
.GT_TXPMARESET (user_txpmareset[i] || rate_txpmareset[i]),
|
.GT_TXPMARESET (user_txpmareset[i] || rate_txpmareset[i]),
|
.GT_RXPMARESET (user_rxpmareset[i] || rate_rxpmareset[i]),
|
.GT_RXPMARESET (user_rxpmareset[i] || rate_rxpmareset[i]),
|
.GT_RXCDRRESET (user_rxcdrreset[i]),
|
.GT_RXCDRRESET (user_rxcdrreset[i]),
|
.GT_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
|
.GT_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
|
.GT_RXDFELPMRESET (user_rxdfelpmreset[i]),
|
.GT_RXDFELPMRESET (user_rxdfelpmreset[i]),
|
.GT_EYESCANRESET (user_eyescanreset[i]),
|
.GT_EYESCANRESET (user_eyescanreset[i]),
|
.GT_TXPCSRESET (user_txpcsreset[i]),
|
.GT_TXPCSRESET (user_txpcsreset[i]),
|
.GT_RXPCSRESET (user_rxpcsreset[i]),
|
.GT_RXPCSRESET (user_rxpcsreset[i]),
|
.GT_RXBUFRESET (user_rxbufreset[i]),
|
.GT_RXBUFRESET (user_rxbufreset[i]),
|
|
|
.GT_TXRESETDONE (gt_txresetdone[i]),
|
.GT_TXRESETDONE (gt_txresetdone[i]),
|
.GT_RXRESETDONE (gt_rxresetdone[i]),
|
.GT_RXRESETDONE (gt_rxresetdone[i]),
|
.GT_RXPMARESETDONE (gt_rxpmaresetdone[i]),
|
.GT_RXPMARESETDONE (gt_rxpmaresetdone[i]),
|
|
|
//---------- GT TX Data Ports ----------------------
|
//---------- GT TX Data Ports ----------------------
|
.GT_TXDATA (PIPE_TXDATA[(32*i)+31:(32*i)]),
|
.GT_TXDATA (PIPE_TXDATA[(32*i)+31:(32*i)]),
|
.GT_TXDATAK (PIPE_TXDATAK[(4*i)+3:(4*i)]),
|
.GT_TXDATAK (PIPE_TXDATAK[(4*i)+3:(4*i)]),
|
|
|
.GT_TXP (PIPE_TXP[i]),
|
.GT_TXP (PIPE_TXP[i]),
|
.GT_TXN (PIPE_TXN[i]),
|
.GT_TXN (PIPE_TXN[i]),
|
|
|
//---------- GT RX Data Ports ----------------------
|
//---------- GT RX Data Ports ----------------------
|
.GT_RXP (PIPE_RXP[i]),
|
.GT_RXP (PIPE_RXP[i]),
|
.GT_RXN (PIPE_RXN[i]),
|
.GT_RXN (PIPE_RXN[i]),
|
|
|
.GT_RXDATA (PIPE_RXDATA[(32*i)+31:(32*i)]),
|
.GT_RXDATA (PIPE_RXDATA[(32*i)+31:(32*i)]),
|
.GT_RXDATAK (PIPE_RXDATAK[(4*i)+3:(4*i)]),
|
.GT_RXDATAK (PIPE_RXDATAK[(4*i)+3:(4*i)]),
|
|
|
//---------- GT Command Ports ----------------------
|
//---------- GT Command Ports ----------------------
|
.GT_TXDETECTRX (PIPE_TXDETECTRX),
|
.GT_TXDETECTRX (PIPE_TXDETECTRX),
|
.GT_TXELECIDLE (PIPE_TXELECIDLE[i]),
|
.GT_TXELECIDLE (PIPE_TXELECIDLE[i]),
|
.GT_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
|
.GT_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
|
.GT_RXPOLARITY (PIPE_RXPOLARITY[i]),
|
.GT_RXPOLARITY (PIPE_RXPOLARITY[i]),
|
.GT_TXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
|
.GT_TXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
|
.GT_RXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
|
.GT_RXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
|
.GT_TXRATE (rate_rate[(3*i)+2:(3*i)]),
|
.GT_TXRATE (rate_rate[(3*i)+2:(3*i)]),
|
.GT_RXRATE (rate_rate[(3*i)+2:(3*i)]),
|
.GT_RXRATE (rate_rate[(3*i)+2:(3*i)]),
|
|
|
//---------- GT Electrical Command Ports -----------
|
//---------- GT Electrical Command Ports -----------
|
.GT_TXMARGIN (PIPE_TXMARGIN),
|
.GT_TXMARGIN (PIPE_TXMARGIN),
|
.GT_TXSWING (PIPE_TXSWING),
|
.GT_TXSWING (PIPE_TXSWING),
|
.GT_TXDEEMPH (PIPE_TXDEEMPH[i]),
|
.GT_TXDEEMPH (PIPE_TXDEEMPH[i]),
|
.GT_TXPRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
|
.GT_TXPRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
|
.GT_TXMAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
|
.GT_TXMAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
|
.GT_TXPOSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
|
.GT_TXPOSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
|
|
|
//---------- GT Status Ports -----------------------
|
//---------- GT Status Ports -----------------------
|
.GT_RXVALID (gt_rxvalid[i]),
|
.GT_RXVALID (gt_rxvalid[i]),
|
.GT_PHYSTATUS (gt_phystatus[i]),
|
.GT_PHYSTATUS (gt_phystatus[i]),
|
.GT_RXELECIDLE (gt_rxelecidle[i]),
|
.GT_RXELECIDLE (gt_rxelecidle[i]),
|
.GT_RXSTATUS (gt_rxstatus[(3*i)+2:(3*i)]),
|
.GT_RXSTATUS (gt_rxstatus[(3*i)+2:(3*i)]),
|
.GT_RXBUFSTATUS (gt_rxbufstatus[(3*i)+2:(3*i)]),
|
.GT_RXBUFSTATUS (gt_rxbufstatus[(3*i)+2:(3*i)]),
|
.GT_TXRATEDONE (gt_txratedone[i]),
|
.GT_TXRATEDONE (gt_txratedone[i]),
|
.GT_RXRATEDONE (gt_rxratedone[i]),
|
.GT_RXRATEDONE (gt_rxratedone[i]),
|
|
|
//---------- GT DRP Ports --------------------------
|
//---------- GT DRP Ports --------------------------
|
.GT_DRPCLK (clk_dclk),
|
.GT_DRPCLK (clk_dclk),
|
.GT_DRPADDR (drp_mux_addr[(9*i)+8:(9*i)]),
|
.GT_DRPADDR (drp_mux_addr[(9*i)+8:(9*i)]),
|
.GT_DRPEN (drp_mux_en[i]),
|
.GT_DRPEN (drp_mux_en[i]),
|
.GT_DRPDI (drp_mux_di[(16*i)+15:(16*i)]),
|
.GT_DRPDI (drp_mux_di[(16*i)+15:(16*i)]),
|
.GT_DRPWE (drp_mux_we[i]),
|
.GT_DRPWE (drp_mux_we[i]),
|
|
|
.GT_DRPDO (gt_do[(16*i)+15:(16*i)]),
|
.GT_DRPDO (gt_do[(16*i)+15:(16*i)]),
|
.GT_DRPRDY (gt_rdy[i]),
|
.GT_DRPRDY (gt_rdy[i]),
|
|
|
//---------- GT TX Sync Ports ----------------------
|
//---------- GT TX Sync Ports ----------------------
|
.GT_TXPHALIGN (sync_txphalign[i]),
|
.GT_TXPHALIGN (sync_txphalign[i]),
|
.GT_TXPHALIGNEN (sync_txphalignen[i]),
|
.GT_TXPHALIGNEN (sync_txphalignen[i]),
|
.GT_TXPHINIT (sync_txphinit[i]),
|
.GT_TXPHINIT (sync_txphinit[i]),
|
.GT_TXDLYBYPASS (sync_txdlybypass[i]),
|
.GT_TXDLYBYPASS (sync_txdlybypass[i]),
|
.GT_TXDLYSRESET (sync_txdlysreset[i]),
|
.GT_TXDLYSRESET (sync_txdlysreset[i]),
|
.GT_TXDLYEN (sync_txdlyen[i]),
|
.GT_TXDLYEN (sync_txdlyen[i]),
|
|
|
.GT_TXDLYSRESETDONE (gt_txdlysresetdone[i]),
|
.GT_TXDLYSRESETDONE (gt_txdlysresetdone[i]),
|
.GT_TXPHINITDONE (gt_txphinitdone[i]),
|
.GT_TXPHINITDONE (gt_txphinitdone[i]),
|
.GT_TXPHALIGNDONE (gt_txphaligndone[i]),
|
.GT_TXPHALIGNDONE (gt_txphaligndone[i]),
|
|
|
.GT_TXPHDLYRESET (sync_txphdlyreset[i]),
|
.GT_TXPHDLYRESET (sync_txphdlyreset[i]),
|
.GT_TXSYNCMODE (i == 0), // GTH, GTP
|
.GT_TXSYNCMODE (i == 0), // GTH, GTP
|
.GT_TXSYNCIN (gt_txsyncout[0]), // GTH, GTP
|
.GT_TXSYNCIN (gt_txsyncout[0]), // GTH, GTP
|
.GT_TXSYNCALLIN (txsyncallin), // GTH, GTP
|
.GT_TXSYNCALLIN (txsyncallin), // GTH, GTP
|
|
|
.GT_TXSYNCOUT (gt_txsyncout[i]), // GTH, GTP
|
.GT_TXSYNCOUT (gt_txsyncout[i]), // GTH, GTP
|
.GT_TXSYNCDONE (gt_txsyncdone[i]), // GTH, GTP
|
.GT_TXSYNCDONE (gt_txsyncdone[i]), // GTH, GTP
|
|
|
//---------- GT RX Sync Ports ----------------------
|
//---------- GT RX Sync Ports ----------------------
|
.GT_RXPHALIGN (sync_rxphalign[i]),
|
.GT_RXPHALIGN (sync_rxphalign[i]),
|
.GT_RXPHALIGNEN (sync_rxphalignen[i]),
|
.GT_RXPHALIGNEN (sync_rxphalignen[i]),
|
.GT_RXDLYBYPASS (sync_rxdlybypass[i]),
|
.GT_RXDLYBYPASS (sync_rxdlybypass[i]),
|
.GT_RXDLYSRESET (sync_rxdlysreset[i]),
|
.GT_RXDLYSRESET (sync_rxdlysreset[i]),
|
.GT_RXDLYEN (sync_rxdlyen[i]),
|
.GT_RXDLYEN (sync_rxdlyen[i]),
|
.GT_RXDDIEN (sync_rxddien[i]),
|
.GT_RXDDIEN (sync_rxddien[i]),
|
|
|
.GT_RXDLYSRESETDONE (gt_rxdlysresetdone[i]),
|
.GT_RXDLYSRESETDONE (gt_rxdlysresetdone[i]),
|
.GT_RXPHALIGNDONE (gt_rxphaligndone[i]),
|
.GT_RXPHALIGNDONE (gt_rxphaligndone[i]),
|
|
|
.GT_RXSYNCMODE (i == 0), // GTH
|
.GT_RXSYNCMODE (i == 0), // GTH
|
.GT_RXSYNCIN (gt_rxsyncout[0]), // GTH
|
.GT_RXSYNCIN (gt_rxsyncout[0]), // GTH
|
.GT_RXSYNCALLIN (rxsyncallin), // GTH
|
.GT_RXSYNCALLIN (rxsyncallin), // GTH
|
|
|
.GT_RXSYNCOUT (gt_rxsyncout[i]), // GTH
|
.GT_RXSYNCOUT (gt_rxsyncout[i]), // GTH
|
.GT_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
|
.GT_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
|
|
|
//---------- GT Comma Alignment Ports --------------
|
//---------- GT Comma Alignment Ports --------------
|
.GT_RXSLIDE (PIPE_RXSLIDE[i]),
|
.GT_RXSLIDE (PIPE_RXSLIDE[i]),
|
|
|
.GT_RXCOMMADET (gt_rxcommadet[i]),
|
.GT_RXCOMMADET (gt_rxcommadet[i]),
|
.GT_RXCHARISCOMMA (gt_rxchariscomma[(4*i)+3:(4*i)]),
|
.GT_RXCHARISCOMMA (gt_rxchariscomma[(4*i)+3:(4*i)]),
|
.GT_RXBYTEISALIGNED (gt_rxbyteisaligned[i]),
|
.GT_RXBYTEISALIGNED (gt_rxbyteisaligned[i]),
|
.GT_RXBYTEREALIGN (gt_rxbyterealign[i]),
|
.GT_RXBYTEREALIGN (gt_rxbyterealign[i]),
|
|
|
//---------- GT Channel Bonding Ports --------------
|
//---------- GT Channel Bonding Ports --------------
|
.GT_RXCHANISALIGNED (PIPE_RXCHANISALIGNED[i]),
|
.GT_RXCHANISALIGNED (PIPE_RXCHANISALIGNED[i]),
|
.GT_RXCHBONDEN (rxchbonden[i]),
|
.GT_RXCHBONDEN (rxchbonden[i]),
|
.GT_RXCHBONDI (gt_rxchbondi[i]),
|
.GT_RXCHBONDI (gt_rxchbondi[i]),
|
.GT_RXCHBONDLEVEL (gt_rxchbondlevel[(3*i)+2:(3*i)]),
|
.GT_RXCHBONDLEVEL (gt_rxchbondlevel[(3*i)+2:(3*i)]),
|
.GT_RXCHBONDMASTER (rxchbondmaster[i]),
|
.GT_RXCHBONDMASTER (rxchbondmaster[i]),
|
.GT_RXCHBONDSLAVE (rxchbondslave[i]),
|
.GT_RXCHBONDSLAVE (rxchbondslave[i]),
|
.GT_RXCHBONDO (gt_rxchbondo[i+1]),
|
.GT_RXCHBONDO (gt_rxchbondo[i+1]),
|
|
|
//---------- GT PRBS/Loopback Ports ----------------
|
//---------- GT PRBS/Loopback Ports ----------------
|
.GT_TXPRBSSEL (PIPE_TXPRBSSEL),
|
.GT_TXPRBSSEL (PIPE_TXPRBSSEL),
|
.GT_RXPRBSSEL (PIPE_RXPRBSSEL),
|
.GT_RXPRBSSEL (PIPE_RXPRBSSEL),
|
.GT_TXPRBSFORCEERR (PIPE_TXPRBSFORCEERR),
|
.GT_TXPRBSFORCEERR (PIPE_TXPRBSFORCEERR),
|
.GT_RXPRBSCNTRESET (PIPE_RXPRBSCNTRESET),
|
.GT_RXPRBSCNTRESET (PIPE_RXPRBSCNTRESET),
|
.GT_LOOPBACK (PIPE_LOOPBACK),
|
.GT_LOOPBACK (PIPE_LOOPBACK),
|
|
|
.GT_RXPRBSERR (PIPE_RXPRBSERR[i]),
|
.GT_RXPRBSERR (PIPE_RXPRBSERR[i]),
|
|
|
//---------- GT Debug Port -------------------------
|
//---------- GT Debug Port -------------------------
|
.GT_DMONITOROUT (PIPE_DMONITOROUT[(15*i)+14:(15*i)])
|
.GT_DMONITOROUT (PIPE_DMONITOROUT[(15*i)+14:(15*i)])
|
|
|
);
|
);
|
|
|
|
|
|
|
//---------- GT Wrapper Assignments ----------------------------------------
|
//---------- GT Wrapper Assignments ----------------------------------------
|
assign oobclk[i] = (PCIE_OOBCLK_MODE == 1) ? user_oobclk[i] : clk_oobclk;
|
assign oobclk[i] = (PCIE_OOBCLK_MODE == 1) ? user_oobclk[i] : clk_oobclk;
|
|
|
//---------- Channel Bonding Master Slave Enable ---------------------------
|
//---------- Channel Bonding Master Slave Enable ---------------------------
|
if (PCIE_CHAN_BOND_EN == "FALSE")
|
if (PCIE_CHAN_BOND_EN == "FALSE")
|
begin : channel_bonding_ms_disable
|
begin : channel_bonding_ms_disable
|
assign rxchbonden[i] = 1'd0;
|
assign rxchbonden[i] = 1'd0;
|
assign rxchbondmaster[i] = 1'd0;
|
assign rxchbondmaster[i] = 1'd0;
|
assign rxchbondslave[i] = 1'd0;
|
assign rxchbondslave[i] = 1'd0;
|
end
|
end
|
else
|
else
|
begin : channel_bonding_ms_enable
|
begin : channel_bonding_ms_enable
|
assign rxchbonden[i] = (PCIE_LANE > 1) && (PCIE_CHAN_BOND_EN == "TRUE") ? !rate_gen3[i] : 1'd0;
|
assign rxchbonden[i] = (PCIE_LANE > 1) && (PCIE_CHAN_BOND_EN == "TRUE") ? !rate_gen3[i] : 1'd0;
|
assign rxchbondmaster[i] = rate_gen3[i] ? 1'd0 : (i == 0);
|
assign rxchbondmaster[i] = rate_gen3[i] ? 1'd0 : (i == 0);
|
assign rxchbondslave[i] = rate_gen3[i] ? 1'd0 : (i > 0);
|
assign rxchbondslave[i] = rate_gen3[i] ? 1'd0 : (i > 0);
|
end
|
end
|
|
|
//---------- Channel Bonding Input Connection ------------------------------
|
//---------- Channel Bonding Input Connection ------------------------------
|
if (PCIE_CHAN_BOND_EN == "FALSE")
|
if (PCIE_CHAN_BOND_EN == "FALSE")
|
begin : channel_bonding_in_disable
|
begin : channel_bonding_in_disable
|
assign gt_rxchbondi[i] = 5'd0;
|
assign gt_rxchbondi[i] = 5'd0;
|
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
|
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
|
end
|
end
|
else
|
else
|
begin : channel_bonding_in_enable
|
begin : channel_bonding_in_enable
|
|
|
//---------- Channel Bonding (2: Binary-Tree) --------------------------
|
//---------- Channel Bonding (2: Binary-Tree) --------------------------
|
if (PCIE_CHAN_BOND == 2)
|
if (PCIE_CHAN_BOND == 2)
|
|
|
begin : channel_bonding_a
|
begin : channel_bonding_a
|
|
|
case (i)
|
case (i)
|
|
|
//---------- Lane 0 --------------------------------
|
//---------- Lane 0 --------------------------------
|
0 :
|
0 :
|
begin
|
begin
|
assign gt_rxchbondi[0] = gt_rxchbondo[0];
|
assign gt_rxchbondi[0] = gt_rxchbondo[0];
|
assign gt_rxchbondlevel[2:0] = (PCIE_LANE == 4'd8) ? 3'd4 :
|
assign gt_rxchbondlevel[2:0] = (PCIE_LANE == 4'd8) ? 3'd4 :
|
(PCIE_LANE > 4'd5) ? 3'd3 :
|
(PCIE_LANE > 4'd5) ? 3'd3 :
|
(PCIE_LANE > 4'd3) ? 3'd2 :
|
(PCIE_LANE > 4'd3) ? 3'd2 :
|
(PCIE_LANE > 4'd1) ? 3'd1 : 3'd0;
|
(PCIE_LANE > 4'd1) ? 3'd1 : 3'd0;
|
end
|
end
|
//---------- Lane 1 --------------------------------
|
//---------- Lane 1 --------------------------------
|
1 :
|
1 :
|
begin
|
begin
|
assign gt_rxchbondi[1] = gt_rxchbondo[1];
|
assign gt_rxchbondi[1] = gt_rxchbondo[1];
|
assign gt_rxchbondlevel[5:3] = (PCIE_LANE == 4'd8) ? 3'd3 :
|
assign gt_rxchbondlevel[5:3] = (PCIE_LANE == 4'd8) ? 3'd3 :
|
(PCIE_LANE > 4'd5) ? 3'd2 :
|
(PCIE_LANE > 4'd5) ? 3'd2 :
|
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
|
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
|
end
|
end
|
//---------- Lane 2 --------------------------------
|
//---------- Lane 2 --------------------------------
|
2 :
|
2 :
|
begin
|
begin
|
assign gt_rxchbondi[2] = gt_rxchbondo[1];
|
assign gt_rxchbondi[2] = gt_rxchbondo[1];
|
assign gt_rxchbondlevel[8:6] = (PCIE_LANE == 4'd8) ? 3'd3 :
|
assign gt_rxchbondlevel[8:6] = (PCIE_LANE == 4'd8) ? 3'd3 :
|
(PCIE_LANE > 4'd5) ? 3'd2 :
|
(PCIE_LANE > 4'd5) ? 3'd2 :
|
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
|
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
|
end
|
end
|
//---------- Lane 3 --------------------------------
|
//---------- Lane 3 --------------------------------
|
3 :
|
3 :
|
begin
|
begin
|
assign gt_rxchbondi[3] = gt_rxchbondo[3];
|
assign gt_rxchbondi[3] = gt_rxchbondo[3];
|
assign gt_rxchbondlevel[11:9] = (PCIE_LANE == 4'd8) ? 3'd2 :
|
assign gt_rxchbondlevel[11:9] = (PCIE_LANE == 4'd8) ? 3'd2 :
|
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
|
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
|
end
|
end
|
//---------- Lane 4 --------------------------------
|
//---------- Lane 4 --------------------------------
|
4 :
|
4 :
|
begin
|
begin
|
assign gt_rxchbondi[4] = gt_rxchbondo[3];
|
assign gt_rxchbondi[4] = gt_rxchbondo[3];
|
assign gt_rxchbondlevel[14:12] = (PCIE_LANE == 4'd8) ? 3'd2 :
|
assign gt_rxchbondlevel[14:12] = (PCIE_LANE == 4'd8) ? 3'd2 :
|
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
|
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
|
end
|
end
|
//---------- Lane 5 --------------------------------
|
//---------- Lane 5 --------------------------------
|
5 :
|
5 :
|
begin
|
begin
|
assign gt_rxchbondi[5] = gt_rxchbondo[5];
|
assign gt_rxchbondi[5] = gt_rxchbondo[5];
|
assign gt_rxchbondlevel[17:15] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
|
assign gt_rxchbondlevel[17:15] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
|
end
|
end
|
//---------- Lane 6 --------------------------------
|
//---------- Lane 6 --------------------------------
|
6 :
|
6 :
|
begin
|
begin
|
assign gt_rxchbondi[6] = gt_rxchbondo[5];
|
assign gt_rxchbondi[6] = gt_rxchbondo[5];
|
assign gt_rxchbondlevel[20:18] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
|
assign gt_rxchbondlevel[20:18] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
|
end
|
end
|
//---------- Lane 7 --------------------------------
|
//---------- Lane 7 --------------------------------
|
7 :
|
7 :
|
begin
|
begin
|
assign gt_rxchbondi[7] = gt_rxchbondo[7];
|
assign gt_rxchbondi[7] = gt_rxchbondo[7];
|
assign gt_rxchbondlevel[23:21] = 3'd0;
|
assign gt_rxchbondlevel[23:21] = 3'd0;
|
end
|
end
|
//---------- Default -------------------------------
|
//---------- Default -------------------------------
|
default :
|
default :
|
begin
|
begin
|
assign gt_rxchbondi[i] = gt_rxchbondo[7];
|
assign gt_rxchbondi[i] = gt_rxchbondo[7];
|
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
|
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
//---------- Channel Bonding (0: One-Hop, 1: Daisy Chain) --------------
|
//---------- Channel Bonding (0: One-Hop, 1: Daisy Chain) --------------
|
else
|
else
|
|
|
begin : channel_bonding_b
|
begin : channel_bonding_b
|
assign gt_rxchbondi[i] = (PCIE_CHAN_BOND == 1) ? gt_rxchbondo[i] : ((i == 0) ? gt_rxchbondo[0] : gt_rxchbondo[1]);
|
assign gt_rxchbondi[i] = (PCIE_CHAN_BOND == 1) ? gt_rxchbondo[i] : ((i == 0) ? gt_rxchbondo[0] : gt_rxchbondo[1]);
|
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = (PCIE_CHAN_BOND == 1) ? (PCIE_LANE-1)-i : ((PCIE_LANE > 1) && (i == 0));
|
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = (PCIE_CHAN_BOND == 1) ? (PCIE_LANE-1)-i : ((PCIE_LANE > 1) && (i == 0));
|
end
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
//---------- PIPE Wrapper Output -----------------------------------------------
|
//---------- PIPE Wrapper Output -----------------------------------------------
|
assign PIPE_TXEQ_FS = 0;//TXEQ_FS;
|
assign PIPE_TXEQ_FS = 0;//TXEQ_FS;
|
assign PIPE_TXEQ_LF = 0;//TXEQ_LF;
|
assign PIPE_TXEQ_LF = 0;//TXEQ_LF;
|
assign PIPE_RXELECIDLE = gt_rxelecidle;
|
assign PIPE_RXELECIDLE = gt_rxelecidle;
|
assign PIPE_RXSTATUS = gt_rxstatus;
|
assign PIPE_RXSTATUS = gt_rxstatus;
|
assign PIPE_RXBUFSTATUS = 0;//gt_rxbufstatus;
|
assign PIPE_RXBUFSTATUS = 0;//gt_rxbufstatus;
|
|
|
assign PIPE_CPLL_LOCK = gt_cplllock;
|
assign PIPE_CPLL_LOCK = gt_cplllock;
|
assign PIPE_QPLL_LOCK = 0;//qpll_qplllock;
|
assign PIPE_QPLL_LOCK = 0;//qpll_qplllock;
|
assign PIPE_PCLK = clk_pclk;
|
assign PIPE_PCLK = clk_pclk;
|
assign PIPE_PCLK_LOCK = clk_mmcm_lock;
|
assign PIPE_PCLK_LOCK = clk_mmcm_lock;
|
assign PIPE_RXCDRLOCK = 0;//user_rxcdrlock;
|
assign PIPE_RXCDRLOCK = 0;//user_rxcdrlock;
|
assign PIPE_RXUSRCLK = 0;//clk_rxusrclk;
|
assign PIPE_RXUSRCLK = 0;//clk_rxusrclk;
|
assign PIPE_RXOUTCLK = 0;//clk_rxoutclk;
|
assign PIPE_RXOUTCLK = 0;//clk_rxoutclk;
|
assign PIPE_TXSYNC_DONE = 0;//sync_txsync_done;
|
assign PIPE_TXSYNC_DONE = 0;//sync_txsync_done;
|
assign PIPE_RXSYNC_DONE = 0;//sync_rxsync_done;
|
assign PIPE_RXSYNC_DONE = 0;//sync_rxsync_done;
|
assign PIPE_ACTIVE_LANE = 0;//user_active_lane;
|
assign PIPE_ACTIVE_LANE = 0;//user_active_lane;
|
|
|
assign PIPE_TXOUTCLK_OUT = gt_txoutclk[0];
|
assign PIPE_TXOUTCLK_OUT = gt_txoutclk[0];
|
assign PIPE_RXOUTCLK_OUT = gt_rxoutclk;
|
assign PIPE_RXOUTCLK_OUT = gt_rxoutclk;
|
assign PIPE_PCLK_SEL_OUT = rate_pclk_sel;
|
assign PIPE_PCLK_SEL_OUT = rate_pclk_sel;
|
assign PIPE_GEN3_OUT = rate_gen3[0];
|
assign PIPE_GEN3_OUT = rate_gen3[0];
|
|
|
assign PIPE_RXEQ_CONVERGE = user_rx_converge;
|
assign PIPE_RXEQ_CONVERGE = user_rx_converge;
|
assign PIPE_RXEQ_ADAPT_DONE = (PCIE_GT_DEVICE == "GTP") ? {PCIE_LANE{1'd0}} : eq_rxeq_adapt_done;
|
assign PIPE_RXEQ_ADAPT_DONE = (PCIE_GT_DEVICE == "GTP") ? {PCIE_LANE{1'd0}} : eq_rxeq_adapt_done;
|
|
|
assign PIPE_RST_FSM = 0;//rst_fsm;
|
assign PIPE_RST_FSM = 0;//rst_fsm;
|
assign PIPE_QRST_FSM = 0;//qrst_fsm;
|
assign PIPE_QRST_FSM = 0;//qrst_fsm;
|
assign PIPE_RATE_FSM = 0;//rate_fsm;
|
assign PIPE_RATE_FSM = 0;//rate_fsm;
|
assign PIPE_SYNC_FSM_TX = 0;//sync_fsm_tx;
|
assign PIPE_SYNC_FSM_TX = 0;//sync_fsm_tx;
|
assign PIPE_SYNC_FSM_RX = 0;//sync_fsm_rx;
|
assign PIPE_SYNC_FSM_RX = 0;//sync_fsm_rx;
|
assign PIPE_DRP_FSM = 0;//drp_fsm;
|
assign PIPE_DRP_FSM = 0;//drp_fsm;
|
assign PIPE_QDRP_FSM = 0;//qdrp_fsm;
|
assign PIPE_QDRP_FSM = 0;//qdrp_fsm;
|
|
|
assign PIPE_RST_IDLE = 0;//&rst_idle;
|
assign PIPE_RST_IDLE = 0;//&rst_idle;
|
assign PIPE_QRST_IDLE = 0;//&qrst_idle;
|
assign PIPE_QRST_IDLE = 0;//&qrst_idle;
|
assign PIPE_RATE_IDLE = 0;//&rate_idle;
|
assign PIPE_RATE_IDLE = 0;//&rate_idle;
|
|
|
assign PIPE_DEBUG_0 = (PCIE_DEBUG_MODE == 1) ? gt_txresetdone : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_0 = (PCIE_DEBUG_MODE == 1) ? gt_txresetdone : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_1 = (PCIE_DEBUG_MODE == 1) ? gt_rxresetdone : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_1 = (PCIE_DEBUG_MODE == 1) ? gt_rxresetdone : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_2 = (PCIE_DEBUG_MODE == 1) ? gt_phystatus : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_2 = (PCIE_DEBUG_MODE == 1) ? gt_phystatus : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_3 = (PCIE_DEBUG_MODE == 1) ? gt_rxvalid : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_3 = (PCIE_DEBUG_MODE == 1) ? gt_rxvalid : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_4 = (PCIE_DEBUG_MODE == 1) ? clk_dclk : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_4 = (PCIE_DEBUG_MODE == 1) ? clk_dclk : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_5 = (PCIE_DEBUG_MODE == 1) ? drp_mux_en : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_5 = (PCIE_DEBUG_MODE == 1) ? drp_mux_en : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_6 = (PCIE_DEBUG_MODE == 1) ? drp_mux_we : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_6 = (PCIE_DEBUG_MODE == 1) ? drp_mux_we : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_7 = (PCIE_DEBUG_MODE == 1) ? gt_rdy : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_7 = (PCIE_DEBUG_MODE == 1) ? gt_rdy : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_8 = (PCIE_DEBUG_MODE == 1) ? user_rx_converge : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_8 = (PCIE_DEBUG_MODE == 1) ? user_rx_converge : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_9 = (PCIE_DEBUG_MODE == 1) ? PIPE_TXELECIDLE : {PCIE_LANE{1'b0}};
|
assign PIPE_DEBUG_9 = (PCIE_DEBUG_MODE == 1) ? PIPE_TXELECIDLE : {PCIE_LANE{1'b0}};
|
|
|
assign PIPE_DEBUG[ 1:0] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_CONTROL[1:0] : 2'd0;
|
assign PIPE_DEBUG[ 1:0] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_CONTROL[1:0] : 2'd0;
|
assign PIPE_DEBUG[ 5:2] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_PRESET[3:0] : 4'd0;
|
assign PIPE_DEBUG[ 5:2] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_PRESET[3:0] : 4'd0;
|
assign PIPE_DEBUG[31:6] = 26'd0;
|
assign PIPE_DEBUG[31:6] = 26'd0;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|