//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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//
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// This file contains confidential and proprietary information
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// international copyright and other intellectual property
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//
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_qpll_drp.v
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// File : cl_a7pcie_x4_qpll_drp.v
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// Version : 1.9
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// Version : 1.10
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : qpll_drp.v
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// Filename : qpll_drp.v
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// Description : QPLL DRP Module for 7 Series Transceiver
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// Description : QPLL DRP Module for 7 Series Transceiver
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// Version : 18.2
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// Version : 18.2
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//---------- QPLL DRP Module ---------------------------------------------------
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//---------- QPLL DRP Module ---------------------------------------------------
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module cl_a7pcie_x4_qpll_drp #
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module cl_a7pcie_x4_qpll_drp #
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(
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(
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_USE_MODE = "3.0", // PCIe use mode
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parameter PCIE_USE_MODE = "3.0", // PCIe use mode
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parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
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parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
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parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
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parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
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parameter LOAD_CNT_MAX = 2'd3, // Load max count
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parameter LOAD_CNT_MAX = 2'd3, // Load max count
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parameter INDEX_MAX = 3'd6 // Index max count
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parameter INDEX_MAX = 3'd6 // Index max count
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)
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)
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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input DRP_CLK,
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input DRP_CLK,
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input DRP_RST_N,
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input DRP_RST_N,
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input DRP_OVRD,
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input DRP_OVRD,
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input DRP_GEN3,
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input DRP_GEN3,
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input DRP_QPLLLOCK,
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input DRP_QPLLLOCK,
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input DRP_START,
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input DRP_START,
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input [15:0] DRP_DO,
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input [15:0] DRP_DO,
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input DRP_RDY,
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input DRP_RDY,
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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output [ 7:0] DRP_ADDR,
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output [ 7:0] DRP_ADDR,
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output DRP_EN,
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output DRP_EN,
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output [15:0] DRP_DI,
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output [15:0] DRP_DI,
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output DRP_WE,
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output DRP_WE,
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output DRP_DONE,
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output DRP_DONE,
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output DRP_QPLLRESET,
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output DRP_QPLLRESET,
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output [ 5:0] DRP_CRSCODE,
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output [ 5:0] DRP_CRSCODE,
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output [ 8:0] DRP_FSM
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output [ 8:0] DRP_FSM
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);
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);
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//---------- Input Registers ---------------------------
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//---------- Input Registers ---------------------------
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reg ovrd_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg1;
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reg gen3_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
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reg qplllock_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
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reg start_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
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reg [15:0] do_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
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reg rdy_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
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reg ovrd_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg2;
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reg gen3_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
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reg qplllock_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
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reg start_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
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reg [15:0] do_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
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reg rdy_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
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//---------- Internal Signals --------------------------
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//---------- Internal Signals --------------------------
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reg [ 1:0] load_cnt = 2'd0;
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reg [ 1:0] load_cnt = 2'd0;
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reg [ 2:0] index = 3'd0;
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reg [ 2:0] index = 3'd0;
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reg mode = 1'd0;
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reg mode = 1'd0;
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reg [ 5:0] crscode = 6'd0;
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reg [ 5:0] crscode = 6'd0;
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//---------- Output Registers --------------------------
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//---------- Output Registers --------------------------
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reg [ 7:0] addr = 8'd0;
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reg [ 7:0] addr = 8'd0;
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reg [15:0] di = 16'd0;
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reg [15:0] di = 16'd0;
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reg done = 1'd0;
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reg done = 1'd0;
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reg [ 8:0] fsm = 7'd1;
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reg [ 8:0] fsm = 7'd1;
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//---------- DRP Address -------------------------------
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//---------- DRP Address -------------------------------
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localparam ADDR_QPLL_FBDIV = 8'h36;
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localparam ADDR_QPLL_FBDIV = 8'h36;
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localparam ADDR_QPLL_CFG = 8'h32;
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localparam ADDR_QPLL_CFG = 8'h32;
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localparam ADDR_QPLL_LPF = 8'h31;
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localparam ADDR_QPLL_LPF = 8'h31;
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localparam ADDR_CRSCODE = 8'h88;
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localparam ADDR_CRSCODE = 8'h88;
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localparam ADDR_QPLL_COARSE_FREQ_OVRD = 8'h35;
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localparam ADDR_QPLL_COARSE_FREQ_OVRD = 8'h35;
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localparam ADDR_QPLL_COARSE_FREQ_OVRD_EN = 8'h36;
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localparam ADDR_QPLL_COARSE_FREQ_OVRD_EN = 8'h36;
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localparam ADDR_QPLL_LOCK_CFG = 8'h34;
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localparam ADDR_QPLL_LOCK_CFG = 8'h34;
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//---------- DRP Mask ----------------------------------
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//---------- DRP Mask ----------------------------------
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localparam MASK_QPLL_FBDIV = 16'b1111110000000000; // Unmask bit [ 9: 0]
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localparam MASK_QPLL_FBDIV = 16'b1111110000000000; // Unmask bit [ 9: 0]
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localparam MASK_QPLL_CFG = 16'b1111111110111111; // Unmask bit [ 6]
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localparam MASK_QPLL_CFG = 16'b1111111110111111; // Unmask bit [ 6]
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localparam MASK_QPLL_LPF = 16'b1000011111111111; // Unmask bit [14:11]
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localparam MASK_QPLL_LPF = 16'b1000011111111111; // Unmask bit [14:11]
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localparam MASK_QPLL_COARSE_FREQ_OVRD = 16'b0000001111111111; // Unmask bit [15:10]
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localparam MASK_QPLL_COARSE_FREQ_OVRD = 16'b0000001111111111; // Unmask bit [15:10]
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localparam MASK_QPLL_COARSE_FREQ_OVRD_EN = 16'b1111011111111111; // Unmask bit [ 11]
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localparam MASK_QPLL_COARSE_FREQ_OVRD_EN = 16'b1111011111111111; // Unmask bit [ 11]
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localparam MASK_QPLL_LOCK_CFG = 16'b1110011111111111; // Unmask bit [12:11]
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localparam MASK_QPLL_LOCK_CFG = 16'b1110011111111111; // Unmask bit [12:11]
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//---------- DRP Data for Normal QPLLLOCK Mode ---------
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//---------- DRP Data for Normal QPLLLOCK Mode ---------
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localparam NORM_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
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localparam NORM_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
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localparam NORM_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000000000000000; // Normal QPLL lock
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localparam NORM_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000000000000000; // Normal QPLL lock
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localparam NORM_QPLL_LOCK_CFG = 16'b0000000000000000; // Normal QPLL lock config
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localparam NORM_QPLL_LOCK_CFG = 16'b0000000000000000; // Normal QPLL lock config
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//---------- DRP Data for Optimize QPLLLOCK Mode -------
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//---------- DRP Data for Optimize QPLLLOCK Mode -------
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localparam OVRD_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
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localparam OVRD_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
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localparam OVRD_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000100000000000; // Override QPLL lock
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localparam OVRD_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000100000000000; // Override QPLL lock
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localparam OVRD_QPLL_LOCK_CFG = 16'b0000000000000000; // Override QPLL lock config
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localparam OVRD_QPLL_LOCK_CFG = 16'b0000000000000000; // Override QPLL lock config
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//---------- Select QPLL Feedback Divider --------------
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//---------- Select QPLL Feedback Divider --------------
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// N = 100 for 100 MHz ref clk and 10Gb/s line rate
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// N = 100 for 100 MHz ref clk and 10Gb/s line rate
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// N = 80 for 125 MHz ref clk and 10Gb/s line rate
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// N = 80 for 125 MHz ref clk and 10Gb/s line rate
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// N = 40 for 250 MHz ref clk and 10Gb/s line rate
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// N = 40 for 250 MHz ref clk and 10Gb/s line rate
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//------------------------------------------------------
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//------------------------------------------------------
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// N = 80 for 100 MHz ref clk and 8Gb/s line rate
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// N = 80 for 100 MHz ref clk and 8Gb/s line rate
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// N = 64 for 125 MHz ref clk and 8Gb/s line rate
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// N = 64 for 125 MHz ref clk and 8Gb/s line rate
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// N = 32 for 250 MHz ref clk and 8Gb/s line rate
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// N = 32 for 250 MHz ref clk and 8Gb/s line rate
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//------------------------------------------------------
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//------------------------------------------------------
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localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000010000000 :
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localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000010000000 :
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000100100000 :
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000100100000 :
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(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000101110000 :
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(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000101110000 :
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(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000001100000 :
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(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000001100000 :
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000011100000 : 16'b0000000100100000;
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000011100000 : 16'b0000000100100000;
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localparam GEN12_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000010000000 :
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localparam GEN12_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000010000000 :
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(PCIE_REFCLK_FREQ == 1) ? 16'b0000000100100000 : 16'b0000000101110000;
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(PCIE_REFCLK_FREQ == 1) ? 16'b0000000100100000 : 16'b0000000101110000;
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localparam GEN3_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000001100000 :
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localparam GEN3_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000001100000 :
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(PCIE_REFCLK_FREQ == 1) ? 16'b0000000011100000 : 16'b0000000100100000;
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(PCIE_REFCLK_FREQ == 1) ? 16'b0000000011100000 : 16'b0000000100100000;
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//---------- Select QPLL Configuration ---------------------------
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//---------- Select QPLL Configuration ---------------------------
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// QPLL_CFG[6] = 0 for upper band
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// QPLL_CFG[6] = 0 for upper band
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// = 1 for lower band
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// = 1 for lower band
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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localparam GEN12_QPLL_CFG = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000000 : 16'b0000000001000000;
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localparam GEN12_QPLL_CFG = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000000 : 16'b0000000001000000;
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localparam GEN3_QPLL_CFG = 16'b0000000001000000;
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localparam GEN3_QPLL_CFG = 16'b0000000001000000;
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//---------- Select QPLL LPF -------------------------------------
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//---------- Select QPLL LPF -------------------------------------
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localparam GEN12_QPLL_LPF = (PCIE_PLL_SEL == "QPLL") ? 16'b0_0100_00000000000 : 16'b0_1101_00000000000;
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localparam GEN12_QPLL_LPF = (PCIE_PLL_SEL == "QPLL") ? 16'b0_0100_00000000000 : 16'b0_1101_00000000000;
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localparam GEN3_QPLL_LPF = 16'b0_1101_00000000000;
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localparam GEN3_QPLL_LPF = 16'b0_1101_00000000000;
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//---------- DRP Data ----------------------------------
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//---------- DRP Data ----------------------------------
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wire [15:0] data_qpll_fbdiv;
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wire [15:0] data_qpll_fbdiv;
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wire [15:0] data_qpll_cfg;
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wire [15:0] data_qpll_cfg;
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wire [15:0] data_qpll_lpf;
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wire [15:0] data_qpll_lpf;
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wire [15:0] data_qpll_coarse_freq_ovrd;
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wire [15:0] data_qpll_coarse_freq_ovrd;
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wire [15:0] data_qpll_coarse_freq_ovrd_en;
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wire [15:0] data_qpll_coarse_freq_ovrd_en;
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wire [15:0] data_qpll_lock_cfg;
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wire [15:0] data_qpll_lock_cfg;
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//---------- FSM ---------------------------------------
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 9'b000000001;
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localparam FSM_IDLE = 9'b000000001;
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localparam FSM_LOAD = 9'b000000010;
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localparam FSM_LOAD = 9'b000000010;
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localparam FSM_READ = 9'b000000100;
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localparam FSM_READ = 9'b000000100;
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localparam FSM_RRDY = 9'b000001000;
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localparam FSM_RRDY = 9'b000001000;
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localparam FSM_WRITE = 9'b000010000;
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localparam FSM_WRITE = 9'b000010000;
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localparam FSM_WRDY = 9'b000100000;
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localparam FSM_WRDY = 9'b000100000;
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localparam FSM_DONE = 9'b001000000;
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localparam FSM_DONE = 9'b001000000;
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localparam FSM_QPLLRESET = 9'b010000000;
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localparam FSM_QPLLRESET = 9'b010000000;
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localparam FSM_QPLLLOCK = 9'b100000000;
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localparam FSM_QPLLLOCK = 9'b100000000;
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//---------- Input FF ----------------------------------------------------------
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge DRP_CLK)
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always @ (posedge DRP_CLK)
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begin
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begin
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if (!DRP_RST_N)
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if (!DRP_RST_N)
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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ovrd_reg1 <= 1'd0;
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ovrd_reg1 <= 1'd0;
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gen3_reg1 <= 1'd0;
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gen3_reg1 <= 1'd0;
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qplllock_reg1 <= 1'd0;
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qplllock_reg1 <= 1'd0;
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start_reg1 <= 1'd0;
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start_reg1 <= 1'd0;
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do_reg1 <= 16'd0;
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do_reg1 <= 16'd0;
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rdy_reg1 <= 1'd0;
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rdy_reg1 <= 1'd0;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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ovrd_reg2 <= 1'd0;
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ovrd_reg2 <= 1'd0;
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gen3_reg2 <= 1'd0;
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gen3_reg2 <= 1'd0;
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qplllock_reg2 <= 1'd0;
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qplllock_reg2 <= 1'd0;
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start_reg2 <= 1'd0;
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start_reg2 <= 1'd0;
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do_reg2 <= 16'd0;
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do_reg2 <= 16'd0;
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rdy_reg2 <= 1'd0;
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rdy_reg2 <= 1'd0;
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end
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end
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else
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else
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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ovrd_reg1 <= DRP_OVRD;
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ovrd_reg1 <= DRP_OVRD;
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gen3_reg1 <= DRP_GEN3;
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gen3_reg1 <= DRP_GEN3;
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qplllock_reg1 <= DRP_QPLLLOCK;
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qplllock_reg1 <= DRP_QPLLLOCK;
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start_reg1 <= DRP_START;
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start_reg1 <= DRP_START;
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do_reg1 <= DRP_DO;
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do_reg1 <= DRP_DO;
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rdy_reg1 <= DRP_RDY;
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rdy_reg1 <= DRP_RDY;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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ovrd_reg2 <= ovrd_reg1;
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ovrd_reg2 <= ovrd_reg1;
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gen3_reg2 <= gen3_reg1;
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gen3_reg2 <= gen3_reg1;
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qplllock_reg2 <= qplllock_reg1;
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qplllock_reg2 <= qplllock_reg1;
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start_reg2 <= start_reg1;
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start_reg2 <= start_reg1;
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do_reg2 <= do_reg1;
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do_reg2 <= do_reg1;
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rdy_reg2 <= rdy_reg1;
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rdy_reg2 <= rdy_reg1;
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end
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end
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end
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end
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//---------- Select DRP Data ---------------------------------------------------
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//---------- Select DRP Data ---------------------------------------------------
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assign data_qpll_fbdiv = (gen3_reg2) ? GEN3_QPLL_FBDIV : GEN12_QPLL_FBDIV;
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assign data_qpll_fbdiv = (gen3_reg2) ? GEN3_QPLL_FBDIV : GEN12_QPLL_FBDIV;
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assign data_qpll_cfg = (gen3_reg2) ? GEN3_QPLL_CFG : GEN12_QPLL_CFG;
|
assign data_qpll_cfg = (gen3_reg2) ? GEN3_QPLL_CFG : GEN12_QPLL_CFG;
|
assign data_qpll_lpf = (gen3_reg2) ? GEN3_QPLL_LPF : GEN12_QPLL_LPF;
|
assign data_qpll_lpf = (gen3_reg2) ? GEN3_QPLL_LPF : GEN12_QPLL_LPF;
|
assign data_qpll_coarse_freq_ovrd = NORM_QPLL_COARSE_FREQ_OVRD;
|
assign data_qpll_coarse_freq_ovrd = NORM_QPLL_COARSE_FREQ_OVRD;
|
assign data_qpll_coarse_freq_ovrd_en = (ovrd_reg2) ? OVRD_QPLL_COARSE_FREQ_OVRD_EN : NORM_QPLL_COARSE_FREQ_OVRD_EN;
|
assign data_qpll_coarse_freq_ovrd_en = (ovrd_reg2) ? OVRD_QPLL_COARSE_FREQ_OVRD_EN : NORM_QPLL_COARSE_FREQ_OVRD_EN;
|
assign data_qpll_lock_cfg = (ovrd_reg2) ? OVRD_QPLL_LOCK_CFG : NORM_QPLL_LOCK_CFG;
|
assign data_qpll_lock_cfg = (ovrd_reg2) ? OVRD_QPLL_LOCK_CFG : NORM_QPLL_LOCK_CFG;
|
|
|
|
|
//---------- Load Counter ------------------------------------------------------
|
//---------- Load Counter ------------------------------------------------------
|
always @ (posedge DRP_CLK)
|
always @ (posedge DRP_CLK)
|
begin
|
begin
|
|
|
if (!DRP_RST_N)
|
if (!DRP_RST_N)
|
load_cnt <= 2'd0;
|
load_cnt <= 2'd0;
|
else
|
else
|
|
|
//---------- Increment Load Counter ----------------
|
//---------- Increment Load Counter ----------------
|
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
|
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
|
load_cnt <= load_cnt + 2'd1;
|
load_cnt <= load_cnt + 2'd1;
|
|
|
//---------- Hold Load Counter ---------------------
|
//---------- Hold Load Counter ---------------------
|
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
|
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
|
load_cnt <= load_cnt;
|
load_cnt <= load_cnt;
|
|
|
//---------- Reset Load Counter --------------------
|
//---------- Reset Load Counter --------------------
|
else
|
else
|
load_cnt <= 2'd0;
|
load_cnt <= 2'd0;
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- Update DRP Address and Data ---------------------------------------
|
//---------- Update DRP Address and Data ---------------------------------------
|
always @ (posedge DRP_CLK)
|
always @ (posedge DRP_CLK)
|
begin
|
begin
|
|
|
if (!DRP_RST_N)
|
if (!DRP_RST_N)
|
begin
|
begin
|
addr <= 8'd0;
|
addr <= 8'd0;
|
di <= 16'd0;
|
di <= 16'd0;
|
crscode <= 6'd0;
|
crscode <= 6'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
case (index)
|
case (index)
|
|
|
//--------------------------------------------------
|
//--------------------------------------------------
|
3'd0 :
|
3'd0 :
|
begin
|
begin
|
addr <= ADDR_QPLL_FBDIV;
|
addr <= ADDR_QPLL_FBDIV;
|
di <= (do_reg2 & MASK_QPLL_FBDIV) | (mode ? data_qpll_fbdiv : QPLL_FBDIV);
|
di <= (do_reg2 & MASK_QPLL_FBDIV) | (mode ? data_qpll_fbdiv : QPLL_FBDIV);
|
crscode <= crscode;
|
crscode <= crscode;
|
end
|
end
|
|
|
//--------------------------------------------------
|
//--------------------------------------------------
|
3'd1 :
|
3'd1 :
|
begin
|
begin
|
addr <= ADDR_QPLL_CFG;
|
addr <= ADDR_QPLL_CFG;
|
if (PCIE_GT_DEVICE == "GTX")
|
if (PCIE_GT_DEVICE == "GTX")
|
di <= (do_reg2 & MASK_QPLL_CFG) | data_qpll_cfg;
|
di <= (do_reg2 & MASK_QPLL_CFG) | data_qpll_cfg;
|
else
|
else
|
di <= (do_reg2 & 16'hFFFF) | data_qpll_cfg;
|
di <= (do_reg2 & 16'hFFFF) | data_qpll_cfg;
|
crscode <= crscode;
|
crscode <= crscode;
|
end
|
end
|
|
|
//--------------------------------------------------
|
//--------------------------------------------------
|
3'd2 :
|
3'd2 :
|
begin
|
begin
|
addr <= ADDR_QPLL_LPF;
|
addr <= ADDR_QPLL_LPF;
|
if (PCIE_GT_DEVICE == "GTX")
|
if (PCIE_GT_DEVICE == "GTX")
|
di <= (do_reg2 & MASK_QPLL_LPF) | data_qpll_lpf;
|
di <= (do_reg2 & MASK_QPLL_LPF) | data_qpll_lpf;
|
else
|
else
|
di <= (do_reg2 & 16'hFFFF) | data_qpll_lpf;
|
di <= (do_reg2 & 16'hFFFF) | data_qpll_lpf;
|
crscode <= crscode;
|
crscode <= crscode;
|
end
|
end
|
|
|
//--------------------------------------------------
|
//--------------------------------------------------
|
3'd3 :
|
3'd3 :
|
begin
|
begin
|
addr <= ADDR_CRSCODE;
|
addr <= ADDR_CRSCODE;
|
di <= do_reg2;
|
di <= do_reg2;
|
|
|
//---------- Latch CRS Code --------------------
|
//---------- Latch CRS Code --------------------
|
if (ovrd_reg2)
|
if (ovrd_reg2)
|
crscode <= do_reg2[6:1];
|
crscode <= do_reg2[6:1];
|
else
|
else
|
crscode <= crscode;
|
crscode <= crscode;
|
end
|
end
|
|
|
//--------------------------------------------------
|
//--------------------------------------------------
|
3'd4 :
|
3'd4 :
|
begin
|
begin
|
addr <= ADDR_QPLL_COARSE_FREQ_OVRD;
|
addr <= ADDR_QPLL_COARSE_FREQ_OVRD;
|
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD) | {(crscode - 6'd1), data_qpll_coarse_freq_ovrd[9:0]};
|
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD) | {(crscode - 6'd1), data_qpll_coarse_freq_ovrd[9:0]};
|
crscode <= crscode;
|
crscode <= crscode;
|
end
|
end
|
|
|
//--------------------------------------------------
|
//--------------------------------------------------
|
3'd5 :
|
3'd5 :
|
begin
|
begin
|
addr <= ADDR_QPLL_COARSE_FREQ_OVRD_EN;
|
addr <= ADDR_QPLL_COARSE_FREQ_OVRD_EN;
|
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD_EN) | data_qpll_coarse_freq_ovrd_en;
|
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD_EN) | data_qpll_coarse_freq_ovrd_en;
|
crscode <= crscode;
|
crscode <= crscode;
|
end
|
end
|
|
|
//--------------------------------------------------
|
//--------------------------------------------------
|
3'd6 :
|
3'd6 :
|
begin
|
begin
|
addr <= ADDR_QPLL_LOCK_CFG;
|
addr <= ADDR_QPLL_LOCK_CFG;
|
di <= (do_reg2 & MASK_QPLL_LOCK_CFG) | data_qpll_lock_cfg;
|
di <= (do_reg2 & MASK_QPLL_LOCK_CFG) | data_qpll_lock_cfg;
|
crscode <= crscode;
|
crscode <= crscode;
|
end
|
end
|
|
|
//--------------------------------------------------
|
//--------------------------------------------------
|
default :
|
default :
|
begin
|
begin
|
addr <= 8'd0;
|
addr <= 8'd0;
|
di <= 16'd0;
|
di <= 16'd0;
|
crscode <= 6'd0;
|
crscode <= 6'd0;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- QPLL DRP FSM ------------------------------------------------------
|
//---------- QPLL DRP FSM ------------------------------------------------------
|
always @ (posedge DRP_CLK)
|
always @ (posedge DRP_CLK)
|
begin
|
begin
|
|
|
if (!DRP_RST_N)
|
if (!DRP_RST_N)
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
index <= 3'd0;
|
index <= 3'd0;
|
mode <= 1'd0;
|
mode <= 1'd0;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
case (fsm)
|
case (fsm)
|
|
|
//---------- Idle State ----------------------------
|
//---------- Idle State ----------------------------
|
FSM_IDLE :
|
FSM_IDLE :
|
|
|
begin
|
begin
|
if (start_reg2)
|
if (start_reg2)
|
begin
|
begin
|
fsm <= FSM_LOAD;
|
fsm <= FSM_LOAD;
|
index <= 3'd0;
|
index <= 3'd0;
|
mode <= 1'd0;
|
mode <= 1'd0;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
else if ((gen3_reg2 != gen3_reg1) && (PCIE_PLL_SEL == "QPLL"))
|
else if ((gen3_reg2 != gen3_reg1) && (PCIE_PLL_SEL == "QPLL"))
|
begin
|
begin
|
fsm <= FSM_LOAD;
|
fsm <= FSM_LOAD;
|
index <= 3'd0;
|
index <= 3'd0;
|
mode <= 1'd1;
|
mode <= 1'd1;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
index <= 3'd0;
|
index <= 3'd0;
|
mode <= 1'd0;
|
mode <= 1'd0;
|
done <= 1'd1;
|
done <= 1'd1;
|
end
|
end
|
end
|
end
|
|
|
//---------- Load DRP Address ---------------------
|
//---------- Load DRP Address ---------------------
|
FSM_LOAD :
|
FSM_LOAD :
|
|
|
begin
|
begin
|
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
|
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
|
index <= index;
|
index <= index;
|
mode <= mode;
|
mode <= mode;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
|
|
//---------- Read DRP ------------------------------
|
//---------- Read DRP ------------------------------
|
FSM_READ :
|
FSM_READ :
|
|
|
begin
|
begin
|
fsm <= FSM_RRDY;
|
fsm <= FSM_RRDY;
|
index <= index;
|
index <= index;
|
mode <= mode;
|
mode <= mode;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
|
|
//---------- Read DRP Ready ------------------------
|
//---------- Read DRP Ready ------------------------
|
FSM_RRDY :
|
FSM_RRDY :
|
|
|
begin
|
begin
|
fsm <= (rdy_reg2 ? FSM_WRITE : FSM_RRDY);
|
fsm <= (rdy_reg2 ? FSM_WRITE : FSM_RRDY);
|
index <= index;
|
index <= index;
|
mode <= mode;
|
mode <= mode;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
|
|
//---------- Write DRP -----------------------------
|
//---------- Write DRP -----------------------------
|
FSM_WRITE :
|
FSM_WRITE :
|
|
|
begin
|
begin
|
fsm <= FSM_WRDY;
|
fsm <= FSM_WRDY;
|
index <= index;
|
index <= index;
|
mode <= mode;
|
mode <= mode;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
|
|
//---------- Write DRP Ready -----------------------
|
//---------- Write DRP Ready -----------------------
|
FSM_WRDY :
|
FSM_WRDY :
|
|
|
begin
|
begin
|
fsm <= (rdy_reg2 ? FSM_DONE : FSM_WRDY);
|
fsm <= (rdy_reg2 ? FSM_DONE : FSM_WRDY);
|
index <= index;
|
index <= index;
|
mode <= mode;
|
mode <= mode;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
|
|
//---------- DRP Done ------------------------------
|
//---------- DRP Done ------------------------------
|
FSM_DONE :
|
FSM_DONE :
|
|
|
begin
|
begin
|
if ((index == INDEX_MAX) || (mode && (index == 3'd2)))
|
if ((index == INDEX_MAX) || (mode && (index == 3'd2)))
|
begin
|
begin
|
fsm <= mode ? FSM_QPLLRESET : FSM_IDLE;
|
fsm <= mode ? FSM_QPLLRESET : FSM_IDLE;
|
index <= 3'd0;
|
index <= 3'd0;
|
mode <= mode;
|
mode <= mode;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm <= FSM_LOAD;
|
fsm <= FSM_LOAD;
|
index <= index + 3'd1;
|
index <= index + 3'd1;
|
mode <= mode;
|
mode <= mode;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
end
|
end
|
|
|
//---------- QPLL Reset ----------------------------
|
//---------- QPLL Reset ----------------------------
|
FSM_QPLLRESET :
|
FSM_QPLLRESET :
|
|
|
begin
|
begin
|
fsm <= !qplllock_reg2 ? FSM_QPLLLOCK : FSM_QPLLRESET;
|
fsm <= !qplllock_reg2 ? FSM_QPLLLOCK : FSM_QPLLRESET;
|
index <= 3'd0;
|
index <= 3'd0;
|
mode <= mode;
|
mode <= mode;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
|
|
//---------- QPLL Reset ----------------------------
|
//---------- QPLL Reset ----------------------------
|
FSM_QPLLLOCK :
|
FSM_QPLLLOCK :
|
|
|
begin
|
begin
|
fsm <= qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK;
|
fsm <= qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK;
|
index <= 3'd0;
|
index <= 3'd0;
|
mode <= mode;
|
mode <= mode;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
|
|
//---------- Default State -------------------------
|
//---------- Default State -------------------------
|
default :
|
default :
|
|
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
index <= 3'd0;
|
index <= 3'd0;
|
mode <= 1'd0;
|
mode <= 1'd0;
|
done <= 1'd0;
|
done <= 1'd0;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- QPLL DRP Output ---------------------------------------------------
|
//---------- QPLL DRP Output ---------------------------------------------------
|
assign DRP_ADDR = addr;
|
assign DRP_ADDR = addr;
|
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
|
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
|
assign DRP_DI = di;
|
assign DRP_DI = di;
|
assign DRP_WE = (fsm == FSM_WRITE); // || (fsm == FSM_WRDY);
|
assign DRP_WE = (fsm == FSM_WRITE); // || (fsm == FSM_WRDY);
|
assign DRP_DONE = done;
|
assign DRP_DONE = done;
|
assign DRP_QPLLRESET = (fsm == FSM_QPLLRESET);
|
assign DRP_QPLLRESET = (fsm == FSM_QPLLRESET);
|
assign DRP_CRSCODE = crscode;
|
assign DRP_CRSCODE = crscode;
|
assign DRP_FSM = fsm;
|
assign DRP_FSM = fsm;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|