//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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//
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// This file contains confidential and proprietary information
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_qpll_wrapper.v
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// File : cl_a7pcie_x4_qpll_wrapper.v
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// Version : 1.10
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// Version : 1.11
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : qpll_wrapper.v
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// Filename : qpll_wrapper.v
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// Description : QPLL Wrapper Module for 7 Series Transceiver
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// Description : QPLL Wrapper Module for 7 Series Transceiver
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// Version : 18.1
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// Version : 18.1
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//---------- QPLL Wrapper ----------------------------------------------------
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//---------- QPLL Wrapper ----------------------------------------------------
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module cl_a7pcie_x4_qpll_wrapper #
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module cl_a7pcie_x4_qpll_wrapper #
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(
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(
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parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
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parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_USE_MODE = "3.0", // PCIe use mode
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parameter PCIE_USE_MODE = "3.0", // PCIe use mode
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parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
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parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
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parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency
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parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency
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|
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)
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)
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(
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(
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//---------- QPLL Clock Ports --------------------------
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//---------- QPLL Clock Ports --------------------------
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input QPLL_GTGREFCLK,
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input QPLL_GTGREFCLK,
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input QPLL_QPLLLOCKDETCLK,
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input QPLL_QPLLLOCKDETCLK,
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output QPLL_QPLLOUTCLK,
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output QPLL_QPLLOUTCLK,
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output QPLL_QPLLOUTREFCLK,
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output QPLL_QPLLOUTREFCLK,
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output QPLL_QPLLLOCK,
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output QPLL_QPLLLOCK,
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//---------- QPLL Reset Ports --------------------------
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//---------- QPLL Reset Ports --------------------------
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input QPLL_QPLLPD,
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input QPLL_QPLLPD,
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input QPLL_QPLLRESET,
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input QPLL_QPLLRESET,
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//---------- QPLL DRP Ports ----------------------------
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//---------- QPLL DRP Ports ----------------------------
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input QPLL_DRPCLK,
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input QPLL_DRPCLK,
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input [ 7:0] QPLL_DRPADDR,
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input [ 7:0] QPLL_DRPADDR,
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input QPLL_DRPEN,
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input QPLL_DRPEN,
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input [15:0] QPLL_DRPDI,
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input [15:0] QPLL_DRPDI,
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input QPLL_DRPWE,
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input QPLL_DRPWE,
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output [15:0] QPLL_DRPDO,
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output [15:0] QPLL_DRPDO,
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output QPLL_DRPRDY
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output QPLL_DRPRDY
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);
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);
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//---------- Select QPLL Feedback Divider --------------
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//---------- Select QPLL Feedback Divider --------------
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// N = 100 for 100 MHz ref clk and 10Gb/s line rate
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// N = 100 for 100 MHz ref clk and 10Gb/s line rate
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// N = 80 for 125 MHz ref clk and 10Gb/s line rate
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// N = 80 for 125 MHz ref clk and 10Gb/s line rate
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// N = 40 for 250 MHz ref clk and 10Gb/s line rate
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// N = 40 for 250 MHz ref clk and 10Gb/s line rate
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//------------------------------------------------------
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//------------------------------------------------------
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// N = 80 for 100 MHz ref clk and 8Gb/s line rate
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// N = 80 for 100 MHz ref clk and 8Gb/s line rate
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// N = 64 for 125 MHz ref clk and 8Gb/s line rate
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// N = 64 for 125 MHz ref clk and 8Gb/s line rate
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// N = 32 for 250 MHz ref clk and 8Gb/s line rate
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// N = 32 for 250 MHz ref clk and 8Gb/s line rate
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//------------------------------------------------------
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//------------------------------------------------------
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localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 10'b0010000000 :
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localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 10'b0010000000 :
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 10'b0100100000 :
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 10'b0100100000 :
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(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 10'b0101110000 :
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(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 10'b0101110000 :
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(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 10'b0001100000 :
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(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 10'b0001100000 :
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 10'b0011100000 : 10'b0100100000;
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(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 10'b0011100000 : 10'b0100100000;
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//---------- Select GTP QPLL Feedback Divider ----------
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//---------- Select GTP QPLL Feedback Divider ----------
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localparam GTP_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 3'd2 :
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localparam GTP_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 3'd2 :
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(PCIE_REFCLK_FREQ == 1) ? 3'd4 : 3'd5;
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(PCIE_REFCLK_FREQ == 1) ? 3'd4 : 3'd5;
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//---------- Select BIAS_CFG ---------------------------
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//---------- Select BIAS_CFG ---------------------------
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localparam BIAS_CFG = ((PCIE_USE_MODE == "1.0") && (PCIE_PLL_SEL == "CPLL")) ? 64'h0000042000001000 : 64'h0000040000001000;
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localparam BIAS_CFG = ((PCIE_USE_MODE == "1.0") && (PCIE_PLL_SEL == "CPLL")) ? 64'h0000042000001000 : 64'h0000040000001000;
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//---------- Select GTX or GTH or GTP ------------------------------------------
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//---------- Select GTX or GTH or GTP ------------------------------------------
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// Notes : Attributes that are commented out uses the GT default settings
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// Notes : Attributes that are commented out uses the GT default settings
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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generate if (PCIE_GT_DEVICE == "GTP")
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generate if (PCIE_GT_DEVICE == "GTP")
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//---------- GTP Common ----------------------------------------------------
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//---------- GTP Common ----------------------------------------------------
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begin : gtp_common
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begin : gtp_common
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//---------- GTP Common Module ---------------------------------------------
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//---------- GTP Common Module ---------------------------------------------
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GTPE2_COMMON #
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GTPE2_COMMON #
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(
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(
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//---------- Simulation Attributes -------------------------------------
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//---------- Simulation Attributes -------------------------------------
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.SIM_PLL0REFCLK_SEL (3'b001), //
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.SIM_PLL0REFCLK_SEL (3'b001), //
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.SIM_PLL1REFCLK_SEL (3'b001), //
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.SIM_PLL1REFCLK_SEL (3'b001), //
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.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
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.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
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.SIM_VERSION (PCIE_USE_MODE), //
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.SIM_VERSION (PCIE_USE_MODE), //
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//---------- Clock Attributes ------------------------------------------
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//---------- Clock Attributes ------------------------------------------
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.PLL0_CFG (27'h01F024C), // Optimized for IES
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.PLL0_CFG (27'h01F024C), // Optimized for IES
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.PLL1_CFG (27'h01F024C), // Optimized for IES
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.PLL1_CFG (27'h01F024C), // Optimized for IES
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.PLL_CLKOUT_CFG (8'd0), // Optimized for IES
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.PLL_CLKOUT_CFG (8'd0), // Optimized for IES
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.PLL0_DMON_CFG (1'b0), // Optimized for IES
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.PLL0_DMON_CFG (1'b0), // Optimized for IES
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.PLL1_DMON_CFG (1'b0), // Optimized for IES
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.PLL1_DMON_CFG (1'b0), // Optimized for IES
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.PLL0_FBDIV (GTP_QPLL_FBDIV), // Optimized for IES
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.PLL0_FBDIV (GTP_QPLL_FBDIV), // Optimized for IES
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.PLL1_FBDIV (GTP_QPLL_FBDIV), // Optimized for IES
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.PLL1_FBDIV (GTP_QPLL_FBDIV), // Optimized for IES
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.PLL0_FBDIV_45 (5), // Optimized for IES
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.PLL0_FBDIV_45 (5), // Optimized for IES
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.PLL1_FBDIV_45 (5), // Optimized for IES
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.PLL1_FBDIV_45 (5), // Optimized for IES
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.PLL0_INIT_CFG (24'h00001E), // Optimized for IES
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.PLL0_INIT_CFG (24'h00001E), // Optimized for IES
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.PLL1_INIT_CFG (24'h00001E), // Optimized for IES
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.PLL1_INIT_CFG (24'h00001E), // Optimized for IES
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.PLL0_LOCK_CFG ( 9'h1E8), // Optimized for IES
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.PLL0_LOCK_CFG ( 9'h1E8), // Optimized for IES
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.PLL1_LOCK_CFG ( 9'h1E8), // Optimized for IES
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.PLL1_LOCK_CFG ( 9'h1E8), // Optimized for IES
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.PLL0_REFCLK_DIV (1), // Optimized for IES
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.PLL0_REFCLK_DIV (1), // Optimized for IES
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.PLL1_REFCLK_DIV (1), // Optimized for IES
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.PLL1_REFCLK_DIV (1), // Optimized for IES
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//---------- MISC ------------------------------------------------------
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//---------- MISC ------------------------------------------------------
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.BIAS_CFG (64'h0000000000050001), // Optimized for GES
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.BIAS_CFG (64'h0000000000050001), // Optimized for GES
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//.COMMON_CFG (32'd0), //
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//.COMMON_CFG (32'd0), //
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.RSVD_ATTR0 (16'd0), //
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.RSVD_ATTR0 (16'd0), //
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.RSVD_ATTR1 (16'd0) //
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.RSVD_ATTR1 (16'd0) //
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|
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)
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)
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gtpe2_common_i
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gtpe2_common_i
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(
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(
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//---------- Clock -----------------------------------------------------
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//---------- Clock -----------------------------------------------------
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.GTGREFCLK0 ( 1'd0), //
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.GTGREFCLK0 ( 1'd0), //
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.GTGREFCLK1 ( 1'd0), //
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.GTGREFCLK1 ( 1'd0), //
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.GTREFCLK0 (QPLL_GTGREFCLK), //
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.GTREFCLK0 (QPLL_GTGREFCLK), //
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.GTREFCLK1 ( 1'd0), //
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.GTREFCLK1 ( 1'd0), //
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.GTEASTREFCLK0 ( 1'd0), //
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.GTEASTREFCLK0 ( 1'd0), //
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.GTEASTREFCLK1 ( 1'd0), //
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.GTEASTREFCLK1 ( 1'd0), //
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.GTWESTREFCLK0 ( 1'd0), //
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.GTWESTREFCLK0 ( 1'd0), //
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.GTWESTREFCLK1 ( 1'd0), //
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.GTWESTREFCLK1 ( 1'd0), //
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.PLL0LOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
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.PLL0LOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
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.PLL1LOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
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.PLL1LOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
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.PLL0LOCKEN ( 1'd1), //
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.PLL0LOCKEN ( 1'd1), //
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.PLL1LOCKEN ( 1'd1), //
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.PLL1LOCKEN ( 1'd1), //
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.PLL0REFCLKSEL ( 3'd1), // Optimized for IES
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.PLL0REFCLKSEL ( 3'd1), // Optimized for IES
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.PLL1REFCLKSEL ( 3'd1), // Optimized for IES
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.PLL1REFCLKSEL ( 3'd1), // Optimized for IES
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.PLLRSVD1 (16'd0), // Optimized for IES
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.PLLRSVD1 (16'd0), // Optimized for IES
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.PLLRSVD2 ( 5'd0), // Optimized for IES
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.PLLRSVD2 ( 5'd0), // Optimized for IES
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.PLL0OUTCLK (QPLL_QPLLOUTCLK), //
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.PLL0OUTCLK (QPLL_QPLLOUTCLK), //
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.PLL1OUTCLK (), //
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.PLL1OUTCLK (), //
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.PLL0OUTREFCLK (QPLL_QPLLOUTREFCLK), //
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.PLL0OUTREFCLK (QPLL_QPLLOUTREFCLK), //
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.PLL1OUTREFCLK (), //
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.PLL1OUTREFCLK (), //
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.PLL0LOCK (QPLL_QPLLLOCK), //
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.PLL0LOCK (QPLL_QPLLLOCK), //
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.PLL1LOCK (), //
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.PLL1LOCK (), //
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.PLL0FBCLKLOST (), //
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.PLL0FBCLKLOST (), //
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.PLL1FBCLKLOST (), //
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.PLL1FBCLKLOST (), //
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.PLL0REFCLKLOST (), //
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.PLL0REFCLKLOST (), //
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.PLL1REFCLKLOST (), //
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.PLL1REFCLKLOST (), //
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.DMONITOROUT (), //
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.DMONITOROUT (), //
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//---------- Reset -----------------------------------------------------
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//---------- Reset -----------------------------------------------------
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.PLL0PD (QPLL_QPLLPD), //
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.PLL0PD (QPLL_QPLLPD), //
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.PLL1PD ( 1'd1), //
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.PLL1PD ( 1'd1), //
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.PLL0RESET (QPLL_QPLLRESET), //
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.PLL0RESET (QPLL_QPLLRESET), //
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.PLL1RESET ( 1'd1), //
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.PLL1RESET ( 1'd1), //
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//---------- DRP -------------------------------------------------------
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//---------- DRP -------------------------------------------------------
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.DRPCLK (QPLL_DRPCLK), //
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.DRPCLK (QPLL_DRPCLK), //
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.DRPADDR (QPLL_DRPADDR), //
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.DRPADDR (QPLL_DRPADDR), //
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.DRPEN (QPLL_DRPEN), //
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.DRPEN (QPLL_DRPEN), //
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.DRPDI (QPLL_DRPDI), //
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.DRPDI (QPLL_DRPDI), //
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.DRPWE (QPLL_DRPWE), //
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.DRPWE (QPLL_DRPWE), //
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|
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.DRPDO (QPLL_DRPDO), //
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.DRPDO (QPLL_DRPDO), //
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.DRPRDY (QPLL_DRPRDY), //
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.DRPRDY (QPLL_DRPRDY), //
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//---------- Band Gap --------------------------------------------------
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//---------- Band Gap --------------------------------------------------
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.BGBYPASSB ( 1'd1), // Optimized for IES
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.BGBYPASSB ( 1'd1), // Optimized for IES
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.BGMONITORENB ( 1'd1), // Optimized for IES
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.BGMONITORENB ( 1'd1), // Optimized for IES
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.BGPDB ( 1'd1), // Optimized for IES
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.BGPDB ( 1'd1), // Optimized for IES
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.BGRCALOVRD ( 5'd31), // Optimized for IES
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.BGRCALOVRD ( 5'd31), // Optimized for IES
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.BGRCALOVRDENB ( 1'd1), // Optimized for IES
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.BGRCALOVRDENB ( 1'd1), // Optimized for IES
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|
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//---------- MISC ------------------------------------------------------
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//---------- MISC ------------------------------------------------------
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.PMARSVD ( 8'd0), //
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.PMARSVD ( 8'd0), //
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.RCALENB ( 1'd1), // Optimized for IES
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.RCALENB ( 1'd1), // Optimized for IES
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|
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.REFCLKOUTMONITOR0 (), //
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.REFCLKOUTMONITOR0 (), //
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.REFCLKOUTMONITOR1 (), //
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.REFCLKOUTMONITOR1 (), //
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.PMARSVDOUT () //
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.PMARSVDOUT () //
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|
|
);
|
);
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|
|
end
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end
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|
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else if (PCIE_GT_DEVICE == "GTH")
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else if (PCIE_GT_DEVICE == "GTH")
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|
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//---------- GTH Common ----------------------------------------------------
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//---------- GTH Common ----------------------------------------------------
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begin : gth_common
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begin : gth_common
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|
|
//---------- GTX Common Module ---------------------------------------------
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//---------- GTX Common Module ---------------------------------------------
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GTHE2_COMMON #
|
GTHE2_COMMON #
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(
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(
|
|
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//---------- Simulation Attributes -------------------------------------
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//---------- Simulation Attributes -------------------------------------
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.SIM_QPLLREFCLK_SEL (3'b001), //
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.SIM_QPLLREFCLK_SEL (3'b001), //
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.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
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.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
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.SIM_VERSION ("2.0"), //
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.SIM_VERSION ("2.0"), //
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|
|
//---------- Clock Attributes ------------------------------------------
|
//---------- Clock Attributes ------------------------------------------
|
.QPLL_CFG (27'h04801C7), // QPLL for Gen3, optimized for GES
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.QPLL_CFG (27'h04801C7), // QPLL for Gen3, optimized for GES
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.QPLL_CLKOUT_CFG ( 4'b1111), // Optimized for GES
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.QPLL_CLKOUT_CFG ( 4'b1111), // Optimized for GES
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.QPLL_COARSE_FREQ_OVRD ( 6'b010000), //
|
.QPLL_COARSE_FREQ_OVRD ( 6'b010000), //
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.QPLL_COARSE_FREQ_OVRD_EN ( 1'd0), //
|
.QPLL_COARSE_FREQ_OVRD_EN ( 1'd0), //
|
.QPLL_CP (10'h0FF), // * Optimized for IES and PCIe PLL BW
|
.QPLL_CP (10'h0FF), // * Optimized for IES and PCIe PLL BW
|
.QPLL_CP_MONITOR_EN ( 1'd0), //
|
.QPLL_CP_MONITOR_EN ( 1'd0), //
|
.QPLL_DMONITOR_SEL ( 1'd0), //
|
.QPLL_DMONITOR_SEL ( 1'd0), //
|
.QPLL_FBDIV (QPLL_FBDIV), //
|
.QPLL_FBDIV (QPLL_FBDIV), //
|
.QPLL_FBDIV_MONITOR_EN ( 1'd0), //
|
.QPLL_FBDIV_MONITOR_EN ( 1'd0), //
|
.QPLL_FBDIV_RATIO ( 1'd1), // Optimized
|
.QPLL_FBDIV_RATIO ( 1'd1), // Optimized
|
.QPLL_INIT_CFG (24'h000006), //
|
.QPLL_INIT_CFG (24'h000006), //
|
.QPLL_LOCK_CFG (16'h05E8), // Optimized for IES
|
.QPLL_LOCK_CFG (16'h05E8), // Optimized for IES
|
.QPLL_LPF ( 4'hD), // Optimized for IES, [1:0] = 2'b00 (13.3 KOhm), [1:0] = 2'b01 (57.0 KOhm)
|
.QPLL_LPF ( 4'hD), // Optimized for IES, [1:0] = 2'b00 (13.3 KOhm), [1:0] = 2'b01 (57.0 KOhm)
|
.QPLL_REFCLK_DIV ( 1), //
|
.QPLL_REFCLK_DIV ( 1), //
|
.QPLL_RP_COMP ( 1'd0), // GTH new
|
.QPLL_RP_COMP ( 1'd0), // GTH new
|
.QPLL_VTRL_RESET ( 2'd0), // GTH new
|
.QPLL_VTRL_RESET ( 2'd0), // GTH new
|
|
|
//---------- MISC ------------------------------------------------------
|
//---------- MISC ------------------------------------------------------
|
.BIAS_CFG (64'h0000040000001050), // Optimized for GES
|
.BIAS_CFG (64'h0000040000001050), // Optimized for GES
|
.COMMON_CFG (32'd0), //
|
.COMMON_CFG (32'd0), //
|
.RCAL_CFG ( 2'b00), // GTH new
|
.RCAL_CFG ( 2'b00), // GTH new
|
.RSVD_ATTR0 (16'd0), // GTH
|
.RSVD_ATTR0 (16'd0), // GTH
|
.RSVD_ATTR1 (16'd0) // GTH
|
.RSVD_ATTR1 (16'd0) // GTH
|
)
|
)
|
gthe2_common_i
|
gthe2_common_i
|
(
|
(
|
|
|
//---------- Clock -----------------------------------------------------
|
//---------- Clock -----------------------------------------------------
|
.GTGREFCLK ( 1'd0), //
|
.GTGREFCLK ( 1'd0), //
|
.GTREFCLK0 (QPLL_GTGREFCLK), //
|
.GTREFCLK0 (QPLL_GTGREFCLK), //
|
.GTREFCLK1 ( 1'd0), //
|
.GTREFCLK1 ( 1'd0), //
|
.GTNORTHREFCLK0 ( 1'd0), //
|
.GTNORTHREFCLK0 ( 1'd0), //
|
.GTNORTHREFCLK1 ( 1'd0), //
|
.GTNORTHREFCLK1 ( 1'd0), //
|
.GTSOUTHREFCLK0 ( 1'd0), //
|
.GTSOUTHREFCLK0 ( 1'd0), //
|
.GTSOUTHREFCLK1 ( 1'd0), //
|
.GTSOUTHREFCLK1 ( 1'd0), //
|
.QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
|
.QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
|
.QPLLLOCKEN ( 1'd1), //
|
.QPLLLOCKEN ( 1'd1), //
|
.QPLLREFCLKSEL ( 3'd1), //
|
.QPLLREFCLKSEL ( 3'd1), //
|
.QPLLRSVD1 (16'd0), //
|
.QPLLRSVD1 (16'd0), //
|
.QPLLRSVD2 ( 5'b11111), //
|
.QPLLRSVD2 ( 5'b11111), //
|
|
|
.QPLLOUTCLK (QPLL_QPLLOUTCLK), //
|
.QPLLOUTCLK (QPLL_QPLLOUTCLK), //
|
.QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), //
|
.QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), //
|
.QPLLLOCK (QPLL_QPLLLOCK), //
|
.QPLLLOCK (QPLL_QPLLLOCK), //
|
.QPLLFBCLKLOST (), //
|
.QPLLFBCLKLOST (), //
|
.QPLLREFCLKLOST (), //
|
.QPLLREFCLKLOST (), //
|
.QPLLDMONITOR (), //
|
.QPLLDMONITOR (), //
|
|
|
//---------- Reset -----------------------------------------------------
|
//---------- Reset -----------------------------------------------------
|
.QPLLPD (QPLL_QPLLPD), //
|
.QPLLPD (QPLL_QPLLPD), //
|
.QPLLRESET (QPLL_QPLLRESET), //
|
.QPLLRESET (QPLL_QPLLRESET), //
|
.QPLLOUTRESET ( 1'd0), //
|
.QPLLOUTRESET ( 1'd0), //
|
|
|
//---------- DRP -------------------------------------------------------
|
//---------- DRP -------------------------------------------------------
|
.DRPCLK (QPLL_DRPCLK), //
|
.DRPCLK (QPLL_DRPCLK), //
|
.DRPADDR (QPLL_DRPADDR), //
|
.DRPADDR (QPLL_DRPADDR), //
|
.DRPEN (QPLL_DRPEN), //
|
.DRPEN (QPLL_DRPEN), //
|
.DRPDI (QPLL_DRPDI), //
|
.DRPDI (QPLL_DRPDI), //
|
.DRPWE (QPLL_DRPWE), //
|
.DRPWE (QPLL_DRPWE), //
|
|
|
.DRPDO (QPLL_DRPDO), //
|
.DRPDO (QPLL_DRPDO), //
|
.DRPRDY (QPLL_DRPRDY), //
|
.DRPRDY (QPLL_DRPRDY), //
|
|
|
//---------- Band Gap --------------------------------------------------
|
//---------- Band Gap --------------------------------------------------
|
.BGBYPASSB ( 1'd1), // Optimized for IES
|
.BGBYPASSB ( 1'd1), // Optimized for IES
|
.BGMONITORENB ( 1'd1), // Optimized for IES
|
.BGMONITORENB ( 1'd1), // Optimized for IES
|
.BGPDB ( 1'd1), // Optimized for IES
|
.BGPDB ( 1'd1), // Optimized for IES
|
.BGRCALOVRD ( 5'd31), // Optimized for IES
|
.BGRCALOVRD ( 5'd31), // Optimized for IES
|
.BGRCALOVRDENB ( 1'd1), // GTH, Optimized for IES
|
.BGRCALOVRDENB ( 1'd1), // GTH, Optimized for IES
|
|
|
//---------- MISC ------------------------------------------------------
|
//---------- MISC ------------------------------------------------------
|
.PMARSVD ( 8'd0), //
|
.PMARSVD ( 8'd0), //
|
.RCALENB ( 1'd1), // Optimized for IES
|
.RCALENB ( 1'd1), // Optimized for IES
|
|
|
.REFCLKOUTMONITOR (), //
|
.REFCLKOUTMONITOR (), //
|
.PMARSVDOUT () // GTH
|
.PMARSVDOUT () // GTH
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
else
|
else
|
|
|
//---------- GTX Common ----------------------------------------------------
|
//---------- GTX Common ----------------------------------------------------
|
begin : gtx_common
|
begin : gtx_common
|
|
|
//---------- GTX Common Module ---------------------------------------------
|
//---------- GTX Common Module ---------------------------------------------
|
GTXE2_COMMON #
|
GTXE2_COMMON #
|
(
|
(
|
|
|
//---------- Simulation Attributes -------------------------------------
|
//---------- Simulation Attributes -------------------------------------
|
.SIM_QPLLREFCLK_SEL ( 3'b001), //
|
.SIM_QPLLREFCLK_SEL ( 3'b001), //
|
.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
|
.SIM_RESET_SPEEDUP (PCIE_SIM_MODE), //
|
.SIM_VERSION (PCIE_USE_MODE), //
|
.SIM_VERSION (PCIE_USE_MODE), //
|
|
|
//---------- Clock Attributes ------------------------------------------
|
//---------- Clock Attributes ------------------------------------------
|
.QPLL_CFG (27'h06801C1), // QPLL for Gen3, Optimized for silicon,
|
.QPLL_CFG (27'h06801C1), // QPLL for Gen3, Optimized for silicon,
|
//.QPLL_CLKOUT_CFG ( 4'd0), //
|
//.QPLL_CLKOUT_CFG ( 4'd0), //
|
.QPLL_COARSE_FREQ_OVRD ( 6'b010000), //
|
.QPLL_COARSE_FREQ_OVRD ( 6'b010000), //
|
.QPLL_COARSE_FREQ_OVRD_EN ( 1'd0), //
|
.QPLL_COARSE_FREQ_OVRD_EN ( 1'd0), //
|
.QPLL_CP (10'h01F), // Optimized for Gen3 compliance (Gen1/Gen2 = 10'h1FF)
|
.QPLL_CP (10'h01F), // Optimized for Gen3 compliance (Gen1/Gen2 = 10'h1FF)
|
.QPLL_CP_MONITOR_EN ( 1'd0), //
|
.QPLL_CP_MONITOR_EN ( 1'd0), //
|
.QPLL_DMONITOR_SEL ( 1'd0), //
|
.QPLL_DMONITOR_SEL ( 1'd0), //
|
.QPLL_FBDIV (QPLL_FBDIV), //
|
.QPLL_FBDIV (QPLL_FBDIV), //
|
.QPLL_FBDIV_MONITOR_EN ( 1'd0), //
|
.QPLL_FBDIV_MONITOR_EN ( 1'd0), //
|
.QPLL_FBDIV_RATIO ( 1'd1), // Optimized for silicon
|
.QPLL_FBDIV_RATIO ( 1'd1), // Optimized for silicon
|
//.QPLL_INIT_CFG (24'h000006), //
|
//.QPLL_INIT_CFG (24'h000006), //
|
.QPLL_LOCK_CFG (16'h21E8), // Optimized for silicon, IES = 16'h01D0, GES 16'h21D0
|
.QPLL_LOCK_CFG (16'h21E8), // Optimized for silicon, IES = 16'h01D0, GES 16'h21D0
|
.QPLL_LPF ( 4'hD), // Optimized for silicon, [1:0] = 2'b00 (13.3 KOhm), [1:0] = 2'b01 (57.0 KOhm)
|
.QPLL_LPF ( 4'hD), // Optimized for silicon, [1:0] = 2'b00 (13.3 KOhm), [1:0] = 2'b01 (57.0 KOhm)
|
.QPLL_REFCLK_DIV (1), //
|
.QPLL_REFCLK_DIV (1), //
|
|
|
//---------- MISC ------------------------------------------------------
|
//---------- MISC ------------------------------------------------------
|
.BIAS_CFG (BIAS_CFG) // Optimized for silicon
|
.BIAS_CFG (BIAS_CFG) // Optimized for silicon
|
//.COMMON_CFG (32'd0) //
|
//.COMMON_CFG (32'd0) //
|
|
|
)
|
)
|
gtxe2_common_i
|
gtxe2_common_i
|
(
|
(
|
|
|
//---------- Clock -----------------------------------------------------
|
//---------- Clock -----------------------------------------------------
|
.GTGREFCLK ( 1'd0), //
|
.GTGREFCLK ( 1'd0), //
|
.GTREFCLK0 (QPLL_GTGREFCLK), //
|
.GTREFCLK0 (QPLL_GTGREFCLK), //
|
.GTREFCLK1 ( 1'd0), //
|
.GTREFCLK1 ( 1'd0), //
|
.GTNORTHREFCLK0 ( 1'd0), //
|
.GTNORTHREFCLK0 ( 1'd0), //
|
.GTNORTHREFCLK1 ( 1'd0), //
|
.GTNORTHREFCLK1 ( 1'd0), //
|
.GTSOUTHREFCLK0 ( 1'd0), //
|
.GTSOUTHREFCLK0 ( 1'd0), //
|
.GTSOUTHREFCLK1 ( 1'd0), //
|
.GTSOUTHREFCLK1 ( 1'd0), //
|
.QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
|
.QPLLLOCKDETCLK (QPLL_QPLLLOCKDETCLK), //
|
.QPLLLOCKEN ( 1'd1), //
|
.QPLLLOCKEN ( 1'd1), //
|
.QPLLREFCLKSEL ( 3'd1), //
|
.QPLLREFCLKSEL ( 3'd1), //
|
.QPLLRSVD1 (16'd0), //
|
.QPLLRSVD1 (16'd0), //
|
.QPLLRSVD2 ( 5'b11111), //
|
.QPLLRSVD2 ( 5'b11111), //
|
|
|
.QPLLOUTCLK (QPLL_QPLLOUTCLK), //
|
.QPLLOUTCLK (QPLL_QPLLOUTCLK), //
|
.QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), //
|
.QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), //
|
.QPLLLOCK (QPLL_QPLLLOCK), //
|
.QPLLLOCK (QPLL_QPLLLOCK), //
|
.QPLLFBCLKLOST (), //
|
.QPLLFBCLKLOST (), //
|
.QPLLREFCLKLOST (), //
|
.QPLLREFCLKLOST (), //
|
.QPLLDMONITOR (), //
|
.QPLLDMONITOR (), //
|
|
|
//---------- Reset -----------------------------------------------------
|
//---------- Reset -----------------------------------------------------
|
.QPLLPD (QPLL_QPLLPD), //
|
.QPLLPD (QPLL_QPLLPD), //
|
.QPLLRESET (QPLL_QPLLRESET), //
|
.QPLLRESET (QPLL_QPLLRESET), //
|
.QPLLOUTRESET ( 1'd0), //
|
.QPLLOUTRESET ( 1'd0), //
|
|
|
//---------- DRP -------------------------------------------------------
|
//---------- DRP -------------------------------------------------------
|
.DRPCLK (QPLL_DRPCLK), //
|
.DRPCLK (QPLL_DRPCLK), //
|
.DRPADDR (QPLL_DRPADDR), //
|
.DRPADDR (QPLL_DRPADDR), //
|
.DRPEN (QPLL_DRPEN), //
|
.DRPEN (QPLL_DRPEN), //
|
.DRPDI (QPLL_DRPDI), //
|
.DRPDI (QPLL_DRPDI), //
|
.DRPWE (QPLL_DRPWE), //
|
.DRPWE (QPLL_DRPWE), //
|
|
|
.DRPDO (QPLL_DRPDO), //
|
.DRPDO (QPLL_DRPDO), //
|
.DRPRDY (QPLL_DRPRDY), //
|
.DRPRDY (QPLL_DRPRDY), //
|
|
|
//---------- Band Gap --------------------------------------------------
|
//---------- Band Gap --------------------------------------------------
|
.BGBYPASSB ( 1'd1), //
|
.BGBYPASSB ( 1'd1), //
|
.BGMONITORENB ( 1'd1), //
|
.BGMONITORENB ( 1'd1), //
|
.BGPDB ( 1'd1), //
|
.BGPDB ( 1'd1), //
|
.BGRCALOVRD ( 5'd31), //
|
.BGRCALOVRD ( 5'd31), //
|
|
|
//---------- MISC ------------------------------------------------------
|
//---------- MISC ------------------------------------------------------
|
.PMARSVD ( 8'd0), //
|
.PMARSVD ( 8'd0), //
|
.RCALENB ( 1'd1), // Optimized for GES
|
.RCALENB ( 1'd1), // Optimized for GES
|
|
|
.REFCLKOUTMONITOR () //
|
.REFCLKOUTMONITOR () //
|
|
|
);
|
);
|
|
|
end
|
end
|
|
|
endgenerate
|
endgenerate
|
|
|
endmodule
|
endmodule
|
|
|