//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
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//
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//
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// This file contains confidential and proprietary information
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Project : Series-7 Integrated Block for PCI Express
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// Project : Series-7 Integrated Block for PCI Express
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// File : cl_a7pcie_x4_rxeq_scan.v
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// File : cl_a7pcie_x4_rxeq_scan.v
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// Version : 1.10
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// Version : 1.11
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// Filename : rxeq_scan.v
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// Filename : rxeq_scan.v
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// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
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// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
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// Version : 18.0
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// Version : 18.0
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//---------- RXEQ Eye Scan Module ----------------------------------------------
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//---------- RXEQ Eye Scan Module ----------------------------------------------
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module cl_a7pcie_x4_rxeq_scan #
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module cl_a7pcie_x4_rxeq_scan #
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(
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(
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parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
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parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
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parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
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parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
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parameter CONVERGE_MAX = 22'd3125000, // Convergence max count (12ms)
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parameter CONVERGE_MAX = 22'd3125000, // Convergence max count (12ms)
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parameter CONVERGE_MAX_BYPASS = 22'd2083333 // Convergence max count for phase2/3 bypass mode (8ms)
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parameter CONVERGE_MAX_BYPASS = 22'd2083333 // Convergence max count for phase2/3 bypass mode (8ms)
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)
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)
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(
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(
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//---------- Input -------------------------------------
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//---------- Input -------------------------------------
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input RXEQSCAN_CLK,
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input RXEQSCAN_CLK,
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input RXEQSCAN_RST_N,
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input RXEQSCAN_RST_N,
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input [ 1:0] RXEQSCAN_CONTROL,
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input [ 1:0] RXEQSCAN_CONTROL,
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input [ 2:0] RXEQSCAN_PRESET,
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input [ 2:0] RXEQSCAN_PRESET,
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input RXEQSCAN_PRESET_VALID,
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input RXEQSCAN_PRESET_VALID,
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input [ 3:0] RXEQSCAN_TXPRESET,
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input [ 3:0] RXEQSCAN_TXPRESET,
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input [17:0] RXEQSCAN_TXCOEFF,
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input [17:0] RXEQSCAN_TXCOEFF,
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input RXEQSCAN_NEW_TXCOEFF_REQ,
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input RXEQSCAN_NEW_TXCOEFF_REQ,
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input [ 5:0] RXEQSCAN_FS,
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input [ 5:0] RXEQSCAN_FS,
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input [ 5:0] RXEQSCAN_LF,
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input [ 5:0] RXEQSCAN_LF,
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|
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//---------- Output ------------------------------------
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//---------- Output ------------------------------------
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output RXEQSCAN_PRESET_DONE,
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output RXEQSCAN_PRESET_DONE,
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output [17:0] RXEQSCAN_NEW_TXCOEFF,
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output [17:0] RXEQSCAN_NEW_TXCOEFF,
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output RXEQSCAN_NEW_TXCOEFF_DONE,
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output RXEQSCAN_NEW_TXCOEFF_DONE,
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output RXEQSCAN_LFFS_SEL,
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output RXEQSCAN_LFFS_SEL,
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output RXEQSCAN_ADAPT_DONE
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output RXEQSCAN_ADAPT_DONE
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);
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);
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//---------- Input Register ----------------------------
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//---------- Input Register ----------------------------
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg1;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg2;
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(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg2;
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//---------- Internal Signals --------------------------
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//---------- Internal Signals --------------------------
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reg adapt_done_cnt = 1'd0;
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reg adapt_done_cnt = 1'd0;
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//---------- Output Register ---------------------------
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//---------- Output Register ---------------------------
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reg preset_done = 1'd0;
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reg preset_done = 1'd0;
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reg [21:0] converge_cnt = 22'd0;
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reg [21:0] converge_cnt = 22'd0;
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reg [17:0] new_txcoeff = 18'd0;
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reg [17:0] new_txcoeff = 18'd0;
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reg new_txcoeff_done = 1'd0;
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reg new_txcoeff_done = 1'd0;
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reg lffs_sel = 1'd0;
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reg lffs_sel = 1'd0;
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reg adapt_done = 1'd0;
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reg adapt_done = 1'd0;
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reg [ 3:0] fsm = 4'd0;
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reg [ 3:0] fsm = 4'd0;
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//---------- FSM ---------------------------------------
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//---------- FSM ---------------------------------------
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localparam FSM_IDLE = 4'b0001;
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localparam FSM_IDLE = 4'b0001;
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localparam FSM_PRESET = 4'b0010;
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localparam FSM_PRESET = 4'b0010;
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localparam FSM_CONVERGE = 4'b0100;
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localparam FSM_CONVERGE = 4'b0100;
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localparam FSM_NEW_TXCOEFF_REQ = 4'b1000;
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localparam FSM_NEW_TXCOEFF_REQ = 4'b1000;
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//---------- Simulation Speedup ------------------------
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//---------- Simulation Speedup ------------------------
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// Gen3: 32 bits / PCLK : 1 million bits / X PCLK
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// Gen3: 32 bits / PCLK : 1 million bits / X PCLK
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// X =
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// X =
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//------------------------------------------------------
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//------------------------------------------------------
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localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX;
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localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX;
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localparam converge_max_bypass_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX_BYPASS;
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localparam converge_max_bypass_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX_BYPASS;
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//---------- Input FF ----------------------------------------------------------
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//---------- Input FF ----------------------------------------------------------
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always @ (posedge RXEQSCAN_CLK)
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always @ (posedge RXEQSCAN_CLK)
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begin
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begin
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if (!RXEQSCAN_RST_N)
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if (!RXEQSCAN_RST_N)
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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preset_reg1 <= 3'd0;
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preset_reg1 <= 3'd0;
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preset_valid_reg1 <= 1'd0;
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preset_valid_reg1 <= 1'd0;
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txpreset_reg1 <= 4'd0;
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txpreset_reg1 <= 4'd0;
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txcoeff_reg1 <= 18'd0;
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txcoeff_reg1 <= 18'd0;
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new_txcoeff_req_reg1 <= 1'd0;
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new_txcoeff_req_reg1 <= 1'd0;
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fs_reg1 <= 6'd0;
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fs_reg1 <= 6'd0;
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lf_reg1 <= 6'd0;
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lf_reg1 <= 6'd0;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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preset_reg2 <= 3'd0;
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preset_reg2 <= 3'd0;
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preset_valid_reg2 <= 1'd0;
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preset_valid_reg2 <= 1'd0;
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txpreset_reg2 <= 4'd0;
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txpreset_reg2 <= 4'd0;
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txcoeff_reg2 <= 18'd0;
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txcoeff_reg2 <= 18'd0;
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new_txcoeff_req_reg2 <= 1'd0;
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new_txcoeff_req_reg2 <= 1'd0;
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fs_reg2 <= 6'd0;
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fs_reg2 <= 6'd0;
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lf_reg2 <= 6'd0;
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lf_reg2 <= 6'd0;
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end
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end
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else
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else
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begin
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begin
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//---------- 1st Stage FF --------------------------
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//---------- 1st Stage FF --------------------------
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preset_reg1 <= RXEQSCAN_PRESET;
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preset_reg1 <= RXEQSCAN_PRESET;
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preset_valid_reg1 <= RXEQSCAN_PRESET_VALID;
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preset_valid_reg1 <= RXEQSCAN_PRESET_VALID;
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txpreset_reg1 <= RXEQSCAN_TXPRESET;
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txpreset_reg1 <= RXEQSCAN_TXPRESET;
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txcoeff_reg1 <= RXEQSCAN_TXCOEFF;
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txcoeff_reg1 <= RXEQSCAN_TXCOEFF;
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new_txcoeff_req_reg1 <= RXEQSCAN_NEW_TXCOEFF_REQ;
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new_txcoeff_req_reg1 <= RXEQSCAN_NEW_TXCOEFF_REQ;
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fs_reg1 <= RXEQSCAN_FS;
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fs_reg1 <= RXEQSCAN_FS;
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lf_reg1 <= RXEQSCAN_LF;
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lf_reg1 <= RXEQSCAN_LF;
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//---------- 2nd Stage FF --------------------------
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//---------- 2nd Stage FF --------------------------
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preset_reg2 <= preset_reg1;
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preset_reg2 <= preset_reg1;
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preset_valid_reg2 <= preset_valid_reg1;
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preset_valid_reg2 <= preset_valid_reg1;
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txpreset_reg2 <= txpreset_reg1;
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txpreset_reg2 <= txpreset_reg1;
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txcoeff_reg2 <= txcoeff_reg1;
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txcoeff_reg2 <= txcoeff_reg1;
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new_txcoeff_req_reg2 <= new_txcoeff_req_reg1;
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new_txcoeff_req_reg2 <= new_txcoeff_req_reg1;
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fs_reg2 <= fs_reg1;
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fs_reg2 <= fs_reg1;
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lf_reg2 <= lf_reg1;
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lf_reg2 <= lf_reg1;
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end
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end
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end
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end
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//---------- Eye Scan ----------------------------------------------------------
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//---------- Eye Scan ----------------------------------------------------------
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always @ (posedge RXEQSCAN_CLK)
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always @ (posedge RXEQSCAN_CLK)
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begin
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begin
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if (!RXEQSCAN_RST_N)
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if (!RXEQSCAN_RST_N)
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begin
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begin
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fsm <= FSM_IDLE;
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fsm <= FSM_IDLE;
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preset_done <= 1'd0;
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preset_done <= 1'd0;
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converge_cnt <= 22'd0;
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converge_cnt <= 22'd0;
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new_txcoeff <= 18'd0;
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new_txcoeff <= 18'd0;
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new_txcoeff_done <= 1'd0;
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new_txcoeff_done <= 1'd0;
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lffs_sel <= 1'd0;
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lffs_sel <= 1'd0;
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adapt_done <= 1'd0;
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adapt_done <= 1'd0;
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adapt_done_cnt <= 1'd0;
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adapt_done_cnt <= 1'd0;
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end
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end
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else
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else
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begin
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begin
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case (fsm)
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case (fsm)
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//---------- Idle State ----------------------------
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//---------- Idle State ----------------------------
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FSM_IDLE :
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FSM_IDLE :
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begin
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begin
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//---------- Process RXEQ Preset ---------------
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//---------- Process RXEQ Preset ---------------
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if (preset_valid_reg2)
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if (preset_valid_reg2)
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begin
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begin
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fsm <= FSM_PRESET;
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fsm <= FSM_PRESET;
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preset_done <= 1'd1;
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preset_done <= 1'd1;
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converge_cnt <= 22'd0;
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converge_cnt <= 22'd0;
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new_txcoeff <= new_txcoeff;
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new_txcoeff <= new_txcoeff;
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new_txcoeff_done <= 1'd0;
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new_txcoeff_done <= 1'd0;
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lffs_sel <= 1'd0;
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lffs_sel <= 1'd0;
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adapt_done <= 1'd0;
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adapt_done <= 1'd0;
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adapt_done_cnt <= adapt_done_cnt;
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adapt_done_cnt <= adapt_done_cnt;
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end
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end
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//---------- Request New TX Coefficient --------
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//---------- Request New TX Coefficient --------
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else if (new_txcoeff_req_reg2)
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else if (new_txcoeff_req_reg2)
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begin
|
begin
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fsm <= FSM_CONVERGE;
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fsm <= FSM_CONVERGE;
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preset_done <= 1'd0;
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preset_done <= 1'd0;
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converge_cnt <= 22'd0;
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converge_cnt <= 22'd0;
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//new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : 18'd4; // Default
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//new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : 18'd4; // Default
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new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : (PCIE_GT_DEVICE == "GTX") ? 18'd5 : 18'd4; // Optimized for Gen3 RX JTOL
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new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : (PCIE_GT_DEVICE == "GTX") ? 18'd5 : 18'd4; // Optimized for Gen3 RX JTOL
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new_txcoeff_done <= 1'd0;
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new_txcoeff_done <= 1'd0;
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lffs_sel <= (PCIE_RXEQ_MODE_GEN3 == 0) ? 1'd0 : 1'd1;
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lffs_sel <= (PCIE_RXEQ_MODE_GEN3 == 0) ? 1'd0 : 1'd1;
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adapt_done <= 1'd0;
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adapt_done <= 1'd0;
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adapt_done_cnt <= adapt_done_cnt;
|
adapt_done_cnt <= adapt_done_cnt;
|
end
|
end
|
//---------- Default ---------------------------
|
//---------- Default ---------------------------
|
else
|
else
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
preset_done <= 1'd0;
|
preset_done <= 1'd0;
|
converge_cnt <= 22'd0;
|
converge_cnt <= 22'd0;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff <= new_txcoeff;
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new_txcoeff_done <= 1'd0;
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new_txcoeff_done <= 1'd0;
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lffs_sel <= 1'd0;
|
lffs_sel <= 1'd0;
|
adapt_done <= 1'd0;
|
adapt_done <= 1'd0;
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adapt_done_cnt <= adapt_done_cnt;
|
adapt_done_cnt <= adapt_done_cnt;
|
end
|
end
|
|
|
end
|
end
|
|
|
//---------- Process RXEQ Preset -------------------
|
//---------- Process RXEQ Preset -------------------
|
FSM_PRESET :
|
FSM_PRESET :
|
|
|
begin
|
begin
|
fsm <= (!preset_valid_reg2) ? FSM_IDLE : FSM_PRESET;
|
fsm <= (!preset_valid_reg2) ? FSM_IDLE : FSM_PRESET;
|
preset_done <= 1'd1;
|
preset_done <= 1'd1;
|
converge_cnt <= 22'd0;
|
converge_cnt <= 22'd0;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff_done <= 1'd0;
|
new_txcoeff_done <= 1'd0;
|
lffs_sel <= 1'd0;
|
lffs_sel <= 1'd0;
|
adapt_done <= 1'd0;
|
adapt_done <= 1'd0;
|
adapt_done_cnt <= adapt_done_cnt;
|
adapt_done_cnt <= adapt_done_cnt;
|
end
|
end
|
|
|
//---------- Wait for Convergence ------------------
|
//---------- Wait for Convergence ------------------
|
FSM_CONVERGE :
|
FSM_CONVERGE :
|
|
|
begin
|
begin
|
if ((adapt_done_cnt == 1'd0) && (RXEQSCAN_CONTROL == 2'd2))
|
if ((adapt_done_cnt == 1'd0) && (RXEQSCAN_CONTROL == 2'd2))
|
begin
|
begin
|
fsm <= FSM_NEW_TXCOEFF_REQ;
|
fsm <= FSM_NEW_TXCOEFF_REQ;
|
preset_done <= 1'd0;
|
preset_done <= 1'd0;
|
converge_cnt <= 22'd0;
|
converge_cnt <= 22'd0;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff_done <= 1'd0;
|
new_txcoeff_done <= 1'd0;
|
lffs_sel <= lffs_sel;
|
lffs_sel <= lffs_sel;
|
adapt_done <= 1'd0;
|
adapt_done <= 1'd0;
|
adapt_done_cnt <= adapt_done_cnt;
|
adapt_done_cnt <= adapt_done_cnt;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
//---------- Phase2/3 ----------------------
|
//---------- Phase2/3 ----------------------
|
if (RXEQSCAN_CONTROL == 2'd2)
|
if (RXEQSCAN_CONTROL == 2'd2)
|
fsm <= (converge_cnt == converge_max_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
|
fsm <= (converge_cnt == converge_max_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
|
//---------- Phase2/3 Bypass ---------------
|
//---------- Phase2/3 Bypass ---------------
|
else
|
else
|
fsm <= (converge_cnt == converge_max_bypass_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
|
fsm <= (converge_cnt == converge_max_bypass_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
|
|
|
preset_done <= 1'd0;
|
preset_done <= 1'd0;
|
converge_cnt <= converge_cnt + 1'd1;
|
converge_cnt <= converge_cnt + 1'd1;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff_done <= 1'd0;
|
new_txcoeff_done <= 1'd0;
|
lffs_sel <= lffs_sel;
|
lffs_sel <= lffs_sel;
|
adapt_done <= 1'd0;
|
adapt_done <= 1'd0;
|
adapt_done_cnt <= adapt_done_cnt;
|
adapt_done_cnt <= adapt_done_cnt;
|
end
|
end
|
end
|
end
|
|
|
//---------- Request New TX Coefficient ------------
|
//---------- Request New TX Coefficient ------------
|
FSM_NEW_TXCOEFF_REQ :
|
FSM_NEW_TXCOEFF_REQ :
|
|
|
begin
|
begin
|
if (!new_txcoeff_req_reg2)
|
if (!new_txcoeff_req_reg2)
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
preset_done <= 1'd0;
|
preset_done <= 1'd0;
|
converge_cnt <= 22'd0;
|
converge_cnt <= 22'd0;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff_done <= 1'd0;
|
new_txcoeff_done <= 1'd0;
|
lffs_sel <= lffs_sel;
|
lffs_sel <= lffs_sel;
|
adapt_done <= 1'd0;
|
adapt_done <= 1'd0;
|
adapt_done_cnt <= (RXEQSCAN_CONTROL == 2'd3) ? 1'd0 : adapt_done_cnt + 1'd1;
|
adapt_done_cnt <= (RXEQSCAN_CONTROL == 2'd3) ? 1'd0 : adapt_done_cnt + 1'd1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fsm <= FSM_NEW_TXCOEFF_REQ;
|
fsm <= FSM_NEW_TXCOEFF_REQ;
|
preset_done <= 1'd0;
|
preset_done <= 1'd0;
|
converge_cnt <= 22'd0;
|
converge_cnt <= 22'd0;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff <= new_txcoeff;
|
new_txcoeff_done <= 1'd1;
|
new_txcoeff_done <= 1'd1;
|
lffs_sel <= lffs_sel;
|
lffs_sel <= lffs_sel;
|
adapt_done <= (adapt_done_cnt == 1'd1) || (RXEQSCAN_CONTROL == 2'd3);
|
adapt_done <= (adapt_done_cnt == 1'd1) || (RXEQSCAN_CONTROL == 2'd3);
|
adapt_done_cnt <= adapt_done_cnt;
|
adapt_done_cnt <= adapt_done_cnt;
|
end
|
end
|
end
|
end
|
|
|
//---------- Default State -------------------------
|
//---------- Default State -------------------------
|
default :
|
default :
|
|
|
begin
|
begin
|
fsm <= FSM_IDLE;
|
fsm <= FSM_IDLE;
|
preset_done <= 1'd0;
|
preset_done <= 1'd0;
|
converge_cnt <= 22'd0;
|
converge_cnt <= 22'd0;
|
new_txcoeff <= 18'd0;
|
new_txcoeff <= 18'd0;
|
new_txcoeff_done <= 1'd0;
|
new_txcoeff_done <= 1'd0;
|
lffs_sel <= 1'd0;
|
lffs_sel <= 1'd0;
|
adapt_done <= 1'd0;
|
adapt_done <= 1'd0;
|
adapt_done_cnt <= 1'd0;
|
adapt_done_cnt <= 1'd0;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
|
|
//---------- RXEQ Eye Scan Output ----------------------------------------------
|
//---------- RXEQ Eye Scan Output ----------------------------------------------
|
assign RXEQSCAN_PRESET_DONE = preset_done;
|
assign RXEQSCAN_PRESET_DONE = preset_done;
|
assign RXEQSCAN_NEW_TXCOEFF = new_txcoeff;
|
assign RXEQSCAN_NEW_TXCOEFF = new_txcoeff;
|
assign RXEQSCAN_NEW_TXCOEFF_DONE = new_txcoeff_done;
|
assign RXEQSCAN_NEW_TXCOEFF_DONE = new_txcoeff_done;
|
assign RXEQSCAN_LFFS_SEL = lffs_sel;
|
assign RXEQSCAN_LFFS_SEL = lffs_sel;
|
assign RXEQSCAN_ADAPT_DONE = adapt_done;
|
assign RXEQSCAN_ADAPT_DONE = adapt_done;
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|