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[/] [pcie_ds_dma/] [trunk/] [projects/] [ac701_a200t_core/] [src/] [testbench/] [stend_ac701_core.vhd] - Diff between revs 49 and 50

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Rev 49 Rev 50 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
--
 
--
 
-- Title       : stend_ambpex5_core
 
-- Title       : stend_ambpex5_core
 
-- Author      : Dmitry Smekhov
 
-- Author      : Dmitry Smekhov
 
-- Company     : Instrumental Systems
 
-- Company     : Instrumental Systems
 
-- E-mail      : dsmv@insys.ru
 
-- E-mail      : dsmv@insys.ru
 
--
 
--
 
-- Version     : 1.0
 
-- Version     : 1.0
 
--
 
--
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
--
 
--
 
-- Description : 
-- Description : 
--
 
--
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
 
 
 
 
 
 
 
 
library ieee;
 
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_1164.all;
 
use ieee.std_logic_textio.all;
 
use ieee.std_logic_textio.all;
 
 
 
 
 
library work;
 
library work;
 
 
 
 
 
use work.cmd_sim_pkg.all;
 
use work.cmd_sim_pkg.all;
 
use work.block_pkg.all;
 
use work.block_pkg.all;
 
use work.ac701_a200t_core_pkg.all;
 
use work.ac701_a200t_core_pkg.all;
 
use work.xilinx_pcie_rport_m2_pkg.all;
 
use work.xilinx_pcie_rport_m2_pkg.all;
 
 
 
 
 
use work.test_pkg.all;
 
use work.test_pkg.all;
 
 
 
 
 
use std.textio.all;
 
use std.textio.all;
 
use std.textio;
 
use std.textio;
 
 
 
 
 
entity stend_ac701_core is
 
entity stend_ac701_core is
 
 
 
        generic(
 
 
 
                test_id                 : in integer:=3;                                                        -- идентификатор теста
 
 
 
                test_log                : in string:="src\testbench\log\file_id_"       -- имя файла отчёта
 
 
 
        );
 
end stend_ac701_core;
 
end stend_ac701_core;
 
 
 
 
 
 
 
 
 
architecture stend_ac701_core of stend_ac701_core is
 
architecture stend_ac701_core of stend_ac701_core is
 
 
 
 
 
 
 
constant        fname_test_log  : string:= test_log & integer'image(test_id) & ".log";
 
 
 
 
 
 
 
 
 
signal  clk250                  : std_logic:='0';
 
signal  clk250                  : std_logic:='0';
 
signal  clk250p                 : std_logic;
 
signal  clk250p                 : std_logic;
 
signal  clk250n                 : std_logic;
 
signal  clk250n                 : std_logic;
 
 
 
 
 
signal  clk100                  : std_logic:='0';
 
signal  clk100                  : std_logic:='0';
 
signal  clk100p                 : std_logic;
 
signal  clk100p                 : std_logic;
 
signal  clk100n                 : std_logic;
 
signal  clk100n                 : std_logic;
 
 
 
 
 
signal  reset                   : std_logic;
 
signal  reset                   : std_logic;
 
 
 
 
 
signal  txp                             : std_logic_vector( 3 downto 0 ):=(others=>'0');
 
signal  txp                             : std_logic_vector( 3 downto 0 ):=(others=>'0');
 
signal  txn                             : std_logic_vector( 3 downto 0 ):=(others=>'1');
 
signal  txn                             : std_logic_vector( 3 downto 0 ):=(others=>'1');
 
signal  rxp                             : std_logic_vector( 3 downto 0 ):=(others=>'0');
 
signal  rxp                             : std_logic_vector( 3 downto 0 ):=(others=>'0');
 
signal  rxn                             : std_logic_vector( 3 downto 0 ):=(others=>'1');
 
signal  rxn                             : std_logic_vector( 3 downto 0 ):=(others=>'1');
 
 
 
 
 
signal  rp_txp                  : std_logic_vector( 0 downto 0 ):=(others=>'0');
 
signal  rp_txp                  : std_logic_vector( 0 downto 0 ):=(others=>'0');
 
signal  rp_txn                  : std_logic_vector( 0 downto 0 ):=(others=>'1');
 
signal  rp_txn                  : std_logic_vector( 0 downto 0 ):=(others=>'1');
 
signal  rp_rxp                  : std_logic_vector( 0 downto 0 ):=(others=>'0');
 
signal  rp_rxp                  : std_logic_vector( 0 downto 0 ):=(others=>'0');
 
signal  rp_rxn                  : std_logic_vector( 0 downto 0 ):=(others=>'1');
 
signal  rp_rxn                  : std_logic_vector( 0 downto 0 ):=(others=>'1');
 
 
 
 
 
signal  tp                              : std_logic_vector( 3 downto 1 );
 
signal  tp                              : std_logic_vector( 3 downto 1 );
 
signal  led1                    : std_logic;
 
signal  led1                    : std_logic;
 
signal  led2                    : std_logic;
 
signal  led2                    : std_logic;
 
signal  led3                    : std_logic;
 
signal  led3                    : std_logic;
 
signal  led4                    : std_logic;
 
signal  led4                    : std_logic;
 
 
 
 
 
signal  cmd                             : bh_cmd;       -- команда
 
signal  cmd                             : bh_cmd;       -- команда
 
signal  ret                             : bh_ret;       -- ответ
 
signal  ret                             : bh_ret;       -- ответ
 
 
 
 
 
 
 
 
 
begin
 
begin
 
 
 
 
 
 amb: ac701_a200t_core
 
 amb: ac701_a200t_core
 
        generic map(
 
        generic map(
 
                is_simulation   => 2    -- 0 - синтез, 1 - моделирование ADM, 2 - моделирование pcie_core  
                is_simulation   => 2    -- 0 - синтез, 1 - моделирование ADM, 2 - моделирование pcie_core  
        )
 
        )
 
        port map(
 
        port map(
 
                ---- PCI-Express ----
 
                ---- PCI-Express ----
 
                pci_exp_txp                     => txp,
 
                pci_exp_txp                     => txp,
 
                pci_exp_txn                     => txn,
 
                pci_exp_txn                     => txn,
 
 
 
 
 
                pci_exp_rxp                     => rxp,
 
                pci_exp_rxp                     => rxp,
 
                pci_exp_rxn                     => rxn,
 
                pci_exp_rxn                     => rxn,
 
 
 
 
 
                sys_clk_p                       => clk100p,   -- тактовая частота 250 MHz от PCI_Express
 
                sys_clk_p                       => clk100p,   -- тактовая частота 250 MHz от PCI_Express
 
                sys_clk_n                       => clk100n,
 
                sys_clk_n                       => clk100n,
 
 
 
 
 
                sys_reset_n                     => reset,       -- 0 - сброс                                               
                sys_reset_n                     => reset,       -- 0 - сброс                                               
 
 
 
 
 
 
 
 
                ---- Светодиоды ----
 
                ---- Светодиоды ----
 
                gpio_led1                       => led1,
 
                gpio_led1                       => led1,
 
                gpio_led2                       => led2,
 
                gpio_led2                       => led2,
 
                gpio_led3                       => led3,
 
                gpio_led3                       => led3,
 
                gpio_led4                       => led4
 
                gpio_led4                       => led4
 
        );
 
        );
 
 
 
 
 
 
 
 
 
rp : xilinx_pcie_rport_m2
 
rp : xilinx_pcie_rport_m2
 
generic map (
 
generic map (
 
      REF_CLK_FREQ => 0,
 
      REF_CLK_FREQ => 0,
 
      ALLOW_X8_GEN2 => FALSE,
 
      ALLOW_X8_GEN2 => FALSE,
 
      PL_FAST_TRAIN => TRUE,
 
      PL_FAST_TRAIN => TRUE,
 
      LINK_CAP_MAX_LINK_SPEED => X"1",
 
      LINK_CAP_MAX_LINK_SPEED => X"1",
 
      DEVICE_ID => X"6011",
 
      DEVICE_ID => X"6011",
 
      LINK_CAP_MAX_LINK_WIDTH => X"01",
 
      LINK_CAP_MAX_LINK_WIDTH => X"01",
 
      LINK_CAP_MAX_LINK_WIDTH_int => 1,
 
      LINK_CAP_MAX_LINK_WIDTH_int => 1,
 
      LINK_CTRL2_TARGET_LINK_SPEED => X"1",
 
      LINK_CTRL2_TARGET_LINK_SPEED => X"1",
 
      LTSSM_MAX_LINK_WIDTH => X"01",
 
      LTSSM_MAX_LINK_WIDTH => X"01",
 
      DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
 
      DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
 
      VC0_TX_LASTPACKET => 29,
 
      VC0_TX_LASTPACKET => 29,
 
      VC0_RX_RAM_LIMIT => X"7FF",
 
      VC0_RX_RAM_LIMIT => X"7FF",
 
      VC0_TOTAL_CREDITS_PD => (308),
 
      VC0_TOTAL_CREDITS_PD => (308),
 
      VC0_TOTAL_CREDITS_CD => (308),
 
      VC0_TOTAL_CREDITS_CD => (308),
 
      USER_CLK_FREQ => 1
 
      USER_CLK_FREQ => 1
 
)
 
)
 
port map (
 
port map (
 
 
 
 
 
                sys_clk => clk100,
 
                sys_clk => clk100,
 
                sys_reset_n => reset,
 
                sys_reset_n => reset,
 
 
 
 
 
                pci_exp_txn => rp_txn,
 
                pci_exp_txn => rp_txn,
 
                pci_exp_txp => rp_txp,
 
                pci_exp_txp => rp_txp,
 
                pci_exp_rxn => rp_rxn,
 
                pci_exp_rxn => rp_rxn,
 
                pci_exp_rxp => rp_rxp,
 
                pci_exp_rxp => rp_rxp,
 
 
 
 
 
                cmd                     => cmd, -- команда
 
                cmd                     => cmd, -- команда
 
                ret                     => ret  -- ответ
 
                ret                     => ret  -- ответ
 
 
 
 
 
);
 
);
 
 
 
 
 
 
 
 
 
clk100 <= not clk100 after 5 ns;
 
clk100 <= not clk100 after 5 ns;
 
--clk250 <= not clk250 after 2 ns;
 
--clk250 <= not clk250 after 2 ns;
 
--
 
--
 
--clk250p <= clk250;
 
--clk250p <= clk250;
 
--clk250n <= not clk250;
 
--clk250n <= not clk250;
 
 
 
 
 
clk100p <= clk100;
 
clk100p <= clk100;
 
clk100n <= not clk100;
 
clk100n <= not clk100;
 
 
 
 
 
rxp(0) <= rp_txp(0);
 
rxp(0) <= rp_txp(0);
 
rxn(0) <= rp_txn(0);
 
rxn(0) <= rp_txn(0);
 
 
 
 
 
rp_rxp(0) <= txp(0);
 
rp_rxp(0) <= txp(0);
 
rp_rxn(0) <= txn(0);
 
rp_rxn(0) <= txn(0);
 
 
 
 
 
reset <= '0', '1' after 5002 ns;
 
reset <= '0', '1' after 5002 ns;
 
 
 
 
 
pr_main: process
 
pr_main: process
 
 
 
 
 
variable        data    : std_logic_vector( 31 downto 0 );
 
variable        data    : std_logic_vector( 31 downto 0 );
 
variable        str     : LINE;         -- pointer to string
 
variable        str     : LINE;         -- pointer to string
 
begin
 
begin
 
 
 
 
 
        test_init( "src\testbench\log\test.log" );
 
 
 
--      test_init( "test.log" );
 
        test_init( fname_test_log );
 
 
 
 
 
        wait for 250 us;
 
        wait for 250 us;
 
 
 
 
 
 
 
 
 
        --test_dsc_incorrect( cmd, ret );          
        --test_dsc_incorrect( cmd, ret );          
 
 
 
 
        --test_read_4kb( cmd, ret );
 
        --test_read_4kb( cmd, ret );
 
        --test_adm_read_8kb( cmd, ret );
 
        --test_adm_read_8kb( cmd, ret );
 
        --test_adm_read_16kb( cmd, ret );
 
        --test_adm_read_16kb( cmd, ret );
 
        --test_adm_write_16kb( cmd, ret );
 
        --test_adm_write_16kb( cmd, ret );
 
        test_block_main( cmd, ret );
 
        --test_block_main( cmd, ret );
 
 
 
 
 
 
 
        case( test_id ) is
 
 
 
                when 0 => test_dsc_incorrect( cmd, ret );
 
 
 
        when 1 => test_read_4kb( cmd, ret );      -- was original
 
 
 
        when 2 => test_adm_read_8kb( cmd, ret );
 
 
 
        when 3 => test_adm_read_16kb( cmd, ret );
 
 
 
        when 4 => test_adm_write_16kb( cmd, ret );
 
 
 
        when 5 => test_block_main( cmd, ret );
 
 
 
 
 
 
 
                when others => null;
 
 
 
 
 
 
 
        end case;
 
 
 
 
 
        test_close;
 
        test_close;
 
    --
 
    --
 
    -- Print Final Banner
 
    -- Print Final Banner
 
    report "Init END OF TEST" severity WARNING;
 
    report "Init END OF TEST" severity WARNING;
 
    assert false
 
    assert false
 
    report "End of TEST; Ending simulation (not a Failure)"
 
    report "End of TEST; Ending simulation (not a Failure)"
 
    severity FAILURE;
 
    severity FAILURE;
 
        wait;
 
        wait;
 
 
 
 
 
end process;
 
end process;
 
 
 
 
 
end stend_ac701_core;
 
end stend_ac701_core;
 
 
 
 

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