---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Title : test_pkg.vhd
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-- Title : test_pkg.vhd
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-- Author : Dmitry Smekhov
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-- Author : Dmitry Smekhov
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-- Company : Instrumental System
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-- Company : Instrumental System
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--
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--
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-- Version : 1.0
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-- Version : 1.0
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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--
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--
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-- Description : Пакет для тестирования ambpex5.
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-- Description : Пакет для тестирования ambpex5.
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--
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--
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---------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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library work;
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library work;
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use work.cmd_sim_pkg.all;
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use work.cmd_sim_pkg.all;
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use work.block_pkg.all;
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use work.block_pkg.all;
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use work.trd_pkg.all;
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use work.trd_pkg.all;
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package test_pkg is
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package test_pkg is
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--! Инициализация теста
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--! Инициализация теста
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procedure test_init(
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procedure test_init(
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fname: in string --! имя файла отчёта
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fname: in string --! имя файла отчёта
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);
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);
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--! Завершение теста
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--! Завершение теста
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procedure test_close;
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procedure test_close;
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--! Запуск DMA с неправильным дескриптором
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--! Запуск DMA с неправильным дескриптором
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procedure test_dsc_incorrect (
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procedure test_dsc_incorrect (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! команда
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! ответ
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);
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);
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--! Запуск DMA на приём одного блока 4 кБ
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--! Запуск DMA на приём одного блока 4 кБ
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procedure test_read_4kb (
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procedure test_read_4kb (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! команда
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! ответ
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);
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);
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--! Чтение 8 кБ из тетрады DIO_IN
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--! Чтение 8 кБ из тетрады DIO_IN
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procedure test_adm_read_8kb (
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procedure test_adm_read_8kb (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! команда
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! ответ
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);
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);
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--! Проверка обращений к блоку MAIN
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--! Проверка обращений к блоку MAIN
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procedure test_block_main (
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procedure test_block_main (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! команда
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! ответ
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);
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);
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--! Чтение 16 кБ с использованием двух блоков дескрипторов
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--! Чтение 16 кБ с использованием двух блоков дескрипторов
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procedure test_adm_read_16kb (
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procedure test_adm_read_16kb (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! команда
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! ответ
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);
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);
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--! Запись 16 кБ с использованием двух блоков дескрипторов
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--! Запись 16 кБ с использованием двух блоков дескрипторов
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procedure test_adm_write_16kb (
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procedure test_adm_write_16kb (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! команда
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! ответ
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);
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);
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end package test_pkg;
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end package test_pkg;
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package body test_pkg is
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package body test_pkg is
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FILE log: text;
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FILE log: text;
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shared variable cnt_ok, cnt_error: integer;
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shared variable cnt_ok, cnt_error: integer;
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-- Инициализация теста
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-- Инициализация теста
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procedure test_init(
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procedure test_init(
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fname: in string -- имя файла отчёта
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fname: in string -- имя файла отчёта
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) is
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) is
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begin
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begin
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file_open( log, fname, WRITE_MODE );
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file_open( log, fname, WRITE_MODE );
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cnt_ok:=0;
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cnt_ok:=0;
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cnt_error:=0;
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cnt_error:=0;
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end test_init;
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end test_init;
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-- Завершение теста
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-- Завершение теста
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procedure test_close is
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procedure test_close is
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variable str : LINE; -- pointer to string
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variable str : LINE; -- pointer to string
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begin
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begin
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std.textio.write( str, string'(" " ));
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std.textio.write( str, string'(" " ));
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writeline( log, str );
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writeline( log, str );
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writeline( log, str );
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writeline( log, str );
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write( str, string'("Проверка завершена" ));
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write( str, string'("Проверка завершена" ));
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writeline( log, str );
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writeline( log, str );
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write( str, string'("Число успешных тестов: " ));
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write( str, string'("Число успешных тестов: " ));
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write( str, cnt_ok );
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write( str, cnt_ok );
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writeline( log, str );
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writeline( log, str );
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write( str, string'("Число ошибочных тестов: " ));
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write( str, string'("Число ошибочных тестов: " ));
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write( str, cnt_error );
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write( str, cnt_error );
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writeline( log, str );
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writeline( log, str );
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file_close( log );
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file_close( log );
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end test_close;
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end test_close;
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--! Запуск DMA с неправильным дескриптором
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--! Запуск DMA с неправильным дескриптором
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procedure test_dsc_incorrect (
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procedure test_dsc_incorrect (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! команда
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! ответ
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)
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)
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is
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable adr : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable str : line;
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variable str : line;
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variable error : integer:=0;
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begin
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begin
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write( str, string'("TEST_DSC_INCORRECT" ));
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write( str, string'("TEST_DSC_INCORRECT" ));
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writeline( log, str );
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writeline( log, str );
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---- Формирование блока дескрипторов ---
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---- Формирование блока дескрипторов ---
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for ii in 0 to 127 loop
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for ii in 0 to 127 loop
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adr:= x"00100000";
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adr:= x"00100000";
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adr:=adr + ii*4;
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adr:=adr + ii*4;
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int_mem_write( cmd, ret, adr, x"00000000" );
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int_mem_write( cmd, ret, adr, x"00000000" );
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end loop;
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end loop;
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int_mem_write( cmd, ret, x"00100000", x"03020100" );
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int_mem_write( cmd, ret, x"00100000", x"03020100" );
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int_mem_write( cmd, ret, x"001001FC", x"FF00AA00" );
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int_mem_write( cmd, ret, x"001001FC", x"FF00AA00" );
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---- Программирование канала DMA ----
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---- Программирование канала DMA ----
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block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
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block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
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block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
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block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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wait for 10 us;
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wait for 10 us;
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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if( data( 15 downto 0 )=x"A021" ) then
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if( data( 15 downto 0 )=x"A021" ) then
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write( str, string'(" - Ok" ));
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write( str, string'(" - Ok" ));
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cnt_ok := cnt_ok + 1;
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else
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else
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write( str, string'(" - Error" ));
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write( str, string'(" - Error" ));
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cnt_error := cnt_error + 1;
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error:=error+1;
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end if;
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end if;
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writeline( log, str );
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writeline( log, str );
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block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
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block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
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-- вывод в файл --
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writeline( log, str );
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if( error=0 ) then
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write( str, string'("TEST finished successfully" ));
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cnt_ok := cnt_ok + 1;
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else
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write( str, string'("TEST finished with ERR" ));
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cnt_error := cnt_error + 1;
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end if;
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writeline( log, str );
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writeline( log, str );
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-- вывод в консоль --
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writeline( output, str );
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if( error=0 ) then
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write( str, string'("TEST finished successfully" ));
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cnt_ok := cnt_ok + 1;
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else
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write( str, string'("TEST finished with ERR" ));
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cnt_error := cnt_error + 1;
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end if;
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writeline( output, str );
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writeline( output, str );
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end test_dsc_incorrect;
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end test_dsc_incorrect;
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--! Запуск DMA приём одного блока 4 кБ
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--! Запуск DMA приём одного блока 4 кБ
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procedure test_read_4kb (
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procedure test_read_4kb (
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signal cmd: out bh_cmd; --! команда
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signal cmd: out bh_cmd; --! команда
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signal ret: in bh_ret --! ответ
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signal ret: in bh_ret --! ответ
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)
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)
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is
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is
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variable adr : std_logic_vector( 31 downto 0 );
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variable adr : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable data : std_logic_vector( 31 downto 0 );
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variable str : line;
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variable str : line;
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variable error : integer:=0;
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variable error : integer:=0;
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variable dma_complete : integer;
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variable dma_complete : integer;
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begin
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begin
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write( str, string'("TEST_READ_4KB" ));
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write( str, string'("TEST_READ_4KB" ));
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writeline( log, str );
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writeline( log, str );
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---- Формирование блока дескрипторов ---
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---- Формирование блока дескрипторов ---
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for ii in 0 to 127 loop
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for ii in 0 to 127 loop
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adr:= x"00100000";
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adr:= x"00100000";
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adr:=adr + ii*4;
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adr:=adr + ii*4;
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int_mem_write( cmd, ret, adr, x"00000000" );
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int_mem_write( cmd, ret, adr, x"00000000" );
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end loop;
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end loop;
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int_mem_write( cmd, ret, x"00100000", x"00008000" );
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int_mem_write( cmd, ret, x"00100000", x"00008000" );
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int_mem_write( cmd, ret, x"00100004", x"00000100" );
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int_mem_write( cmd, ret, x"00100004", x"00000100" );
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int_mem_write( cmd, ret, x"001001F8", x"00000000" );
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int_mem_write( cmd, ret, x"001001F8", x"00000000" );
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int_mem_write( cmd, ret, x"001001FC", x"762C4953" );
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int_mem_write( cmd, ret, x"001001FC", x"762C4953" );
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---- Программирование канала DMA ----
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---- Программирование канала DMA ----
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block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE
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block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
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block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
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block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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wait for 20 us;
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wait for 20 us;
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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if( data( 8 )='1' ) then
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if( data( 8 )='1' ) then
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write( str, string'(" - Дескриптор правильный" ));
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write( str, string'(" - Дескриптор правильный" ));
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else
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else
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write( str, string'(" - Ошибка чтения дескриптора" ));
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write( str, string'(" - Ошибка чтения дескриптора" ));
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error := error + 1;
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error := error + 1;
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end if;
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end if;
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writeline( log, str );
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writeline( log, str );
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if( error=0 ) then
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if( error=0 ) then
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---- Ожидание завершения DMA ----
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---- Ожидание завершения DMA ----
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dma_complete := 0;
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dma_complete := 0;
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for ii in 0 to 100 loop
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for ii in 0 to 100 loop
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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if( data(5)='1' ) then
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if( data(5)='1' ) then
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write( str, string'(" - DMA завершён " ));
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write( str, string'(" - DMA завершён " ));
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dma_complete := 1;
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dma_complete := 1;
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end if;
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end if;
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writeline( log, str );
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writeline( log, str );
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if( dma_complete=1 ) then
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if( dma_complete=1 ) then
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exit;
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exit;
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end if;
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end if;
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wait for 1 us;
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wait for 1 us;
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end loop;
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end loop;
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writeline( log, str );
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writeline( log, str );
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if( dma_complete=0 ) then
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if( dma_complete=0 ) then
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write( str, string'("Ошибка - DMA не завершён " ));
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write( str, string'("Ошибка - DMA не завершён " ));
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writeline( log, str );
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writeline( log, str );
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error:=error+1;
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error:=error+1;
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end if;
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end if;
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end if;
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end if;
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for ii in 0 to 3 loop
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for ii in 0 to 3 loop
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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block_read( cmd, ret, 4, 16, data ); -- STATUS
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
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writeline( log, str );
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writeline( log, str );
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wait for 500 ns;
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wait for 500 ns;
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end loop;
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end loop;
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|
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block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
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block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
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write( str, string'(" Прочитано: " ));
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write( str, string'(" Прочитано: " ));
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writeline( log, str );
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writeline( log, str );
|
|
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for ii in 0 to 15 loop
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for ii in 0 to 15 loop
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|
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adr:= x"00800000";
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adr:= x"00800000";
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adr:=adr + ii*4;
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adr:=adr + ii*4;
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int_mem_read( cmd, ret, adr, data );
|
int_mem_read( cmd, ret, adr, data );
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|
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write( str, ii ); write( str, string'(" " )); hwrite( str, data );
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write( str, ii ); write( str, string'(" " )); hwrite( str, data );
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writeline( log, str );
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writeline( log, str );
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|
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end loop;
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end loop;
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|
|
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
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-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
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-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
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|
|
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|
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-- вывод в файл --
|
writeline( log, str );
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writeline( log, str );
|
if( error=0 ) then
|
if( error=0 ) then
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write( str, string'(" Тест завершён успешно " ));
|
write( str, string'("TEST finished successfully" ));
|
cnt_ok := cnt_ok + 1;
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cnt_ok := cnt_ok + 1;
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else
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else
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write( str, string'(" Тест не выполнен " ));
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write( str, string'("TEST finished with ERR" ));
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cnt_error := cnt_error + 1;
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cnt_error := cnt_error + 1;
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end if;
|
end if;
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writeline( log, str );
|
writeline( log, str );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
|
-- вывод в консоль --
|
|
writeline( output, str );
|
|
if( error=0 ) then
|
|
write( str, string'("TEST finished successfully" ));
|
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cnt_ok := cnt_ok + 1;
|
|
else
|
|
write( str, string'("TEST finished with ERR" ));
|
|
cnt_error := cnt_error + 1;
|
|
end if;
|
|
writeline( output, str );
|
|
writeline( output, str );
|
|
|
|
|
|
|
end test_read_4kb;
|
end test_read_4kb;
|
|
|
|
|
--! Чтение 8 кБ из тетрады DIO_IN
|
--! Чтение 8 кБ из тетрады DIO_IN
|
procedure test_adm_read_8kb (
|
procedure test_adm_read_8kb (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! команда
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! ответ
|
)
|
)
|
is
|
is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable str : line;
|
variable str : line;
|
|
|
variable error : integer:=0;
|
variable error : integer:=0;
|
variable dma_complete : integer;
|
variable dma_complete : integer;
|
|
|
begin
|
begin
|
|
|
write( str, string'("TEST_ADM_READ_8KB" ));
|
write( str, string'("TEST_ADM_READ_8KB" ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
---- Формирование блока дескрипторов ---
|
---- Формирование блока дескрипторов ---
|
for ii in 0 to 127 loop
|
for ii in 0 to 127 loop
|
adr:= x"00100000";
|
adr:= x"00100000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
end loop;
|
end loop;
|
|
|
--- Дескриптор 0 ---
|
--- Дескриптор 0 ---
|
int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
int_mem_write( cmd, ret, x"00100004", x"00000111" ); -- переход к следующему
|
int_mem_write( cmd, ret, x"00100004", x"00000111" ); -- переход к следующему
|
|
|
--- Дескриптор 1 ---
|
--- Дескриптор 1 ---
|
int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
int_mem_write( cmd, ret, x"0010000C", x"00000110" ); -- остановка
|
int_mem_write( cmd, ret, x"0010000C", x"00000110" ); -- остановка
|
|
|
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
int_mem_write( cmd, ret, x"001001FC", x"D6644953" );
|
int_mem_write( cmd, ret, x"001001FC", x"D6644953" );
|
|
|
trd_test_mode( cmd, ret, 0 ); -- переход в рабочий режим --
|
trd_test_mode( cmd, ret, 0 ); -- переход в рабочий режим --
|
|
|
---- Программирование канала DMA ----
|
---- Программирование канала DMA ----
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
|
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
|
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
block_write( cmd, ret, 4, 23, x"00019000" ); -- LOCAL_ADR
|
block_write( cmd, ret, 4, 23, x"00019000" ); -- LOCAL_ADR
|
|
|
|
|
---- Подготовка тетрады ----
|
---- Подготовка тетрады ----
|
trd_test_mode( cmd, ret, 0 ); -- переход в рабочий режим --
|
trd_test_mode( cmd, ret, 0 ); -- переход в рабочий режим --
|
trd_wait_cmd( cmd, ret, 0, 16, x"1600" ); -- DMAR0 - от тетрады 6 --
|
trd_wait_cmd( cmd, ret, 0, 16, x"1600" ); -- DMAR0 - от тетрады 6 --
|
|
|
trd_wait_cmd( cmd, ret, 1, 16#1F#, x"0001" ); -- Размер блока = 4 кБ --
|
trd_wait_cmd( cmd, ret, 1, 16#1F#, x"0001" ); -- Размер блока = 4 кБ --
|
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
|
|
trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" ); -- Подключение выхода генератора к DIO_IN --
|
trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" ); -- Подключение выхода генератора к DIO_IN --
|
|
|
trd_wait_cmd( cmd, ret, 6, 0, x"2038" ); -- запуск тетрады DIO_IN
|
trd_wait_cmd( cmd, ret, 6, 0, x"2038" ); -- запуск тетрады DIO_IN
|
|
|
trd_wait_cmd( cmd, ret, 1, 16#1E#, x"0020" ); -- Запуск тестовой последовательности --
|
trd_wait_cmd( cmd, ret, 1, 16#1E#, x"0020" ); -- Запуск тестовой последовательности --
|
|
|
wait for 20 us;
|
wait for 20 us;
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
if( data( 8 )='1' ) then
|
if( data( 8 )='1' ) then
|
write( str, string'(" - Дескриптор правильный" ));
|
write( str, string'(" - Дескриптор правильный" ));
|
else
|
else
|
write( str, string'(" - Ошибка чтения дескриптора" ));
|
write( str, string'(" - Ошибка чтения дескриптора" ));
|
error := error + 1;
|
error := error + 1;
|
end if;
|
end if;
|
|
|
writeline( log, str );
|
writeline( log, str );
|
|
|
if( error=0 ) then
|
if( error=0 ) then
|
|
|
---- Ожидание завершения DMA ----
|
---- Ожидание завершения DMA ----
|
dma_complete := 0;
|
dma_complete := 0;
|
for ii in 0 to 100 loop
|
for ii in 0 to 100 loop
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
if( data(5)='1' ) then
|
if( data(5)='1' ) then
|
write( str, string'(" - DMA завершён " ));
|
write( str, string'(" - DMA завершён " ));
|
dma_complete := 1;
|
dma_complete := 1;
|
|
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - сброс EOT
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - сброс EOT
|
|
|
end if;
|
end if;
|
writeline( log, str );
|
writeline( log, str );
|
|
|
if( dma_complete=1 ) then
|
if( dma_complete=1 ) then
|
exit;
|
exit;
|
end if;
|
end if;
|
|
|
wait for 1 us;
|
wait for 1 us;
|
|
|
end loop;
|
end loop;
|
|
|
writeline( log, str );
|
writeline( log, str );
|
|
|
if( dma_complete=0 ) then
|
if( dma_complete=0 ) then
|
write( str, string'("Ошибка - DMA не завершён " ));
|
write( str, string'("Ошибка - DMA не завершён " ));
|
writeline( log, str );
|
writeline( log, str );
|
error:=error+1;
|
error:=error+1;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
for ii in 0 to 3 loop
|
for ii in 0 to 3 loop
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
writeline( log, str );
|
writeline( log, str );
|
wait for 500 ns;
|
wait for 500 ns;
|
|
|
end loop;
|
end loop;
|
|
|
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
|
|
write( str, string'(" Блок 0 - прочитано: " ));
|
write( str, string'(" Блок 0 - прочитано: " ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
for ii in 0 to 15 loop
|
for ii in 0 to 15 loop
|
|
|
adr:= x"00800000";
|
adr:= x"00800000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_read( cmd, ret, adr, data );
|
int_mem_read( cmd, ret, adr, data );
|
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
end loop;
|
end loop;
|
|
|
writeline( log, str );
|
writeline( log, str );
|
|
|
write( str, string'(" Блок 1 - прочитано: " ));
|
write( str, string'(" Блок 1 - прочитано: " ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
for ii in 0 to 15 loop
|
for ii in 0 to 15 loop
|
|
|
adr:= x"00801000";
|
adr:= x"00801000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_read( cmd, ret, adr, data );
|
int_mem_read( cmd, ret, adr, data );
|
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
end loop;
|
end loop;
|
|
|
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
|
|
|
|
|
-- вывод в файл --
|
writeline( log, str );
|
writeline( log, str );
|
if( error=0 ) then
|
if( error=0 ) then
|
write( str, string'(" Тест завершён успешно " ));
|
write( str, string'("TEST finished successfully" ));
|
cnt_ok := cnt_ok + 1;
|
cnt_ok := cnt_ok + 1;
|
else
|
else
|
write( str, string'(" Тест не выполнен " ));
|
write( str, string'("TEST finished with ERR" ));
|
cnt_error := cnt_error + 1;
|
cnt_error := cnt_error + 1;
|
end if;
|
end if;
|
writeline( log, str );
|
writeline( log, str );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
|
-- вывод в консоль --
|
|
writeline( output, str );
|
|
if( error=0 ) then
|
|
write( str, string'("TEST finished successfully" ));
|
|
cnt_ok := cnt_ok + 1;
|
|
else
|
|
write( str, string'("TEST finished with ERR" ));
|
|
cnt_error := cnt_error + 1;
|
|
end if;
|
|
writeline( output, str );
|
|
writeline( output, str );
|
|
|
|
|
end test_adm_read_8kb;
|
end test_adm_read_8kb;
|
|
|
|
|
--! Проверка обращений к блоку MAIN
|
--! Проверка обращений к блоку MAIN
|
procedure test_block_main (
|
procedure test_block_main (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! команда
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! ответ
|
)
|
)
|
is
|
is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable str : line;
|
variable str : line;
|
|
|
variable error : integer:=0;
|
variable error : integer:=0;
|
variable dma_complete : integer;
|
variable dma_complete : integer;
|
|
|
begin
|
begin
|
|
|
write( str, string'("TEST_BLOCK_MAIN" ));
|
write( str, string'("TEST_BLOCK_MAIN" ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
|
block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
|
block_read( cmd, ret, 4, 16#08#, data );
|
block_read( cmd, ret, 4, 16#08#, data );
|
write( str, string'("БЛОК 4: " )); hwrite( str, data ); writeline( log, str );
|
write( str, string'("БЛОК 4: " )); hwrite( str, data ); writeline( log, str );
|
|
|
wait for 10 us;
|
wait for 10 us;
|
|
|
-- write( str, "Константы:" );
|
write( str, "Константы:" );
|
-- writeline( log, str );
|
writeline( log, str );
|
-- for ii in 0 to 5 loop
|
for ii in 0 to 5 loop
|
-- write( str, "Блок " );
|
write( str, "Блок " );
|
-- write( str, ii );
|
write( str, ii );
|
-- for jj in 0 to 7 loop
|
for jj in 0 to 7 loop
|
-- block_read( cmd, ret, ii, jj, data );
|
block_read( cmd, ret, ii, jj, data );
|
-- write( str, " " );
|
write( str, " " );
|
-- hwrite( str, data );
|
hwrite( str, data );
|
-- end loop;
|
end loop;
|
-- writeline( log, str );
|
writeline( log, str );
|
-- end loop;
|
end loop;
|
--
|
|
--
|
|
-- writeline( log, str );
|
|
--
|
|
-- block_read( cmd, ret, 0, 16#10#, data );
|
|
-- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
|
--
|
|
-- block_write( cmd, ret, 80, 16#08#, x"00000100" );
|
|
--
|
|
-- block_read( cmd, ret, 0, 16#10#, data );
|
|
-- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
|
--
|
|
-- block_write( cmd, ret, 80, 16#08#, x"00000200" );
|
|
--
|
|
-- block_read( cmd, ret, 0, 16#10#, data );
|
|
-- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
|
--
|
|
--
|
|
-- writeline( log, str );
|
|
-- if( error=0 ) then
|
|
-- write( str, " Тест завершён успешно " );
|
|
-- cnt_ok := cnt_ok + 1;
|
|
-- else
|
|
-- write( str, " Тест не выполнен " );
|
|
-- cnt_error := cnt_error + 1;
|
|
-- end if;
|
|
|
|
for ii in 0 to 127 loop
|
|
|
writeline( log, str );
|
|
|
|
block_read( cmd, ret, 0, 16#10#, data );
|
|
write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
|
|
|
block_write( cmd, ret, 80, 16#08#, x"00000100" );
|
|
|
|
block_read( cmd, ret, 0, 16#10#, data );
|
|
write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
|
|
|
block_write( cmd, ret, 80, 16#08#, x"00000200" );
|
|
|
|
block_read( cmd, ret, 0, 16#10#, data );
|
|
write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
|
|
|
|
|
|
for ii in 0 to 7 loop
|
|
|
block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
|
block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
|
block_read( cmd, ret, 4, 8, data );
|
block_read( cmd, ret, 4, 8, data );
|
write( str, string'("READ: " )); hwrite( str, data( 15 downto 0 ) ); writeline( log, str );
|
write( str, string'("READ: " )); hwrite( str, data( 15 downto 0 ) ); writeline( log, str );
|
if( data/=x"0000AA55" ) then
|
if( data/=x"0000AA55" ) then
|
error:=error+1;
|
error:=error+1;
|
end if;
|
end if;
|
|
|
end loop;
|
end loop;
|
|
|
|
|
|
|
|
-- вывод в файл --
|
|
writeline( log, str );
|
|
if( error=0 ) then
|
|
write( str, string'("TEST finished successfully" ));
|
|
cnt_ok := cnt_ok + 1;
|
|
else
|
|
write( str, string'("TEST finished with ERR" ));
|
|
cnt_error := cnt_error + 1;
|
|
end if;
|
writeline( log, str );
|
writeline( log, str );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
|
-- вывод в консоль --
|
|
writeline( output, str );
|
|
if( error=0 ) then
|
|
write( str, string'("TEST finished successfully" ));
|
|
cnt_ok := cnt_ok + 1;
|
|
else
|
|
write( str, string'("TEST finished with ERR" ));
|
|
cnt_error := cnt_error + 1;
|
|
end if;
|
|
writeline( output, str );
|
|
writeline( output, str );
|
|
|
|
|
end test_block_main;
|
end test_block_main;
|
|
|
|
|
|
|
|
|
--! Чтение 16 кБ с использованием двух блоков дескрипторов
|
--! Чтение 16 кБ с использованием двух блоков дескрипторов
|
procedure test_adm_read_16kb (
|
procedure test_adm_read_16kb (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! команда
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! ответ
|
)
|
)
|
is
|
is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable str : line;
|
variable str : line;
|
|
|
variable error : integer:=0;
|
variable error : integer:=0;
|
variable dma_complete : integer;
|
variable dma_complete : integer;
|
variable kk : integer;
|
variable kk : integer;
|
variable status : std_logic_vector( 15 downto 0 );
|
variable status : std_logic_vector( 15 downto 0 );
|
|
|
begin
|
begin
|
|
|
write( str, string'("TEST_ADM_READ_16KB" ));
|
write( str, string'("TEST_ADM_READ_16KB" ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
---- Формирование блока дескрипторов ---
|
---- Формирование блока дескрипторов ---
|
for ii in 0 to 256 loop
|
for ii in 0 to 256 loop
|
adr:= x"00100000";
|
adr:= x"00100000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
end loop;
|
end loop;
|
|
|
--- Блок 0 ---
|
--- Блок 0 ---
|
|
|
--- Дескриптор 0 ---
|
--- Дескриптор 0 ---
|
int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
int_mem_write( cmd, ret, x"00100004", x"00000111" ); -- переход к следующему дескриптору
|
int_mem_write( cmd, ret, x"00100004", x"00000111" ); -- переход к следующему дескриптору
|
|
|
--- Дескриптор 1 ---
|
--- Дескриптор 1 ---
|
int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
int_mem_write( cmd, ret, x"0010000C", x"00000112" ); -- переход к следующему блоку
|
int_mem_write( cmd, ret, x"0010000C", x"00000112" ); -- переход к следующему блоку
|
|
|
--- Дескриптор 2 ---
|
--- Дескриптор 2 ---
|
int_mem_write( cmd, ret, x"00100010", x"00001002" ); -- адрес следующего дескриптора
|
int_mem_write( cmd, ret, x"00100010", x"00001002" ); -- адрес следующего дескриптора
|
int_mem_write( cmd, ret, x"00100014", x"00000000" );
|
int_mem_write( cmd, ret, x"00100014", x"00000000" );
|
|
|
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
int_mem_write( cmd, ret, x"001001FC", x"14644953" );
|
int_mem_write( cmd, ret, x"001001FC", x"14644953" );
|
|
|
|
|
--- Блок 1 ---
|
--- Блок 1 ---
|
|
|
--- Дескриптор 0 ---
|
--- Дескриптор 0 ---
|
int_mem_write( cmd, ret, x"00100200", x"00008020" );
|
int_mem_write( cmd, ret, x"00100200", x"00008020" );
|
int_mem_write( cmd, ret, x"00100204", x"00000111" ); -- переход к следующему дескриптору
|
int_mem_write( cmd, ret, x"00100204", x"00000111" ); -- переход к следующему дескриптору
|
|
|
--- Дескриптор 1 ---
|
--- Дескриптор 1 ---
|
int_mem_write( cmd, ret, x"00100208", x"00008030" );
|
int_mem_write( cmd, ret, x"00100208", x"00008030" );
|
int_mem_write( cmd, ret, x"0010020C", x"00000110" ); -- остановка
|
int_mem_write( cmd, ret, x"0010020C", x"00000110" ); -- остановка
|
|
|
|
|
int_mem_write( cmd, ret, x"001003F8", x"00000000" );
|
int_mem_write( cmd, ret, x"001003F8", x"00000000" );
|
int_mem_write( cmd, ret, x"001003FC", x"D67C4953" );
|
int_mem_write( cmd, ret, x"001003FC", x"D67C4953" );
|
|
|
|
|
|
|
---- Программирование канала DMA ----
|
---- Программирование канала DMA ----
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
|
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
|
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
|
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
|
block_write( cmd, ret, 4, 23, x"00019000" ); -- LOCAL_ADR
|
block_write( cmd, ret, 4, 23, x"00019000" ); -- LOCAL_ADR
|
|
|
|
|
---- Подготовка тетрады ----
|
---- Подготовка тетрады ----
|
trd_test_mode( cmd, ret, 0 ); -- переход в рабочий режим --
|
trd_test_mode( cmd, ret, 0 ); -- переход в рабочий режим --
|
trd_wait_cmd( cmd, ret, 0, 16, x"1600" ); -- DMAR0 - от тетрады 6 --
|
trd_wait_cmd( cmd, ret, 0, 16, x"1600" ); -- DMAR0 - от тетрады 6 --
|
|
|
trd_wait_cmd( cmd, ret, 1, 16#1F#, x"0001" ); -- Размер блока = 4 кБ --
|
trd_wait_cmd( cmd, ret, 1, 16#1F#, x"0001" ); -- Размер блока = 4 кБ --
|
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
|
|
trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" ); -- Подключение выхода генератора к DIO_IN --
|
trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" ); -- Подключение выхода генератора к DIO_IN --
|
|
|
trd_wait_cmd( cmd, ret, 6, 0, x"2038" ); -- запуск тетрады DIO_IN
|
trd_wait_cmd( cmd, ret, 6, 0, x"2038" ); -- запуск тетрады DIO_IN
|
|
|
trd_wait_cmd( cmd, ret, 1, 16#1E#, x"06A0" ); -- Запуск тестовой последовательности --
|
trd_wait_cmd( cmd, ret, 1, 16#1E#, x"06A0" ); -- Запуск тестовой последовательности --
|
|
|
wait for 20 us;
|
wait for 20 us;
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
if( data( 8 )='1' ) then
|
if( data( 8 )='1' ) then
|
write( str, string'(" - Дескриптор правильный" ));
|
write( str, string'(" - Дескриптор правильный" ));
|
else
|
else
|
write( str, string'(" - Ошибка чтения дескриптора" ));
|
write( str, string'(" - Ошибка чтения дескриптора" ));
|
error := error + 1;
|
error := error + 1;
|
end if;
|
end if;
|
|
|
writeline( log, str );
|
writeline( log, str );
|
|
|
if( error=0 ) then
|
if( error=0 ) then
|
|
|
kk:=0;
|
kk:=0;
|
loop
|
loop
|
|
|
trd_status( cmd, ret, 6, status );
|
trd_status( cmd, ret, 6, status );
|
write( str, string'("TRD_STATUS: " )); hwrite( str, status );
|
write( str, string'("TRD_STATUS: " )); hwrite( str, status );
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
|
|
if( data(4)='1' ) then
|
if( data(4)='1' ) then
|
write( str, string'(" - завершено чтение блока " ));
|
write( str, string'(" - завершено чтение блока " ));
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - сброс EOT
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - сброс EOT
|
kk:=kk+1;
|
kk:=kk+1;
|
if( kk=4 ) then
|
if( kk=4 ) then
|
exit;
|
exit;
|
end if;
|
end if;
|
end if;
|
end if;
|
writeline( log, str );
|
writeline( log, str );
|
|
|
wait for 500 ns;
|
wait for 500 ns;
|
|
|
|
|
end loop;
|
end loop;
|
|
|
---- Ожидание завершения DMA ----
|
---- Ожидание завершения DMA ----
|
dma_complete := 0;
|
dma_complete := 0;
|
for ii in 0 to 100 loop
|
for ii in 0 to 100 loop
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
if( data(5)='1' ) then
|
if( data(5)='1' ) then
|
write( str, string'(" - DMA завершён " ));
|
write( str, string'(" - DMA завершён " ));
|
dma_complete := 1;
|
dma_complete := 1;
|
|
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - сброс EOT
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - сброс EOT
|
|
|
end if;
|
end if;
|
writeline( log, str );
|
writeline( log, str );
|
|
|
if( dma_complete=1 ) then
|
if( dma_complete=1 ) then
|
exit;
|
exit;
|
end if;
|
end if;
|
|
|
wait for 1 us;
|
wait for 1 us;
|
|
|
end loop;
|
end loop;
|
|
|
writeline( log, str );
|
writeline( log, str );
|
|
|
if( dma_complete=0 ) then
|
if( dma_complete=0 ) then
|
write( str, string'("Ошибка - DMA не завершён " ));
|
write( str, string'("Ошибка - DMA не завершён " ));
|
writeline( log, str );
|
writeline( log, str );
|
error:=error+1;
|
error:=error+1;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
for ii in 0 to 3 loop
|
for ii in 0 to 3 loop
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
writeline( log, str );
|
writeline( log, str );
|
wait for 500 ns;
|
wait for 500 ns;
|
|
|
end loop;
|
end loop;
|
|
|
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
|
|
write( str, string'(" Блок 0 - прочитано: " ));
|
write( str, string'(" Блок 0 - прочитано: " ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
for ii in 0 to 15 loop
|
for ii in 0 to 15 loop
|
|
|
adr:= x"00800000";
|
adr:= x"00800000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_read( cmd, ret, adr, data );
|
int_mem_read( cmd, ret, adr, data );
|
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
end loop;
|
end loop;
|
|
|
writeline( log, str );
|
writeline( log, str );
|
|
|
write( str, string'(" Блок 1 - прочитано: " ));
|
write( str, string'(" Блок 1 - прочитано: " ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
for ii in 0 to 15 loop
|
for ii in 0 to 15 loop
|
|
|
adr:= x"00801000";
|
adr:= x"00801000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_read( cmd, ret, adr, data );
|
int_mem_read( cmd, ret, adr, data );
|
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
end loop;
|
end loop;
|
|
|
write( str, string'(" Блок 2 - прочитано: " ));
|
write( str, string'(" Блок 2 - прочитано: " ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
for ii in 0 to 15 loop
|
for ii in 0 to 15 loop
|
|
|
adr:= x"00802000";
|
adr:= x"00802000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_read( cmd, ret, adr, data );
|
int_mem_read( cmd, ret, adr, data );
|
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
end loop;
|
end loop;
|
|
|
|
|
write( str, string'(" Блок 3 - прочитано: " ));
|
write( str, string'(" Блок 3 - прочитано: " ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
for ii in 0 to 15 loop
|
for ii in 0 to 15 loop
|
|
|
adr:= x"00803000";
|
adr:= x"00803000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_read( cmd, ret, adr, data );
|
int_mem_read( cmd, ret, adr, data );
|
|
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
end loop;
|
end loop;
|
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
|
|
|
|
|
-- вывод в файл --
|
writeline( log, str );
|
writeline( log, str );
|
if( error=0 ) then
|
if( error=0 ) then
|
write( str, string'(" Тест завершён успешно " ));
|
write( str, string'("TEST finished successfully" ));
|
cnt_ok := cnt_ok + 1;
|
cnt_ok := cnt_ok + 1;
|
else
|
else
|
write( str, string'(" Тест не выполнен " ));
|
write( str, string'("TEST finished with ERR" ));
|
cnt_error := cnt_error + 1;
|
cnt_error := cnt_error + 1;
|
end if;
|
end if;
|
writeline( log, str );
|
writeline( log, str );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
|
-- вывод в консоль --
|
|
writeline( output, str );
|
|
if( error=0 ) then
|
|
write( str, string'("TEST finished successfully" ));
|
|
cnt_ok := cnt_ok + 1;
|
|
else
|
|
write( str, string'("TEST finished with ERR" ));
|
|
cnt_error := cnt_error + 1;
|
|
end if;
|
|
writeline( output, str );
|
|
writeline( output, str );
|
|
|
|
|
|
|
end test_adm_read_16kb;
|
end test_adm_read_16kb;
|
|
|
|
|
|
|
|
|
--! Запись 16 кБ с использованием двух блоков дескрипторов
|
--! Запись 16 кБ с использованием двух блоков дескрипторов
|
procedure test_adm_write_16kb (
|
procedure test_adm_write_16kb (
|
signal cmd: out bh_cmd; --! команда
|
signal cmd: out bh_cmd; --! команда
|
signal ret: in bh_ret --! ответ
|
signal ret: in bh_ret --! ответ
|
)
|
)
|
is
|
is
|
|
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable adr : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable data : std_logic_vector( 31 downto 0 );
|
variable str : line;
|
variable str : line;
|
|
|
variable error : integer:=0;
|
variable error : integer:=0;
|
variable dma_complete : integer;
|
variable dma_complete : integer;
|
variable kk : integer;
|
variable kk : integer;
|
variable status : std_logic_vector( 15 downto 0 );
|
variable status : std_logic_vector( 15 downto 0 );
|
|
|
begin
|
begin
|
|
|
write( str, string'("TEST_ADM_WRITE_16KB" ));
|
write( str, string'("TEST_ADM_WRITE_16KB" ));
|
writeline( log, str );
|
writeline( log, str );
|
|
|
---- Формирование блока дескрипторов ---
|
---- Формирование блока дескрипторов ---
|
for ii in 0 to 256 loop
|
for ii in 0 to 256 loop
|
adr:= x"00100000";
|
adr:= x"00100000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
int_mem_write( cmd, ret, adr, x"00000000" );
|
end loop;
|
end loop;
|
|
|
---- Заполнение памяти ----
|
---- Заполнение памяти ----
|
for ii in 0 to 256 loop
|
for ii in 0 to 256 loop
|
adr:= x"00800000";
|
adr:= x"00800000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
data:=x"00A00000";
|
data:=x"00A00000";
|
data:=data + ii;
|
data:=data + ii;
|
int_mem_write( cmd, ret, adr, data );
|
int_mem_write( cmd, ret, adr, data );
|
end loop;
|
end loop;
|
|
|
for ii in 0 to 1023 loop
|
for ii in 0 to 1023 loop
|
adr:= x"00801000";
|
adr:= x"00801000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
data:=x"00A10000";
|
data:=x"00A10000";
|
data:=data + ii;
|
data:=data + ii;
|
int_mem_write( cmd, ret, adr, data );
|
int_mem_write( cmd, ret, adr, data );
|
end loop;
|
end loop;
|
|
|
for ii in 0 to 256 loop
|
for ii in 0 to 256 loop
|
adr:= x"00802000";
|
adr:= x"00802000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
data:=x"00A20000";
|
data:=x"00A20000";
|
data:=data + ii;
|
data:=data + ii;
|
int_mem_write( cmd, ret, adr, data );
|
int_mem_write( cmd, ret, adr, data );
|
end loop;
|
end loop;
|
|
|
for ii in 0 to 256 loop
|
for ii in 0 to 256 loop
|
adr:= x"00803000";
|
adr:= x"00803000";
|
adr:=adr + ii*4;
|
adr:=adr + ii*4;
|
data:=x"00A30000";
|
data:=x"00A30000";
|
data:=data + ii;
|
data:=data + ii;
|
int_mem_write( cmd, ret, adr, data );
|
int_mem_write( cmd, ret, adr, data );
|
end loop;
|
end loop;
|
|
|
--- Блок 0 ---
|
--- Блок 0 ---
|
|
|
--- Дескриптор 0 ---
|
--- Дескриптор 0 ---
|
int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
int_mem_write( cmd, ret, x"00100000", x"00008000" );
|
int_mem_write( cmd, ret, x"00100004", x"00000011" ); -- переход к следующему дескриптору
|
int_mem_write( cmd, ret, x"00100004", x"00000011" ); -- переход к следующему дескриптору
|
|
|
--- Дескриптор 1 ---
|
--- Дескриптор 1 ---
|
int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
int_mem_write( cmd, ret, x"00100008", x"00008010" );
|
int_mem_write( cmd, ret, x"0010000C", x"00000012" ); -- переход к следующему блоку
|
int_mem_write( cmd, ret, x"0010000C", x"00000012" ); -- переход к следующему блоку
|
|
|
--- Дескриптор 2 ---
|
--- Дескриптор 2 ---
|
int_mem_write( cmd, ret, x"00100010", x"00001002" ); -- адрес следующего дескриптора
|
int_mem_write( cmd, ret, x"00100010", x"00001002" ); -- адрес следующего дескриптора
|
int_mem_write( cmd, ret, x"00100014", x"00000000" );
|
int_mem_write( cmd, ret, x"00100014", x"00000000" );
|
|
|
|
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
|
int_mem_write( cmd, ret, x"001001FC", x"14A44953" );
|
int_mem_write( cmd, ret, x"001001FC", x"14A44953" );
|
|
|
|
|
--- Блок 1 ---
|
--- Блок 1 ---
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|
|
--- Дескриптор 0 ---
|
--- Дескриптор 0 ---
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int_mem_write( cmd, ret, x"00100200", x"00008020" );
|
int_mem_write( cmd, ret, x"00100200", x"00008020" );
|
int_mem_write( cmd, ret, x"00100204", x"00000011" ); -- переход к следующему дескриптору
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int_mem_write( cmd, ret, x"00100204", x"00000011" ); -- переход к следующему дескриптору
|
|
|
--- Дескриптор 1 ---
|
--- Дескриптор 1 ---
|
int_mem_write( cmd, ret, x"00100208", x"00008030" );
|
int_mem_write( cmd, ret, x"00100208", x"00008030" );
|
int_mem_write( cmd, ret, x"0010020C", x"00000010" ); -- остановка
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int_mem_write( cmd, ret, x"0010020C", x"00000010" ); -- остановка
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|
|
|
|
int_mem_write( cmd, ret, x"001003F8", x"00000000" );
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int_mem_write( cmd, ret, x"001003F8", x"00000000" );
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int_mem_write( cmd, ret, x"001003FC", x"D6BC4953" );
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int_mem_write( cmd, ret, x"001003FC", x"D6BC4953" );
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|
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|
|
|
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---- Программирование канала DMA ----
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---- Программирование канала DMA ----
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block_write( cmd, ret, 4, 8, x"00000023" ); -- DMA_MODE
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block_write( cmd, ret, 4, 8, x"00000023" ); -- DMA_MODE
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
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block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
|
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block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
|
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
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block_write( cmd, ret, 4, 23, x"0001D000" ); -- LOCAL_ADR
|
block_write( cmd, ret, 4, 23, x"0001D000" ); -- LOCAL_ADR
|
|
|
|
|
---- Подготовка тетрады ----
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---- Подготовка тетрады ----
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trd_test_mode( cmd, ret, 0 ); -- переход в рабочий режим --
|
trd_test_mode( cmd, ret, 0 ); -- переход в рабочий режим --
|
trd_wait_cmd( cmd, ret, 0, 16, x"1700" ); -- DMAR0 - от тетрады 7 --
|
trd_wait_cmd( cmd, ret, 0, 16, x"1700" ); -- DMAR0 - от тетрады 7 --
|
|
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trd_wait_cmd( cmd, ret, 1, 16#1D#, x"0001" ); -- Размер блока = 4 кБ --
|
trd_wait_cmd( cmd, ret, 1, 16#1D#, x"0001" ); -- Размер блока = 4 кБ --
|
|
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
|
|
trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" ); -- Подключение выхода генератора к DIO_IN --
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trd_wait_cmd( cmd, ret, 1, 16#0F#, x"0001" ); -- Подключение выхода генератора к DIO_IN --
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|
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trd_wait_cmd( cmd, ret, 7, 0, x"2038" ); -- запуск тетрады DIO_OUT
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trd_wait_cmd( cmd, ret, 7, 0, x"2038" ); -- запуск тетрады DIO_OUT
|
|
|
trd_wait_cmd( cmd, ret, 1, 16#1C#, x"0020" ); -- Запуск тестовой последовательности --
|
trd_wait_cmd( cmd, ret, 1, 16#1C#, x"0020" ); -- Запуск тестовой последовательности --
|
|
|
wait for 20 us;
|
wait for 20 us;
|
|
|
|
|
for ii in 0 to 20 loop
|
for ii in 0 to 20 loop
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
|
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
if( data( 8 )='1' ) then
|
if( data( 8 )='1' ) then
|
write( str, string'(" - Дескриптор правильный" ));
|
write( str, string'(" - Дескриптор правильный" ));
|
error := 0;
|
error := 0;
|
exit;
|
exit;
|
else
|
else
|
write( str, string'(" - Ошибка чтения дескриптора" ));
|
write( str, string'(" - Ошибка чтения дескриптора" ));
|
error := error + 1;
|
error := error + 1;
|
wait for 10 us;
|
wait for 10 us;
|
end if;
|
end if;
|
|
|
writeline( log, str );
|
writeline( log, str );
|
end loop;
|
end loop;
|
|
|
|
|
if( error=0 ) then
|
if( error=0 ) then
|
|
|
kk:=0;
|
kk:=0;
|
loop
|
loop
|
|
|
trd_status( cmd, ret, 6, status );
|
trd_status( cmd, ret, 6, status );
|
write( str, string'("TRD_STATUS: " )); hwrite( str, status );
|
write( str, string'("TRD_STATUS: " )); hwrite( str, status );
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
|
|
if( data(4)='1' ) then
|
if( data(4)='1' ) then
|
write( str, string'(" - завершено чтение блока " ));
|
write( str, string'(" - завершено чтение блока " ));
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - сброс EOT
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - сброс EOT
|
kk:=kk+1;
|
kk:=kk+1;
|
if( kk=4 ) then
|
if( kk=4 ) then
|
exit;
|
exit;
|
end if;
|
end if;
|
end if;
|
end if;
|
writeline( log, str );
|
writeline( log, str );
|
|
|
wait for 500 ns;
|
wait for 500 ns;
|
|
|
|
|
end loop;
|
end loop;
|
|
|
---- Ожидание завершения DMA ----
|
---- Ожидание завершения DMA ----
|
dma_complete := 0;
|
dma_complete := 0;
|
for ii in 0 to 100 loop
|
for ii in 0 to 100 loop
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
if( data(5)='1' ) then
|
if( data(5)='1' ) then
|
write( str, string'(" - DMA завершён " ));
|
write( str, string'(" - DMA завершён " ));
|
dma_complete := 1;
|
dma_complete := 1;
|
|
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - сброс EOT
|
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - сброс EOT
|
|
|
end if;
|
end if;
|
writeline( log, str );
|
writeline( log, str );
|
|
|
if( dma_complete=1 ) then
|
if( dma_complete=1 ) then
|
exit;
|
exit;
|
end if;
|
end if;
|
|
|
wait for 1 us;
|
wait for 1 us;
|
|
|
end loop;
|
end loop;
|
|
|
writeline( log, str );
|
writeline( log, str );
|
|
|
if( dma_complete=0 ) then
|
if( dma_complete=0 ) then
|
write( str, string'("Ошибка - DMA не завершён " ));
|
write( str, string'("Ошибка - DMA не завершён " ));
|
writeline( log, str );
|
writeline( log, str );
|
error:=error+1;
|
error:=error+1;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
for ii in 0 to 3 loop
|
for ii in 0 to 3 loop
|
|
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
block_read( cmd, ret, 4, 16, data ); -- STATUS
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
|
writeline( log, str );
|
writeline( log, str );
|
wait for 500 ns;
|
wait for 500 ns;
|
|
|
end loop;
|
end loop;
|
|
|
|
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
|
|
|
|
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
|
|
|
|
|
|
-- вывод в файл --
|
writeline( log, str );
|
writeline( log, str );
|
if( error=0 ) then
|
if( error=0 ) then
|
write( str, string'(" Тест завершён успешно " ));
|
write( str, string'("TEST finished successfully" ));
|
cnt_ok := cnt_ok + 1;
|
cnt_ok := cnt_ok + 1;
|
else
|
else
|
write( str, string'(" Тест не выполнен " ));
|
write( str, string'("TEST finished with ERR" ));
|
cnt_error := cnt_error + 1;
|
cnt_error := cnt_error + 1;
|
end if;
|
end if;
|
writeline( log, str );
|
writeline( log, str );
|
writeline( log, str );
|
writeline( log, str );
|
|
|
|
-- вывод в консоль --
|
|
writeline( output, str );
|
|
if( error=0 ) then
|
|
write( str, string'("TEST finished successfully" ));
|
|
cnt_ok := cnt_ok + 1;
|
|
else
|
|
write( str, string'("TEST finished with ERR" ));
|
|
cnt_error := cnt_error + 1;
|
|
end if;
|
|
writeline( output, str );
|
|
writeline( output, str );
|
|
|
|
|
end test_adm_write_16kb;
|
end test_adm_write_16kb;
|
|
|
end package body test_pkg;
|
end package body test_pkg;
|
|
|
|
|
