////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// WISHBONE revB.2 compliant Programable Interval Timer - Test Bench
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// WISHBONE revB.2 compliant Programable Interval Timer - Test Bench
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//
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//
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// Author: Bob Hayes
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// Author: Bob Hayes
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// rehayes@opencores.org
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// rehayes@opencores.org
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//
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//
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// Downloaded from: http://www.opencores.org/projects/pit.....
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// Downloaded from: http://www.opencores.org/projects/pit.....
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2011, Robert Hayes
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// Copyright (c) 2011, Robert Hayes
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//
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//
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the nor the
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// * Neither the name of the nor the
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// names of its contributors may be used to endorse or promote products
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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// derived from this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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`include "timescale.v"
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`include "timescale.v"
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module tst_bench_top();
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module tst_bench_top();
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parameter STOP_ON_ERROR = 1'b0;
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parameter STOP_ON_ERROR = 1'b0;
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parameter MAX_VECTOR = 1_000;
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parameter MAX_VECTOR = 1_000;
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//
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//
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// wires && regs
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// wires && regs
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//
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//
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logic mstr_test_clk;
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logic mstr_test_clk;
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logic [19:0] vector;
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logic [19:0] vector;
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logic [ 7:0] test_num;
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logic [ 7:0] test_num;
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logic rstn;
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logic rstn;
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logic sync_reset;
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logic sync_reset;
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logic [31:0] adr;
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logic [31:0] adr;
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logic [15:0] dat_i, dat_o, dat0_i, dat1_i, dat2_i, dat3_i;
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logic [15:0] dat_i, dat_o, dat0_i, dat1_i, dat2_i, dat3_i;
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logic we;
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logic we;
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logic stb;
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logic stb;
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logic cyc;
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logic cyc;
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logic ack, ack_1, ack_2, ack_3, ack_4;
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logic ack, ack_1, ack_2, ack_3, ack_4;
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logic inta_1, inta_2, inta_3, inta_4;
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logic inta_1, inta_2, inta_3, inta_4;
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logic count_en_1;
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logic count_en_1;
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logic count_flag_1;
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logic count_flag_1;
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logic [15:0] q, qq;
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logic [15:0] q, qq;
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logic [15:0] error_count;
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logic [15:0] error_count;
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logic scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
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logic scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
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logic sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
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logic sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
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// Name Address Locations
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// Name the Address Locations of the PIT Wishbone control registers
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parameter PIT_CNTRL = 5'b0_0000;
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parameter PIT_CNTRL = 5'b0_0000;
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parameter PIT_MOD = 5'b0_0001;
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parameter PIT_MOD = 5'b0_0001;
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parameter PIT_COUNT = 5'b0_0010;
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parameter PIT_COUNT = 5'b0_0010;
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parameter RD = 1'b1;
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parameter RD = 1'b1;
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parameter WR = 1'b0;
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parameter WR = 1'b0;
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parameter SADR = 7'b0010_000;
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parameter SADR = 7'b0010_000;
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parameter CTR_EN = 8'b1000_0000; // core enable bit
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parameter CTR_EN = 8'b1000_0000; // core enable bit
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parameter CTR_IEN = 8'b0100_0000; // core interrupt enable bit
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parameter CTR_IEN = 8'b0100_0000; // core interrupt enable bit
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// Name the control/status bits of the PIT registers
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parameter PIT_CNTRL_SLAVE = 16'h8000; // PIT Slave mode
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parameter PIT_CNTRL_SLAVE = 16'h8000; // PIT Slave mode
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parameter PIT_CNTRL_FLAG = 16'h0004; // PIT Rollover Flag
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parameter PIT_CNTRL_FLAG = 16'h0004; // PIT Rollover Flag
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parameter PIT_CNTRL_IRQEN = 16'h0002; // PIT Interupt Enable
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parameter PIT_CNTRL_IRQEN = 16'h0002; // PIT Interupt Enable
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parameter PIT_CNTRL_ENA = 16'h0001; // PIT Enable
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parameter PIT_CNTRL_ENA = 16'h0001; // PIT Enable
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parameter SLAVE_0_CNTRL = 5'b0_1000;
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parameter SLAVE_0_CNTRL = 5'b0_1000 + PIT_CNTRL;
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parameter SLAVE_0_MOD = 5'b0_1001;
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parameter SLAVE_0_MOD = 5'b0_1000 + PIT_MOD;
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parameter SLAVE_0_COUNT = 5'b0_1010;
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parameter SLAVE_0_COUNT = 5'b0_1000 + PIT_COUNT;
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parameter SLAVE_1_CNTRL = 5'b1_0000;
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parameter SLAVE_1_CNTRL = 5'b1_0000 + PIT_CNTRL;
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parameter SLAVE_1_MOD = 5'b1_0001;
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parameter SLAVE_1_MOD = 5'b1_0000 + PIT_MOD;
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parameter SLAVE_1_COUNT = 5'b1_0010;
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parameter SLAVE_1_COUNT = 5'b1_0000 + PIT_COUNT;
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parameter SLAVE_2_CNTRL_0 = 5'b1_1000;
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parameter SLAVE_2_CNTRL_0 = 5'b1_1000;
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parameter SLAVE_2_CNTRL_1 = 5'b1_1001;
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parameter SLAVE_2_CNTRL_1 = 5'b1_1001;
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parameter SLAVE_2_MOD_0 = 5'b1_1010;
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parameter SLAVE_2_MOD_0 = 5'b1_1010;
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parameter SLAVE_2_MOD_1 = 5'b1_1011;
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parameter SLAVE_2_MOD_1 = 5'b1_1011;
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parameter SLAVE_2_COUNT_0 = 5'b1_1100;
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parameter SLAVE_2_COUNT_0 = 5'b1_1100;
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parameter SLAVE_2_COUNT_1 = 5'b1_1101;
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parameter SLAVE_2_COUNT_1 = 5'b1_1101;
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// initial values and testbench setup
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// initial values and testbench setup
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initial
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initial
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begin
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begin
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mstr_test_clk = 0;
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mstr_test_clk <= 0;
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vector = 0;
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vector <= 0;
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test_num = 0;
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test_num <= 0;
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error_count = 0;
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error_count <= 0;
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`ifdef WAVES
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`ifdef WAVES
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$shm_open("waves");
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$shm_open("waves");
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$shm_probe("AS",tst_bench_top,"AS");
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$shm_probe("AS",tst_bench_top,"AS");
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$display("\nINFO: Signal dump enabled ...\n\n");
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$display("\nINFO: Signal dump enabled ...\n\n");
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`endif
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`endif
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`ifdef WAVES_V
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`ifdef WAVES_V
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$dumpfile ("pit_wave_dump.lxt");
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$dumpfile ("pit_wave_dump.lxt");
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$dumpvars (0, tst_bench_top);
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$dumpvars (0, tst_bench_top);
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$dumpon;
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$dumpon;
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$display("\nINFO: VCD Signal dump enabled ...\n\n");
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$display("\nINFO: VCD Signal dump enabled ...\n\n");
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`endif
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`endif
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`ifdef DEBUSSY
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`ifdef DEBUSSY
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$fsdbDumpfile("pit_wave_dump.fsdb");
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$fsdbDumpfile("pit_wave_dump.fsdb");
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$fsdbDumpvars(0);
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$fsdbDumpvars(0);
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$display("\nINFO: Debussy Signal dump enabled ...\n\n");
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$display("\nINFO: Debussy Signal dump enabled ...\n\n");
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`endif
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`endif
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end
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end
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// generate clock
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// generate clock
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always #20 mstr_test_clk = ~mstr_test_clk;
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always #20 mstr_test_clk = ~mstr_test_clk;
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// Keep a count of how many clocks we've simulated
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// Keep a count of how many clocks we've simulated
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always @(posedge mstr_test_clk)
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always @(posedge mstr_test_clk)
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begin
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begin
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vector <= vector + 1;
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vector <= vector + 1;
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if (vector > MAX_VECTOR)
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if (vector > MAX_VECTOR)
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begin
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begin
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error_count <= error_count + 1;
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error_count <= error_count + 1;
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$display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
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$display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
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wrap_up;
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wrap_up;
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end
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end
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end
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end
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// Add up errors tha come from WISHBONE read compares
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// Add up errors tha come from WISHBONE read compares
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always @u0.cmp_error_detect
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always @master.cmp_error_detect
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begin
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begin
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error_count <= error_count + 1;
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error_count <= error_count + 1;
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end
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end
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// Define a seperate interface for each PIT instance since each PIT
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// intstance has small differences
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wishbone_if #(.D_WIDTH (16),
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.A_WIDTH (3))
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wb_1(
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.wb_clk (mstr_test_clk),
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.wb_rst (1'b0),
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.arst (rstn));
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wishbone_if wb_2(
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.wb_clk (mstr_test_clk),
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.wb_rst (sync_reset),
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.arst (1'b0));
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wishbone_if wb_3(
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.wb_clk (mstr_test_clk),
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.wb_rst (sync_reset),
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.arst (1'b1));
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wishbone_if #(.D_WIDTH (8))
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wb_4(
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.wb_clk (mstr_test_clk),
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.wb_rst (sync_reset),
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.arst (1'b1));
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// hookup wishbone master model
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// hookup wishbone master model
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wb_master_model #(.dwidth(16), .awidth(32))
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wb_master_model #(.dwidth(16), .awidth(32))
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u0 (
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master (
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.wb_1(wb_1),
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.wb_2(wb_2),
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.wb_3(wb_3),
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.wb_4(wb_4),
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.clk(mstr_test_clk),
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.clk(mstr_test_clk),
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.rst(rstn),
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.rst(rstn),
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.adr(adr),
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.adr(adr),
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.din(dat_i),
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.din(dat_i),
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.dout(dat_o),
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.dout(dat_o),
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.cyc(cyc),
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.cyc(cyc),
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.stb(stb),
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.stb(stb),
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.we(we),
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.we(we),
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.sel(),
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.sel(),
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.ack(ack),
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.ack(ack),
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.err(1'b0),
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.err(1'b0),
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.rty(1'b0)
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.rty(1'b0)
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);
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);
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// Address decoding for different PIT module instances
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// Address decoding for different PIT module instances
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wire stb0 = stb && ~adr[4] && ~adr[3];
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wire stb0 = stb && ~adr[4] && ~adr[3];
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wire stb1 = stb && ~adr[4] && adr[3];
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wire stb1 = stb && ~adr[4] && adr[3];
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wire stb2 = stb && adr[4] && ~adr[3];
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wire stb2 = stb && adr[4] && ~adr[3];
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wire stb3 = stb && adr[4] && adr[3];
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wire stb3 = stb && adr[4] && adr[3];
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// Create the Read Data Bus
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// Create the Read Data Bus
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assign dat_i = ({16{stb0}} & dat0_i) |
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assign dat_i = ({16{stb0}} & dat0_i) |
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({16{stb1}} & dat1_i) |
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({16{stb1}} & dat1_i) |
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({16{stb2}} & dat2_i) |
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({16{stb2}} & dat2_i) |
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({16{stb3}} & {8'b0, dat3_i[7:0]});
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({16{stb3}} & {8'b0, dat3_i[7:0]});
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assign ack = ack_1 || ack_2 || ack_3 || ack_4;
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assign ack = ack_1 || ack_2 || ack_3 || ack_4;
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// hookup wishbone_PIT_master core - Parameters take all default values
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// hookup wishbone_PIT_slave core - Parameters take all default values
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// Async Reset, 16 bit Bus, 16 bit Granularity,Wait States
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// Async Reset, 16 bit Bus, 16 bit Granularity,Wait States
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pit_top #(.SINGLE_CYCLE(1'b0))
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pit_top pit_1(
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pit_1(
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// wishbone interface
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// wishbone interface
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.wb_clk_i(mstr_test_clk),
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.wb (wb_1),
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.wb_rst_i(1'b0),
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.arst_i(rstn),
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.wb_adr_i(adr[2:0]),
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.wb_dat_i(dat_o),
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.wb_dat_o(dat0_i),
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.wb_dat_o(dat0_i),
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.wb_we_i(we),
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.wb_stb (stb0),
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.wb_stb_i(stb0),
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.wb_ack (ack_1),
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.wb_cyc_i(cyc),
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.wb_sel_i( 2'b11 ),
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.wb_ack_o(ack_1),
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.pit_irq_o(inta_1),
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.pit_irq_o (inta_1),
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.pit_o(pit_1_out),
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.pit_o(pit_1_out),
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.ext_sync_i(1'b0),
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.ext_sync_i(1'b0),
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.cnt_sync_o(count_en_1),
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.cnt_sync_o(count_en_1),
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.cnt_flag_o(count_flag_1)
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.cnt_flag_o(count_flag_1)
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);
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);
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// hookup wishbone_PIT_slave core - Parameters take all default values
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// hookup wishbone_PIT_slave core - Parameters take all default values
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// Sync Reset, 16 bit Bus, 16 bit Granularity
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// Sync Reset, 16 bit Bus, 16 bit Granularity
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pit_top #(.ARST_LVL(1'b1))
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pit_top #(.ARST_LVL(1'b1))
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pit_2(
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pit_2(
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// wishbone interface
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// wishbone interface
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.wb_clk_i(mstr_test_clk),
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.wb (wb_2),
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.wb_rst_i(sync_reset),
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.arst_i(1'b0),
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.wb_adr_i(adr[2:0]),
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.wb_dat_i(dat_o),
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.wb_dat_o(dat1_i),
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.wb_dat_o(dat1_i),
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.wb_we_i(we),
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.wb_stb (stb1),
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.wb_stb_i(stb1),
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.wb_ack (ack_2),
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.wb_cyc_i(cyc),
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.wb_sel_i( 2'b11 ),
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.wb_ack_o(ack_2),
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.pit_irq_o(inta_2),
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.pit_irq_o(inta_2),
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.pit_o(pit_2_out),
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.pit_o(pit_2_out),
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.ext_sync_i(count_en_1),
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.ext_sync_i(count_en_1),
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.cnt_sync_o(count_en_2),
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.cnt_sync_o(count_en_2),
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.cnt_flag_o(count_flag_2)
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.cnt_flag_o(count_flag_2)
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);
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);
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// hookup wishbone_PIT_slave core
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// hookup wishbone_PIT_slave core
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// 16 bit Bus, 16 bit Granularity
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// 16 bit Bus, 16 bit Granularity
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pit_top #(.NO_PRESCALE(1'b1))
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pit_top #(.NO_PRESCALE(1'b1))
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pit_3(
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pit_3(
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// wishbone interface
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// wishbone interface
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.wb_clk_i(mstr_test_clk),
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.wb (wb_3),
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.wb_rst_i(sync_reset),
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.arst_i(1'b1),
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.wb_adr_i(adr[2:0]),
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.wb_dat_i(dat_o),
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.wb_dat_o(dat2_i),
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.wb_dat_o(dat2_i),
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.wb_we_i(we),
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.wb_stb (stb2),
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.wb_stb_i(stb2),
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.wb_ack (ack_3),
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.wb_cyc_i(cyc),
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.wb_sel_i( 2'b11 ),
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.wb_ack_o(ack_3),
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.pit_irq_o(inta_3),
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|
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.pit_irq_o(inta_3),
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.pit_o(pit_3_out),
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.pit_o(pit_3_out),
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.ext_sync_i(count_en_1),
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.ext_sync_i(count_en_1),
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.cnt_sync_o(count_en_3),
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.cnt_sync_o(count_en_3),
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.cnt_flag_o(count_flag_3)
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.cnt_flag_o(count_flag_3)
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);
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);
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// hookup wishbone_PIT_slave core
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// hookup wishbone_PIT_slave core
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// 8 bit Bus, 8 bit Granularity
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// 8 bit Bus, 8 bit Granularity
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pit_top #(.DWIDTH(8))
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pit_top #(.D_WIDTH(8))
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pit_4(
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pit_4(
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// wishbone interface
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// wishbone interface
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.wb_clk_i(mstr_test_clk),
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.wb (wb_4),
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.wb_rst_i(sync_reset),
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.arst_i(1'b1),
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.wb_adr_i(adr[2:0]),
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.wb_dat_i(dat_o[7:0]),
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.wb_dat_o(dat3_i[7:0]),
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.wb_dat_o(dat3_i[7:0]),
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.wb_we_i(we),
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.wb_stb (stb3),
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.wb_stb_i(stb3),
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.wb_ack (ack_4),
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.wb_cyc_i(cyc),
|
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.wb_sel_i( 2'b11 ),
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.wb_ack_o(ack_4),
|
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.pit_irq_o(inta_4),
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|
|
|
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.pit_irq_o(inta_4),
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.pit_o(pit_4_out),
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.pit_o(pit_4_out),
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.ext_sync_i(count_en_1),
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.ext_sync_i(count_en_1),
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.cnt_sync_o(count_en_4),
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.cnt_sync_o(count_en_4),
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.cnt_flag_o(count_flag_4)
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.cnt_flag_o(count_flag_4)
|
);
|
);
|
|
|
// Test Program
|
// Main Test Program -----------------------------------------------------------
|
initial
|
initial
|
begin
|
begin
|
$display("\nstatus: %t Testbench started", $time);
|
$display("\nstatus: %t Testbench started", $time);
|
|
|
// reset system
|
// reset system
|
rstn = 1'b1; // negate reset
|
rstn = 1'b1; // negate reset
|
repeat(1) @(posedge mstr_test_clk);
|
repeat(1) @(posedge mstr_test_clk);
|
sync_reset = 1'b1; // Make the sync reset 1 clock cycle long
|
sync_reset = 1'b1; // Make the sync reset 1 clock cycle long
|
#2; // move the async reset away from the clock edge
|
#2; // move the async reset away from the clock edge
|
rstn = 1'b0; // assert async reset
|
rstn = 1'b0; // assert async reset
|
#5; // Keep the async reset pulse with less than a clock cycle
|
#5; // Keep the async reset pulse with less than a clock cycle
|
rstn = 1'b1; // negate async reset
|
rstn = 1'b1; // negate async reset
|
repeat(1) @(posedge mstr_test_clk);
|
repeat(1) @(posedge mstr_test_clk);
|
sync_reset = 1'b0;
|
sync_reset = 1'b0;
|
|
|
$display("\nstatus: %t done reset", $time);
|
$display("\nstatus: %t done reset", $time);
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
|
|
repeat(2) @(posedge mstr_test_clk);
|
repeat(2) @(posedge mstr_test_clk);
|
|
|
//
|
//
|
// program core
|
// program core
|
//
|
//
|
|
|
reg_test_16;
|
reg_test_16;
|
|
|
reg_test_8;
|
reg_test_8;
|
|
|
u0.wb_write(1, SLAVE_0_CNTRL, PIT_CNTRL_SLAVE); // Enable Slave Mode
|
master.wb_write(1, SLAVE_0_CNTRL, PIT_CNTRL_SLAVE); // Enable Slave Mode
|
u0.wb_write(1, SLAVE_1_CNTRL, PIT_CNTRL_SLAVE); // Enable Slave Mode
|
master.wb_write(1, SLAVE_1_CNTRL, PIT_CNTRL_SLAVE); // Enable Slave Mode
|
u0.wb_write(1, SLAVE_2_CNTRL_1, 16'h0080); // Enable Slave Mode
|
master.wb_write(1, SLAVE_2_CNTRL_1, 16'h0080); // Enable Slave Mode
|
u0.wb_write(1, SLAVE_0_MOD, 16'h000a); // load Modulo
|
master.wb_write(1, SLAVE_0_MOD, 16'h000a); // load Modulo
|
u0.wb_write(1, SLAVE_1_MOD, 16'h0010); // load Modulo
|
master.wb_write(1, SLAVE_1_MOD, 16'h0010); // load Modulo
|
u0.wb_write(1, SLAVE_2_MOD_0, 16'h0010); // load Modulo
|
master.wb_write(1, SLAVE_2_MOD_0, 16'h0010); // load Modulo
|
|
|
// Set Master Mode PS=0, Modulo=16
|
// Set Master Mode PS=0, Modulo=16
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("TEST #%d Starts at vector=%d, ms_test", test_num, vector);
|
$display("TEST #%d Starts at vector=%d, ms_test", test_num, vector);
|
|
|
u0.wb_write(1, PIT_MOD, 16'h0010); // load prescaler hi-byte
|
master.wb_write(1, PIT_MOD, 16'h0010); // load prescaler hi-byte
|
u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_ENA); // Enable to start counting
|
master.wb_write(1, PIT_CNTRL, PIT_CNTRL_ENA); // Enable to start counting
|
$display("status: %t programmed registers", $time);
|
$display("status: %t programmed registers", $time);
|
|
|
wait_flag_set; // Wait for Counter to tomeout
|
wait_flag_set; // Wait for Counter to tomeout
|
u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
|
master.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
|
|
|
wait_flag_set; // Wait for Counter to tomeout
|
wait_flag_set; // Wait for Counter to tomeout
|
u0.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
|
master.wb_write(1, PIT_CNTRL, PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
|
|
|
repeat(10) @(posedge mstr_test_clk);
|
repeat(10) @(posedge mstr_test_clk);
|
u0.wb_write(1, PIT_CNTRL, 16'b0); //
|
master.wb_write(1, PIT_CNTRL, 16'b0); //
|
|
|
repeat(10) @(posedge mstr_test_clk);
|
repeat(10) @(posedge mstr_test_clk);
|
|
|
mstr_psx_modx(2,4);
|
mstr_psx_modx(2,4);
|
|
|
mstr_psx_modx(4,0);
|
mstr_psx_modx(4,0);
|
|
|
repeat(100) @(posedge mstr_test_clk);
|
repeat(100) @(posedge mstr_test_clk);
|
|
|
wrap_up;
|
wrap_up;
|
|
|
end // Main Test Flow
|
end // Main Test Flow ------------------------------------------------------
|
|
|
// Poll for flag set
|
// Poll for flag set
|
task wait_flag_set;
|
task wait_flag_set;
|
u0.wb_read(1, PIT_CNTRL, q);
|
master.wb_read(1, PIT_CNTRL, q);
|
while(~|(q & PIT_CNTRL_FLAG))
|
while(~|(q & PIT_CNTRL_FLAG))
|
u0.wb_read(1, PIT_CNTRL, q); // poll it until it is set
|
master.wb_read(1, PIT_CNTRL, q); // poll it until it is set
|
$display("PIT Flag set detected at vector =%d", vector);
|
$display("PIT Flag set detected at vector =%d", vector);
|
endtask
|
endtask
|
|
|
// check register bits - reset, read/write
|
// check register bits - reset, read/write
|
task reg_test_16;
|
task reg_test_16;
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
|
$display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
|
u0.wb_cmp(0, PIT_CNTRL, 16'h4000); // verify reset
|
master.wb_cmp(0, PIT_CNTRL, 16'h4000); // verify reset
|
u0.wb_cmp(0, PIT_MOD, 16'h0000); // verify reset
|
master.wb_cmp(0, PIT_MOD, 16'h0000); // verify reset
|
u0.wb_cmp(0, PIT_COUNT, 16'h0001); // verify reset
|
master.wb_cmp(0, PIT_COUNT, 16'h0001); // verify reset
|
|
|
u0.wb_write(1, PIT_CNTRL, 16'hfffe); // load prescaler lo-byte
|
master.wb_write(1, PIT_CNTRL, 16'hfffe); // load prescaler lo-byte
|
u0.wb_cmp( 0, PIT_CNTRL, 16'hCf02); // verify write data
|
master.wb_cmp( 0, PIT_CNTRL, 16'hCf02); // verify write data
|
u0.wb_write(1, PIT_CNTRL, 16'h0000); // load prescaler lo-byte
|
master.wb_write(1, PIT_CNTRL, 16'h0000); // load prescaler lo-byte
|
u0.wb_cmp( 0, PIT_CNTRL, 16'h4000); // verify write data
|
master.wb_cmp( 0, PIT_CNTRL, 16'h4000); // verify write data
|
|
|
u0.wb_write(1, PIT_MOD, 16'h5555); // load prescaler lo-byte
|
master.wb_write(1, PIT_MOD, 16'h5555); // load prescaler lo-byte
|
u0.wb_cmp( 0, PIT_MOD, 16'h5555); // verify write data
|
master.wb_cmp( 0, PIT_MOD, 16'h5555); // verify write data
|
u0.wb_write(1, PIT_MOD, 16'haaaa); // load prescaler lo-byte
|
master.wb_write(1, PIT_MOD, 16'haaaa); // load prescaler lo-byte
|
u0.wb_cmp( 0, PIT_MOD, 16'haaaa); // verify write data
|
master.wb_cmp( 0, PIT_MOD, 16'haaaa); // verify write data
|
|
|
u0.wb_write(0, PIT_COUNT, 16'hfffe);
|
master.wb_write(0, PIT_COUNT, 16'hfffe);
|
u0.wb_cmp( 0, PIT_COUNT, 16'h0001); // verify register not writable
|
master.wb_cmp( 0, PIT_COUNT, 16'h0001); // verify register not writable
|
endtask
|
endtask
|
|
|
|
// Check the registers when the PIT is configured for 8-bit mode
|
task reg_test_8;
|
task reg_test_8;
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("TEST #%d Starts at vector=%d, reg_test_8", test_num, vector);
|
$display("TEST #%d Starts at vector=%d, reg_test_8", test_num, vector);
|
u0.wb_cmp(0, SLAVE_2_CNTRL_0, 16'h0000); // verify reset
|
master.wb_cmp(0, SLAVE_2_CNTRL_0, 16'h0000); // verify reset
|
u0.wb_cmp(0, SLAVE_2_CNTRL_1, 16'h0040); // verify reset
|
master.wb_cmp(0, SLAVE_2_CNTRL_1, 16'h0040); // verify reset
|
u0.wb_cmp(0, SLAVE_2_MOD_0, 16'h0000); // verify reset
|
master.wb_cmp(0, SLAVE_2_MOD_0, 16'h0000); // verify reset
|
u0.wb_cmp(0, SLAVE_2_MOD_1, 16'h0000); // verify reset
|
master.wb_cmp(0, SLAVE_2_MOD_1, 16'h0000); // verify reset
|
u0.wb_cmp(0, SLAVE_2_COUNT_0, 16'h0001); // verify reset
|
master.wb_cmp(0, SLAVE_2_COUNT_0, 16'h0001); // verify reset
|
u0.wb_cmp(0, SLAVE_2_COUNT_1, 16'h0000); // verify reset
|
master.wb_cmp(0, SLAVE_2_COUNT_1, 16'h0000); // verify reset
|
|
|
u0.wb_write(1, SLAVE_2_CNTRL_0, 16'hfffe); // load prescaler lo-byte
|
master.wb_write(1, SLAVE_2_CNTRL_0, 16'hfffe); // load prescaler lo-byte
|
u0.wb_cmp( 0, SLAVE_2_CNTRL_0, 16'h0002); // verify write data
|
master.wb_cmp( 0, SLAVE_2_CNTRL_0, 16'h0002); // verify write data
|
u0.wb_write(1, SLAVE_2_CNTRL_0, 16'h0000); // load prescaler lo-byte
|
master.wb_write(1, SLAVE_2_CNTRL_0, 16'h0000); // load prescaler lo-byte
|
u0.wb_cmp( 0, SLAVE_2_CNTRL_0, 16'h0000); // verify write data
|
master.wb_cmp( 0, SLAVE_2_CNTRL_0, 16'h0000); // verify write data
|
u0.wb_cmp( 0, SLAVE_2_CNTRL_1, 16'h0040); // verify write data
|
master.wb_cmp( 0, SLAVE_2_CNTRL_1, 16'h0040); // verify write data
|
|
|
u0.wb_write(1, SLAVE_2_MOD_0, 16'hff55); // load prescaler lo-byte
|
master.wb_write(1, SLAVE_2_MOD_0, 16'hff55); // load prescaler lo-byte
|
u0.wb_cmp( 0, SLAVE_2_MOD_0, 16'h0055); // verify write data
|
master.wb_cmp( 0, SLAVE_2_MOD_0, 16'h0055); // verify write data
|
u0.wb_write(1, SLAVE_2_MOD_0, 16'hffaa); // load prescaler lo-byte
|
master.wb_write(1, SLAVE_2_MOD_0, 16'hffaa); // load prescaler lo-byte
|
u0.wb_cmp( 0, SLAVE_2_MOD_0, 16'h00aa); // verify write data
|
master.wb_cmp( 0, SLAVE_2_MOD_0, 16'h00aa); // verify write data
|
u0.wb_write(1, SLAVE_2_MOD_1, 16'hff66); // load prescaler lo-byte
|
master.wb_write(1, SLAVE_2_MOD_1, 16'hff66); // load prescaler lo-byte
|
u0.wb_cmp( 0, SLAVE_2_MOD_1, 16'h0066); // verify write data
|
master.wb_cmp( 0, SLAVE_2_MOD_1, 16'h0066); // verify write data
|
u0.wb_write(1, SLAVE_2_MOD_1, 16'hff99); // load prescaler lo-byte
|
master.wb_write(1, SLAVE_2_MOD_1, 16'hff99); // load prescaler lo-byte
|
u0.wb_cmp( 0, SLAVE_2_MOD_1, 16'h0099); // verify write data
|
master.wb_cmp( 0, SLAVE_2_MOD_1, 16'h0099); // verify write data
|
u0.wb_write(1, SLAVE_2_MOD_1, 16'hff00); // load prescaler lo-byte
|
master.wb_write(1, SLAVE_2_MOD_1, 16'hff00); // load prescaler lo-byte
|
|
|
u0.wb_write(0, SLAVE_2_COUNT_0, 16'hfffe);
|
master.wb_write(0, SLAVE_2_COUNT_0, 16'hfffe);
|
u0.wb_cmp( 0, SLAVE_2_COUNT_0, 16'h0001); // verify register not writable
|
master.wb_cmp( 0, SLAVE_2_COUNT_0, 16'h0001); // verify register not writable
|
u0.wb_write(0, SLAVE_2_COUNT_1, 16'hfffe);
|
master.wb_write(0, SLAVE_2_COUNT_1, 16'hfffe);
|
u0.wb_cmp( 0, SLAVE_2_COUNT_1, 16'h0000); // verify register not writable
|
master.wb_cmp( 0, SLAVE_2_COUNT_1, 16'h0000); // verify register not writable
|
endtask
|
endtask
|
|
|
task mstr_psx_modx(
|
task mstr_psx_modx(
|
logic [ 3:0] ps_val,
|
logic [ 3:0] ps_val,
|
logic [15:0] mod_val);
|
logic [15:0] mod_val);
|
logic [15:0] cntrl_val;
|
logic [15:0] cntrl_val;
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("TEST #%d Starts at vector=%d, mstr_psx_modx Pre=%h, Mod=%h",
|
$display("TEST #%d Starts at vector=%d, mstr_psx_modx Pre=%h, Mod=%h",
|
test_num, vector, ps_val, mod_val);
|
test_num, vector, ps_val, mod_val);
|
// program internal registers
|
// program internal registers
|
|
|
cntrl_val = {1'b0, 3'b0, ps_val, 8'b0} | PIT_CNTRL_IRQEN;
|
cntrl_val = {1'b0, 3'b0, ps_val, 8'b0} | PIT_CNTRL_IRQEN;
|
u0.wb_write(1, PIT_MOD, mod_val); // load modulo
|
master.wb_write(1, PIT_MOD, mod_val); // load modulo
|
u0.wb_write(1, PIT_CNTRL, ( cntrl_val | PIT_CNTRL_ENA)); // Enable to start counting
|
master.wb_write(1, PIT_CNTRL, ( cntrl_val | PIT_CNTRL_ENA)); // Enable to start counting
|
|
|
wait_flag_set; // Wait for Counter to timeout
|
wait_flag_set; // Wait for Counter to timeout
|
u0.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
|
master.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
|
|
|
wait_flag_set; // Wait for Counter to timeout
|
wait_flag_set; // Wait for Counter to timeout
|
u0.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
|
master.wb_write(1, PIT_CNTRL, cntrl_val | PIT_CNTRL_FLAG | PIT_CNTRL_ENA); //
|
|
|
repeat(10) @(posedge mstr_test_clk);
|
repeat(10) @(posedge mstr_test_clk);
|
|
|
u0.wb_write(1, PIT_CNTRL, 16'b0); //
|
master.wb_write(1, PIT_CNTRL, 16'b0); //
|
endtask
|
endtask
|
|
|
|
// End the simulation and print out the final results
|
task wrap_up;
|
task wrap_up;
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
repeat(10) @(posedge mstr_test_clk);
|
repeat(10) @(posedge mstr_test_clk);
|
$display("\nSimulation Finished!! - vector =%d", vector);
|
$display("\nSimulation Finished!! - vector =%d", vector);
|
if (error_count == 0)
|
if (error_count == 0)
|
$display("Simulation Passed");
|
$display("Simulation Passed");
|
else
|
else
|
$display("Simulation Failed --- Errors =%d", error_count);
|
$display("Simulation Failed --- Errors =%d", error_count);
|
|
|
$finish;
|
$finish;
|
endtask
|
endtask
|
|
|
|
|
endmodule // tst_bench_top
|
endmodule // tst_bench_top
|
|
|
|
|
