-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Present - a lightweight block cipher project ----
|
---- Present - a lightweight block cipher project ----
|
---- ----
|
---- ----
|
---- This file is part of the Present - a lightweight block ----
|
---- This file is part of the Present - a lightweight block ----
|
---- cipher project ----
|
---- cipher project ----
|
---- http://www.http://opencores.org/project,present ----
|
---- http://www.http://opencores.org/project,present ----
|
---- ----
|
---- ----
|
---- Description: ----
|
---- Description: ----
|
---- State machine of 'pure' Present cipher with RS-232 ----
|
---- State machine of 'pure' Present cipher with RS-232 ----
|
---- communication with PC. For more informations see below. ----
|
---- communication with PC. For more informations see below. ----
|
---- To Do: ----
|
---- To Do: ----
|
---- ----
|
---- ----
|
---- Author(s): ----
|
---- Author(s): ----
|
---- - Krzysztof Gajewski, gajos@opencores.org ----
|
---- - Krzysztof Gajewski, gajos@opencores.org ----
|
---- k.gajewski@gmail.com ----
|
---- k.gajewski@gmail.com ----
|
---- ----
|
---- ----
|
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
|
---- Copyright (C) 2013 Authors and OPENCORES.ORG ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
---- restriction provided that this copyright statement is not ----
|
---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- ----
|
---- ----
|
---- This source file is free software; you can redistribute it ----
|
---- This source file is free software; you can redistribute it ----
|
---- and-or modify it under the terms of the GNU Lesser General ----
|
---- and-or modify it under the terms of the GNU Lesser General ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- later version. ----
|
---- later version. ----
|
---- ----
|
---- ----
|
---- This source is distributed in the hope that it will be ----
|
---- This source is distributed in the hope that it will be ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- details. ----
|
---- details. ----
|
---- ----
|
---- ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- Public License along with this source; if not, download it ----
|
---- Public License along with this source; if not, download it ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- from http://www.opencores.org/lgpl.shtml ----
|
---- ----
|
---- ----
|
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use work.kody.ALL;
|
use work.kody.ALL;
|
|
|
-- Uncomment the following library declaration if using
|
-- Uncomment the following library declaration if using
|
-- arithmetic functions with Signed or Unsigned values
|
-- arithmetic functions with Signed or Unsigned values
|
--use IEEE.NUMERIC_STD.ALL;
|
--use IEEE.NUMERIC_STD.ALL;
|
|
|
-- Uncomment the following library declaration if instantiating
|
-- Uncomment the following library declaration if instantiating
|
-- any Xilinx primitives in this code.
|
-- any Xilinx primitives in this code.
|
--library UNISIM;
|
--library UNISIM;
|
--use UNISIM.VComponents.all;
|
--use UNISIM.VComponents.all;
|
|
|
entity PresentCommSM is
|
entity PresentCommSM is
|
port (
|
port (
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
reset : in STD_LOGIC;
|
RDAsig : in STD_LOGIC;
|
RDAsig : in STD_LOGIC;
|
TBEsig : in STD_LOGIC;
|
TBEsig : in STD_LOGIC;
|
RDsig : out STD_LOGIC;
|
RDsig : out STD_LOGIC;
|
WRsig : out STD_LOGIC;
|
WRsig : out STD_LOGIC;
|
textDataEn : out STD_LOGIC;
|
textDataEn : out STD_LOGIC;
|
textDataShift : out STD_LOGIC;
|
textDataShift : out STD_LOGIC;
|
keyDataEn : out STD_LOGIC;
|
keyDataEn : out STD_LOGIC;
|
keyDataShift : out STD_LOGIC;
|
keyDataShift : out STD_LOGIC;
|
ciphDataEn : out STD_LOGIC;
|
ciphDataEn : out STD_LOGIC;
|
ciphDataShift : out STD_LOGIC;
|
ciphDataShift : out STD_LOGIC;
|
startSig : out STD_LOGIC;
|
startSig : out STD_LOGIC;
|
readySig : in STD_LOGIC
|
readySig : in STD_LOGIC
|
);
|
);
|
end PresentCommSM;
|
end PresentCommSM;
|
|
|
architecture Behavioral of PresentCommSM is
|
architecture Behavioral of PresentCommSM is
|
|
|
-- counter used for determine number of readed/sended data (key, text, result)
|
-- counter used for determine number of readed/sended data (key, text, result)
|
component counter is
|
component counter is
|
generic (
|
generic (
|
w_5 : integer := 5
|
w_5 : integer := 5
|
);
|
);
|
port (
|
port (
|
clk, reset, cnt_res : in std_logic;
|
clk, reset, cnt_res : in std_logic;
|
num : out std_logic_vector (w_5-1 downto 0)
|
num : out std_logic_vector (w_5-1 downto 0)
|
);
|
);
|
end component counter;
|
end component counter;
|
|
|
-- signals
|
-- signals
|
|
|
signal state : stany_comm := NOP;
|
signal state : stany_comm := NOP;
|
signal next_state : stany_comm := NOP;
|
signal next_state : stany_comm := NOP;
|
|
|
-- modify for variable key size
|
-- modify for variable key size
|
signal serialDataCtrCt : STD_LOGIC;
|
signal serialDataCtrCt : STD_LOGIC;
|
signal serialDataCtrOut : STD_LOGIC_VECTOR(3 downto 0);
|
signal serialDataCtrOut : STD_LOGIC_VECTOR(3 downto 0);
|
signal serialDataCtrReset : STD_LOGIC;
|
signal serialDataCtrReset : STD_LOGIC;
|
signal ctrReset : STD_LOGIC;
|
signal ctrReset : STD_LOGIC;
|
-- DO NOT MODIFY!!!
|
-- DO NOT MODIFY!!!
|
signal shiftDataCtrCt : STD_LOGIC;
|
signal shiftDataCtrCt : STD_LOGIC;
|
signal shiftDataCtrOut : STD_LOGIC_VECTOR(2 downto 0);
|
signal shiftDataCtrOut : STD_LOGIC_VECTOR(2 downto 0);
|
|
|
begin
|
begin
|
-- In this state machine is determined, that firs data should be 64 bit text
|
-- In this state machine is determined, that firs data should be 64 bit text
|
-- after text, key should appear. After receiving last byte of key, ciphertext
|
-- after text, key should appear. After receiving last byte of key, ciphertext
|
-- is counted. And later it is sended back to PC.
|
-- is counted. And later it is sended back to PC.
|
ctrReset <= serialDataCtrReset or reset;
|
ctrReset <= serialDataCtrReset or reset;
|
SM : process(state, RDAsig, TBEsig, shiftDataCtrOut, serialDataCtrOut, readySig)
|
SM : process(state, RDAsig, TBEsig, shiftDataCtrOut, serialDataCtrOut, readySig)
|
begin
|
begin
|
case state is
|
case state is
|
-- No operation - waiting for incoming data
|
-- No operation - waiting for incoming data
|
when NOP =>
|
when NOP =>
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '0';
|
startSig <= '0';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
-- data has come
|
-- data has come
|
if (RDAsig = '1') then
|
if (RDAsig = '1') then
|
next_state <= READ_DATA_TEXT;
|
next_state <= READ_DATA_TEXT;
|
else
|
else
|
next_state <= NOP;
|
next_state <= NOP;
|
end if;
|
end if;
|
-- Text data enable and read data
|
-- Text data enable and read data
|
when READ_DATA_TEXT =>
|
when READ_DATA_TEXT =>
|
RDsig <= '1';
|
RDsig <= '1';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '1';
|
textDataEn <= '1';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '0';
|
startSig <= '0';
|
-- counter of retrieved bytes
|
-- counter of retrieved bytes
|
serialDataCtrCt <= '1';
|
serialDataCtrCt <= '1';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
next_state <= DECODE_READ_TEXT;
|
next_state <= DECODE_READ_TEXT;
|
-- Data readed, stop counter and check if proper number of byte
|
-- Data readed, stop counter and check if proper number of byte
|
-- was readed
|
-- was readed
|
when DECODE_READ_TEXT =>
|
when DECODE_READ_TEXT =>
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '0';
|
startSig <= '0';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
-- 8 bytes should be readed
|
-- 8 bytes should be readed
|
if (serialDataCtrOut(3 downto 0) = "1000") then
|
if (serialDataCtrOut(3 downto 0) = "1000") then
|
-- 8 bytes was readed
|
-- 8 bytes was readed
|
next_state <= TEMP_STATE;
|
next_state <= TEMP_STATE;
|
else
|
else
|
-- 8 bytes was not readed
|
-- 8 bytes was not readed
|
next_state <= MOVE_TEXT;
|
next_state <= MOVE_TEXT;
|
end if;
|
end if;
|
-- Reset counter for next reading
|
-- Reset counter for next reading
|
when TEMP_STATE =>
|
when TEMP_STATE =>
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '0';
|
startSig <= '0';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '1';
|
serialDataCtrReset <= '1';
|
next_state <= NOP_FOR_KEY;
|
next_state <= NOP_FOR_KEY;
|
-- Here data are shfted in shift register - another shift counter are used
|
-- Here data are shfted in shift register - another shift counter are used
|
when MOVE_TEXT =>
|
when MOVE_TEXT =>
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '1';
|
textDataShift <= '1';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '0';
|
startSig <= '0';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '1';
|
shiftDataCtrCt <= '1';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
if (shiftDataCtrOut(2 downto 0) = "111") then
|
if (shiftDataCtrOut(2 downto 0) = "111") then
|
next_state <= NOP;
|
next_state <= NOP;
|
else
|
else
|
next_state <= MOVE_TEXT;
|
next_state <= MOVE_TEXT;
|
end if;
|
end if;
|
-- "No operation 2" waiting for data - it could be optimized in way,
|
-- "No operation 2" waiting for data - it could be optimized in way,
|
-- that waiting for key and text could be the same state, but it was
|
-- that waiting for key and text could be the same state, but it was
|
-- intentionally separated.
|
-- intentionally separated.
|
when NOP_FOR_KEY =>
|
when NOP_FOR_KEY =>
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '0';
|
startSig <= '0';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
if (RDAsig = '1') then
|
if (RDAsig = '1') then
|
-- data has come
|
-- data has come
|
next_state <= READ_DATA_KEY;
|
next_state <= READ_DATA_KEY;
|
else
|
else
|
next_state <= NOP_FOR_KEY;
|
next_state <= NOP_FOR_KEY;
|
end if;
|
end if;
|
-- Key data enable and read data
|
-- Key data enable and read data
|
when READ_DATA_KEY =>
|
when READ_DATA_KEY =>
|
RDsig <= '1';
|
RDsig <= '1';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '1';
|
keyDataEn <= '1';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '0';
|
startSig <= '0';
|
-- counter of retrieved bytes
|
-- counter of retrieved bytes
|
serialDataCtrCt <= '1';
|
serialDataCtrCt <= '1';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
next_state <= DECODE_READ_KEY;
|
next_state <= DECODE_READ_KEY;
|
-- Data readed, stop counter and check if proper number of byte
|
-- Data readed, stop counter and check if proper number of byte
|
-- was readed
|
-- was readed
|
when DECODE_READ_KEY =>
|
when DECODE_READ_KEY =>
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '0';
|
startSig <= '0';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
-- 10 bytes should be readed
|
-- 10 bytes should be readed
|
if (serialDataCtrOut(3 downto 0) = "1010") then
|
if (serialDataCtrOut(3 downto 0) = "1010") then
|
-- 10 bytes was readed
|
-- 10 bytes was readed
|
next_state <= TEMP2_STATE;
|
next_state <= TEMP2_STATE;
|
else
|
else
|
-- 10 bytes was not readed
|
-- 10 bytes was not readed
|
next_state <= MOVE_KEY;
|
next_state <= MOVE_KEY;
|
end if;
|
end if;
|
-- Reset counter for next reading
|
-- Reset counter for next reading
|
when TEMP2_STATE =>
|
when TEMP2_STATE =>
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '0';
|
startSig <= '0';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '1';
|
serialDataCtrReset <= '1';
|
next_state <= PRESENT_ENCODE;
|
next_state <= PRESENT_ENCODE;
|
-- Here data are shfted in shift register - another shift counter are used
|
-- Here data are shfted in shift register - another shift counter are used
|
when MOVE_KEY =>
|
when MOVE_KEY =>
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '1';
|
keyDataShift <= '1';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '0';
|
startSig <= '0';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '1';
|
shiftDataCtrCt <= '1';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
if (shiftDataCtrOut(2 downto 0) = "111") then
|
if (shiftDataCtrOut(2 downto 0) = "111") then
|
next_state <= NOP_FOR_KEY;
|
next_state <= NOP_FOR_KEY;
|
else
|
else
|
next_state <= MOVE_KEY;
|
next_state <= MOVE_KEY;
|
end if;
|
end if;
|
-- All suitable data was readed Present encode start
|
-- All suitable data was readed Present encode start
|
when PRESENT_ENCODE =>
|
when PRESENT_ENCODE =>
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '1';
|
startSig <= '1';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
-- change state if Present result ready
|
-- change state if Present result ready
|
if (readySig = '1') then
|
if (readySig = '1') then
|
ciphDataEn <= '1';
|
ciphDataEn <= '1';
|
next_state <= WRITE_OUT;
|
next_state <= WRITE_OUT;
|
else
|
else
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
next_state <= PRESENT_ENCODE;
|
next_state <= PRESENT_ENCODE;
|
end if;
|
end if;
|
-- similar control of writing result as during reading
|
-- similar control of writing result as during reading
|
when WRITE_OUT =>
|
when WRITE_OUT =>
|
RDsig <= '0';
|
RDsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '1';
|
startSig <= '1';
|
serialDataCtrCt <= '1';
|
serialDataCtrCt <= '1';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
if (serialDataCtrOut = "1000") then
|
if (serialDataCtrOut = "1000") then
|
WRsig <= '0';
|
WRsig <= '0';
|
next_state <= TEMP_OUT;
|
next_state <= TEMP_OUT;
|
else
|
else
|
WRsig <= '1';
|
WRsig <= '1';
|
next_state <= MOVE_OUT;
|
next_state <= MOVE_OUT;
|
end if;
|
end if;
|
-- all data was sended - start new Present encode cycle
|
-- all data was sended - start new Present encode cycle
|
when TEMP_OUT =>
|
when TEMP_OUT =>
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '1';
|
startSig <= '1';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '1';
|
serialDataCtrReset <= '1';
|
next_state <= NOP;
|
next_state <= NOP;
|
when MOVE_OUT =>
|
when MOVE_OUT =>
|
if (TBEsig = '0') then
|
if (TBEsig = '0') then
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '0';
|
ciphDataShift <= '0';
|
startSig <= '1';
|
startSig <= '1';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
shiftDataCtrCt <= '0';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
next_state <= MOVE_OUT;
|
next_state <= MOVE_OUT;
|
else
|
else
|
RDsig <= '0';
|
RDsig <= '0';
|
WRsig <= '0';
|
WRsig <= '0';
|
textDataEn <= '0';
|
textDataEn <= '0';
|
textDataShift <= '0';
|
textDataShift <= '0';
|
keyDataEn <= '0';
|
keyDataEn <= '0';
|
keyDataShift <= '0';
|
keyDataShift <= '0';
|
ciphDataEn <= '0';
|
ciphDataEn <= '0';
|
ciphDataShift <= '1';
|
ciphDataShift <= '1';
|
startSig <= '1';
|
startSig <= '1';
|
serialDataCtrCt <= '0';
|
serialDataCtrCt <= '0';
|
shiftDataCtrCt <= '1';
|
shiftDataCtrCt <= '1';
|
serialDataCtrReset <= '0';
|
serialDataCtrReset <= '0';
|
if (shiftDataCtrOut = "111") then
|
if (shiftDataCtrOut = "111") then
|
next_state <= WRITE_OUT;
|
next_state <= WRITE_OUT;
|
else
|
else
|
next_state <= MOVE_OUT;
|
next_state <= MOVE_OUT;
|
end if;
|
end if;
|
end if;
|
end if;
|
end case;
|
end case;
|
end process SM;
|
end process SM;
|
|
|
state_modifier : process (clk, reset)
|
state_modifier : process (clk, reset)
|
begin
|
begin
|
if (clk = '1' and clk'Event) then
|
|
if (reset = '1') then
|
if (reset = '1') then
|
state <= NOP;
|
state <= NOP;
|
else
|
elsif (clk = '1' and clk'Event) then
|
state <= next_state;
|
state <= next_state;
|
end if;
|
end if;
|
end if;
|
|
end process state_modifier;
|
end process state_modifier;
|
|
|
-- counter for controling number of bytes of readed data
|
-- counter for controling number of bytes of readed data
|
dataCounter : counter
|
dataCounter : counter
|
generic map(
|
generic map(
|
w_5 => 4
|
w_5 => 4
|
)
|
)
|
port map (
|
port map (
|
cnt_res => serialDataCtrCt,
|
cnt_res => serialDataCtrCt,
|
num => serialDataCtrOut,
|
num => serialDataCtrOut,
|
clk => clk,
|
clk => clk,
|
reset => ctrReset
|
reset => ctrReset
|
);
|
);
|
|
|
-- counter for controling number of shifted bits of readed data
|
-- counter for controling number of shifted bits of readed data
|
shiftCounter : counter
|
shiftCounter : counter
|
generic map(
|
generic map(
|
w_5 => 3
|
w_5 => 3
|
)
|
)
|
port map (
|
port map (
|
cnt_res => shiftDataCtrCt,
|
cnt_res => shiftDataCtrCt,
|
num => shiftDataCtrOut,
|
num => shiftDataCtrOut,
|
clk => clk,
|
clk => clk,
|
reset => reset
|
reset => reset
|
);
|
);
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
