/*
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/*
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RC4 PRGA module implementation
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RC4 PRGA module implementation
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Copyright 2012 - Alfredo Ortega
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Copyright 2012 - Alfredo Ortega
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aortega@alu.itba.edu.ar
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aortega@alu.itba.edu.ar
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This library is free software: you can redistribute it and/or
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This library is free software: you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation, either
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License as published by the Free Software Foundation, either
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version 3 of the License, or (at your option) any later version.
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version 3 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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You should have received a copy of the GNU Lesser General Public
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License along with this library. If not, see <http://www.gnu.org/licenses/>.
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License along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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`include "rc4.inc"
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`include "/home/alfred/docto/FPGADesign/rc4-prbs/trunk/rc4.inc"
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module rc4(clk,rst,output_ready,password_input,K);
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module rc4(clk,rst,output_ready,password_input,K);
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input clk; // Clock
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input clk; // Clock
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input rst; // Reset
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input rst; // Reset
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input [7:0] password_input; // Password input
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input [7:0] password_input; // Password input
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output output_ready; // Output valid
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output output_ready; // Output valid
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output [7:0] K; // Output port
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output [7:0] K; // Output port
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wire clk, rst; // clock, reset
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wire clk, rst; // clock, reset
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reg output_ready;
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reg output_ready;
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wire [7:0] password_input;
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wire [7:0] password_input;
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/* RC4 PRGA */
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/* RC4 PRGA */
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// Key
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// Key
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reg [7:0] key[0:`KEY_SIZE-1];
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reg [7:0] key[0:`KEY_SIZE-1];
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// S array
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// S array
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reg [7:0] S[0:256];
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reg [7:0] S[0:256];
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reg [9:0] discardCount;
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// Key-scheduling state
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// Key-scheduling state
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`define KSS_KEYREAD 4'h0
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`define KSS_KEYREAD 4'h0
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`define KSS_KEYSCHED1 4'h1
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`define KSS_KEYSCHED1 4'h1
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`define KSS_KEYSCHED2 4'h2
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`define KSS_KEYSCHED2 4'h2
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`define KSS_KEYSCHED3 4'h3
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`define KSS_KEYSCHED3 4'h3
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`define KSS_CRYPTO 4'h4
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`define KSS_CRYPTO 4'h4
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`define KSS_CRYPTO2 4'h5
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`define KSS_CRYPTO2 4'h5
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// Variable names from http://en.wikipedia.org/wiki/RC4
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// Variable names from http://en.wikipedia.org/wiki/RC4
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reg [3:0] KSState;
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reg [3:0] KSState;
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reg [7:0] i; // Counter
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reg [7:0] i; // Counter
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reg [7:0] j;
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reg [7:0] j;
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reg [7:0] K;
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reg [7:0] K;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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begin
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begin
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i <= 8'h0;
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i <= 8'h0;
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KSState <= `KSS_KEYREAD;
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KSState <= `KSS_KEYREAD;
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output_ready <= 0;
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output_ready <= 0;
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j <= 0;
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j <= 0;
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end
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end
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else
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else
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case (KSState)
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case (KSState)
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`KSS_KEYREAD: begin // KSS_KEYREAD state: Read key from input
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`KSS_KEYREAD: begin // KSS_KEYREAD state: Read key from input
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if (i == `KEY_SIZE)
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if (i == `KEY_SIZE)
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begin
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begin
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KSState <= `KSS_KEYSCHED1;
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KSState <= `KSS_KEYSCHED1;
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i<=8'h00;
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i<=8'h00;
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end
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end
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else begin
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else begin
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i <= i+1;
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i <= i+1;
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key[i] <= password_input;
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key[i] <= password_input;
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$display ("key[%d] = %08X",i,password_input);
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$display ("key[%d] = %08X",i,password_input);
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end
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end
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end
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end
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/*
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/*
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for i from 0 to 255
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for i from 0 to 255
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S[i] := i
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S[i] := i
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endfor
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endfor
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*/
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*/
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`KSS_KEYSCHED1: begin // KSS_KEYSCHED1: Increment counter for S initialization
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`KSS_KEYSCHED1: begin // KSS_KEYSCHED1: Increment counter for S initialization
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S[i] <= i;
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S[i] <= i;
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if (i == 8'hFF)
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if (i == 8'hFF)
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begin
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begin
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KSState <= `KSS_KEYSCHED2;
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KSState <= `KSS_KEYSCHED2;
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i <= 8'h00;
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i <= 8'h00;
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end
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end
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else i <= i +1;
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else i <= i +1;
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end
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end
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/*
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/*
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j := 0
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j := 0
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for i from 0 to 255
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for i from 0 to 255
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j := (j + S[i] + key[i mod keylength]) mod 256
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j := (j + S[i] + key[i mod keylength]) mod 256
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swap values of S[i] and S[j]
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swap values of S[i] and S[j]
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endfor
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endfor
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*/
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*/
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`KSS_KEYSCHED2: begin // KSS_KEYSCHED2: Initialize S array
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`KSS_KEYSCHED2: begin // KSS_KEYSCHED2: Initialize S array
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j <= (j + S[i] + key[i % `KEY_SIZE]);
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j <= (j + S[i] + key[i % `KEY_SIZE]);
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KSState <= `KSS_KEYSCHED3;
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KSState <= `KSS_KEYSCHED3;
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end
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end
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`KSS_KEYSCHED3: begin // KSS_KEYSCHED3: S array permutation
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`KSS_KEYSCHED3: begin // KSS_KEYSCHED3: S array permutation
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S[i]<=S[j];
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S[i]<=S[j];
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S[j]<=S[i];
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S[j]<=S[i];
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if (i == 8'hFF)
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if (i == 8'hFF)
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begin
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begin
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KSState <= `KSS_CRYPTO;
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KSState <= `KSS_CRYPTO;
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i <= 8'h01;
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i <= 8'h01;
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j <= 8'h00;
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j <= 8'h00;
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discardCount <= 10'h0;
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end
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end
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else begin
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else begin
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i <= i + 1;
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i <= i + 1;
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KSState <= `KSS_KEYSCHED2;
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KSState <= `KSS_KEYSCHED2;
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end
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end
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end
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end
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/*
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/*
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i := 0
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i := 0
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j := 0
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j := 0
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while GeneratingOutput:
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while GeneratingOutput:
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i := (i + 1) mod 256
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i := (i + 1) mod 256
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j := (j + S[i]) mod 256
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j := (j + S[i]) mod 256
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swap values of S[i] and S[j]
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swap values of S[i] and S[j]
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K := S[(S[i] + S[j]) mod 256]
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K := S[(S[i] + S[j]) mod 256]
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output K
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output K
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endwhile
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endwhile
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*/
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*/
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`KSS_CRYPTO: begin //KSS_CRYPTO: Output crypto stream
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`KSS_CRYPTO: begin //KSS_CRYPTO: Output crypto stream
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j <= (j + S[i]);
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j <= (j + S[i]);
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KSState <= `KSS_CRYPTO2;
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KSState <= `KSS_CRYPTO2;
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output_ready <= 0; // K not valid yet
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output_ready <= 0; // K not valid yet
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end
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end
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`KSS_CRYPTO2: begin
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`KSS_CRYPTO2: begin
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S[i] <= S[j];
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S[i] <= S[j];
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S[j] <= S[i]; // We can do this because of verilog.
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S[j] <= S[i]; // We can do this because of verilog.
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K <= S[ S[i]+S[j] ];
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K <= S[ S[i]+S[j] ];
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output_ready <= 1; // Valid K at output
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if (discardCount<1000)
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discardCount<=discardCount+1;
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else output_ready <= 1; // Valid K at output
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i <= i+1;
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i <= i+1;
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KSState <= `KSS_CRYPTO;
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KSState <= `KSS_CRYPTO;
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end
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end
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default: begin
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default: begin
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end
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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