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[/] [robust_axi2apb/] [trunk/] [src/] [base/] [axi2apb_wr.v] - Diff between revs 8 and 13

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Rev 8 Rev 13
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////  Author: Eyal Hochberg                                      ////
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INCLUDE def_axi2apb.txt
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_wr.v
OUTFILE PREFIX_wr.v
 
 
module  PREFIX_wr (PORTS);
module  PREFIX_wr (PORTS);
 
 
   input                          clk;
   input                          clk;
   input                          reset;
   input                          reset;
 
 
   input                  GROUP_APB3;
   input                  GROUP_APB3;
 
 
   input                  cmd_err;
   input                  cmd_err;
   input [ID_BITS-1:0]    cmd_id;
   input [ID_BITS-1:0]    cmd_id;
   output                 finish_wr;
   output                 finish_wr;
 
 
   port                   WGROUP_APB_AXI_W;
   port                   WGROUP_APB_AXI_W;
   port                   BGROUP_APB_AXI_B;
   port                   BGROUP_APB_AXI_B;
 
 
 
 
   parameter              RESP_OK     = 2'b00;
   parameter              RESP_OK     = 2'b00;
   parameter              RESP_SLVERR = 2'b10;
   parameter              RESP_SLVERR = 2'b10;
   parameter              RESP_DECERR = 2'b11;
   parameter              RESP_DECERR = 2'b11;
 
 
   reg                    BGROUP_APB_AXI_B.OUT;
   reg                    BGROUP_APB_AXI_B.OUT;
 
 
 
 
   assign                 finish_wr = BVALID & BREADY;
   assign                 finish_wr = BVALID & BREADY;
 
 
   assign                 WREADY = psel & penable & pwrite & pready;
   assign                 WREADY = psel & penable & pwrite & pready;
 
 
   always @(posedge clk or posedge reset)
   always @(posedge clk or posedge reset)
     if (reset)
     if (reset)
           begin
           begin
         BGROUP_APB_AXI_B.OUT <= #FFD {GROUP_APB_AXI_B.OUT.WIDTH{1'b0}};
         BGROUP_APB_AXI_B.OUT <= #FFD {GROUP_APB_AXI_B.OUT.WIDTH{1'b0}};
           end
           end
         else if (finish_wr)
         else if (finish_wr)
           begin
           begin
         BGROUP_APB_AXI_B.OUT <= #FFD {GROUP_APB_AXI_B.OUT.WIDTH{1'b0}};
         BGROUP_APB_AXI_B.OUT <= #FFD {GROUP_APB_AXI_B.OUT.WIDTH{1'b0}};
           end
           end
         else if (psel & penable & pwrite & pready)
         else if (psel & penable & pwrite & pready)
           begin
           begin
             BID    <= #FFD cmd_id;
             BID    <= #FFD cmd_id;
                 BRESP  <= #FFD cmd_err ? RESP_SLVERR : pslverr ? RESP_DECERR : RESP_OK;
                 BRESP  <= #FFD cmd_err ? RESP_SLVERR : pslverr ? RESP_DECERR : RESP_OK;
                 BVALID <= #FFD 1'b1;
                 BVALID <= #FFD 1'b1;
           end
           end
 
 
endmodule
endmodule
 
 
 
 
 
 

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