// ============================================================================
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// ============================================================================
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// ALU
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// ALU
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// - perform datapath operations
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// - perform datapath operations
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//
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//
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//
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//
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// (C) 2009-2012 Robert Finch
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// (C) 2009-2013 Robert Finch
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// robfinch[remove]@opencores.org
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// robfinch[remove]@finitron.ca
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// Verilog
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// Verilog
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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function carry;
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function carry;
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input op;
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input op;
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input a;
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input a;
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input b;
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input b;
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input s;
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input s;
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begin
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begin
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carry = op ? (~a&b)|(s&~a)|(s&b) : (a&b)|(a&~s)|(b&~s);
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carry = op ? (~a&b)|(s&~a)|(s&b) : (a&b)|(a&~s)|(b&~s);
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end
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end
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endfunction
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endfunction
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function overflow;
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function overflow;
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input op;
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input op;
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input a;
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input a;
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input b;
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input b;
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input s;
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input s;
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begin
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begin
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overflow = (op ^ s ^ b) & (~op ^ a ^ b);
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overflow = (op ^ s ^ b) & (~op ^ a ^ b);
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end
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end
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endfunction
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endfunction
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reg [15:0] alu_o;
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reg [15:0] alu_o;
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reg [15:0] a;
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reg [15:0] a;
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reg [15:0] b;
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reg [15:0] b;
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wire amsb = w ? a[15] : a[7];
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wire amsb = w ? a[15] : a[7];
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wire bmsb = w ? b[15] : b[7];
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wire bmsb = w ? b[15] : b[7];
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wire [15:0] as = {!a[15],a[14:0]};
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wire [15:0] as = {!a[15],a[14:0]};
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wire [15:0] bs = {!b[15],b[14:0]};
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wire [15:0] bs = {!b[15],b[14:0]};
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wire signed [15:0] sa = a;
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wire signed [15:0] sa = a;
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wire signed [15:0] sb = b;
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wire signed [15:0] sb = b;
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wire signed [7:0] als = a[7:0];
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wire signed [7:0] als = a[7:0];
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wire signed [7:0] bls = b[7:0];
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wire signed [7:0] bls = b[7:0];
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wire signed [15:0] p = als * bls;
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wire signed [15:0] p = als * bls;
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wire signed [31:0] wp = sa * sb;
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wire signed [31:0] wp = sa * sb;
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wire [15:0] p16 = a[7:0] * b[7:0];
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wire [15:0] p16 = a[7:0] * b[7:0];
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wire [31:0] p32 = a * b;
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wire [31:0] p32 = a * b;
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// Compute AL/10
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// Compute AL/10
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// - multiply by 1/10 = 26/256
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// - multiply by 1/10 = 26/256
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wire [15:0] al26 = {al,4'b0} + {al,3'b0} + {al,1'b0}; // * 26
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wire [15:0] al26 = {al,4'b0} + {al,3'b0} + {al,1'b0}; // * 26
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wire [7:0] aldv10 = al26[15:8]; // 256
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wire [7:0] aldv10 = al26[15:8]; // 256
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wire [15:0] cmp_o = a - b;
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wire [15:0] cmp_o = a - b;
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wire eq = a == b;
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wire eq = a == b;
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wire ltu = a < b;
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wire ltu = a < b;
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wire lt = as < bs;
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wire lt = as < bs;
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wire [31:0] shlo = {16'h0000,b} << shftamt;
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wire [31:0] shlo = {16'h0000,b} << shftamt;
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wire [31:0] shruo = {b,16'h0000} >> shftamt;
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wire [31:0] shruo = {b,16'h0000} >> shftamt;
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wire [15:0] shro = ~(~b >> shftamt);
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wire [15:0] shro = ~(~b >> shftamt);
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wire [32:0] shlco = {16'h0000,b,cf} << shftamt;
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wire [32:0] shlco = {16'h0000,b,cf} << shftamt;
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wire [32:0] shrcuo = {cf,b,16'h0000} >> shftamt;
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wire [32:0] shrcuo = {cf,b,16'h0000} >> shftamt;
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wire [15:0] shlo8 = {8'h00,b[7:0]} << shftamt;
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wire [15:0] shlo8 = {8'h00,b[7:0]} << shftamt;
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wire [15:0] shruo8 = {b[7:0],8'h00} >> shftamt;
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wire [15:0] shruo8 = {b[7:0],8'h00} >> shftamt;
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wire [ 7:0] shro8 = ~(~b[7:0] >> shftamt);
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wire [ 7:0] shro8 = ~(~b[7:0] >> shftamt);
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wire [16:0] shlco8 = {8'h00,b,cf} << shftamt;
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wire [16:0] shlco8 = {8'h00,b,cf} << shftamt;
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wire [16:0] shrcuo8 = {cf,b[7:0],8'h00} >> shftamt;
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wire [16:0] shrcuo8 = {cf,b[7:0],8'h00} >> shftamt;
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wire div16_done;
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wire div16_done;
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wire div32_done;
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wire div32_done;
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wire [15:0] q16;
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wire [15:0] q16;
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wire [7:0] r16;
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wire [7:0] r16;
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wire [31:0] q32;
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wire [31:0] q32;
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wire [15:0] r32;
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wire [15:0] r32;
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wire [31:0] negdxax = -{dx,ax};
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wire [31:0] negdxax = -{dx,ax};
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divr2 #(16) udiv1
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divr2 #(16) udiv1
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(
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(
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.rst(rst_i),
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.rst(rst_i),
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.clk(clk_i),
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.clk(clk_i),
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.ce(1'b1),
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.ce(1'b1),
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.ld(ld_div16),
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.ld(ld_div16),
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.su(TTT[0]),
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.su(TTT[0]),
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.ri(1'b0),
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.ri(1'b0),
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.a(ax),
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.a(ax),
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.b(b[7:0]),
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.b(b[7:0]),
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.i(8'h00),
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.i(8'h00),
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.q(q16),
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.q(q16),
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.r(r16),
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.r(r16),
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.divByZero(),
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.divByZero(),
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.done(div16_done)
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.done(div16_done)
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);
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);
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divr2 #(32) udiv2
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divr2 #(32) udiv2
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(
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(
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.rst(rst_i),
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.rst(rst_i),
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.clk(clk_i),
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.clk(clk_i),
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.ce(1'b1),
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.ce(1'b1),
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.ld(ld_div32),
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.ld(ld_div32),
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.su(TTT[0]),
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.su(TTT[0]),
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.ri(1'b0),
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.ri(1'b0),
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.a({dx,ax}),
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.a({dx,ax}),
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.b(b),
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.b(b),
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.i(16'h0000),
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.i(16'h0000),
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.q(q32),
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.q(q32),
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.r(r32),
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.r(r32),
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.divByZero(),
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.divByZero(),
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.done(div32_done)
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.done(div32_done)
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);
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);
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always @(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)
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always @* //(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)
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begin
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begin
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casex(ir)
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casex(ir)
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`MOV_M2AL,`MOV_M2AX,`LDS,`LES:
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`MOV_M2AL,`MOV_M2AX,`LDS,`LES:
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alu_o <= a;
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alu_o <= a;
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`MOV_MR,`MOV_R2S,
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`MOV_MR,`MOV_R2S,
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`MOV_RR8,`MOV_RR16,
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`MOV_RR8,`MOV_RR16,
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`MOV_I8M,`MOV_I16M,
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`MOV_I8M,`MOV_I16M,
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`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
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`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
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`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
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`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
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alu_o <= b;
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alu_o <= b;
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`XCHG_MEM:
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`XCHG_MEM:
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alu_o <= b;
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alu_o <= b;
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`ADD,`ADD_ALI8,`ADD_AXI16: alu_o <= a + b;
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`ADD,`ADD_ALI8,`ADD_AXI16: alu_o <= a + b;
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`SUB,`SUB_ALI8,`SUB_AXI16: alu_o <= a - b;
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`SUB,`SUB_ALI8,`SUB_AXI16: alu_o <= a - b;
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`ADC,`ADC_ALI8,`ADC_AXI16: alu_o <= a + b + cf;
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`ADC,`ADC_ALI8,`ADC_AXI16: alu_o <= a + b + cf;
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`SBB,`SBB_ALI8,`SBB_AXI16: alu_o <= a - b - cf;
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`SBB,`SBB_ALI8,`SBB_AXI16: alu_o <= a - b - cf;
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`AND,`AND_ALI8,`AND_AXI16: alu_o <= a & b;
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`AND,`AND_ALI8,`AND_AXI16: alu_o <= a & b;
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`TEST,`TEST_ALI8,`TEST_AXI16: alu_o <= a & b;
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`TEST,`TEST_ALI8,`TEST_AXI16: alu_o <= a & b;
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`OR, `OR_ALI8, `OR_AXI16: alu_o <= a | b;
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`OR, `OR_ALI8, `OR_AXI16: alu_o <= a | b;
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`XOR,`XOR_ALI8,`XOR_AXI16: alu_o <= a ^ b;
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`XOR,`XOR_ALI8,`XOR_AXI16: alu_o <= a ^ b;
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`CMP,`CMP_ALI8,`CMP_AXI16: alu_o <= a - b;
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`CMP,`CMP_ALI8,`CMP_AXI16: alu_o <= a - b;
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`SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
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`SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
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`INC_REG: alu_o <= a + 16'd1;
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`INC_REG: alu_o <= a + 16'd1;
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`DEC_REG: alu_o <= a - 16'd1;
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`DEC_REG: alu_o <= a - 16'd1;
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`IMUL: alu_o <= w ? p : wp[15:0];
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// `IMUL: alu_o <= w ? p : wp[15:0];
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`ALU_I2R8:
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`ALU_I2R8:
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case(TTT)
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case(TTT)
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3'd0: alu_o <= a + b; // ADD
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3'd0: alu_o <= a + b; // ADD
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3'd1: alu_o <= a | b; // OR
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3'd1: alu_o <= a | b; // OR
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3'd2: alu_o <= a + b + cf; // ADC
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3'd2: alu_o <= a + b + cf; // ADC
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3'd3: alu_o <= a - b - cf; // SBB
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3'd3: alu_o <= a - b - cf; // SBB
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3'd4: alu_o <= a & b; // AND
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3'd4: alu_o <= a & b; // AND
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3'd5: alu_o <= a - b; // SUB
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3'd5: alu_o <= a - b; // SUB
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3'd6: alu_o <= a ^ b; // XOR
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3'd6: alu_o <= a ^ b; // XOR
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default: alu_o <= 16'h0000;
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default: alu_o <= 16'h0000;
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endcase
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endcase
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// ToDo: fix sign extension / extra immediate byte ?
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// ToDo: fix sign extension / extra immediate byte ?
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`ALU_I2R16:
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`ALU_I2R16:
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case(TTT)
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case(TTT)
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3'd0: alu_o <= a + b; // ADD
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3'd0: alu_o <= a + b; // ADD
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3'd1: alu_o <= a | b; // OR
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3'd1: alu_o <= a | b; // OR
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3'd2: alu_o <= a + b + cf; // ADC
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3'd2: alu_o <= a + b + cf; // ADC
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3'd3: alu_o <= a - b - cf; // SBB
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3'd3: alu_o <= a - b - cf; // SBB
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3'd4: alu_o <= a & b; // AND
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3'd4: alu_o <= a & b; // AND
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3'd5: alu_o <= a - b; // SUB
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3'd5: alu_o <= a - b; // SUB
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3'd6: alu_o <= a ^ b; // XOR
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3'd6: alu_o <= a ^ b; // XOR
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default: alu_o <= 16'h0000;
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default: alu_o <= 16'h0000;
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endcase
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endcase
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8'hF6,8'hF7:
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8'hF6,8'hF7:
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begin
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case(TTT)
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case(TTT)
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3'd0: alu_o <= a & b; // TEST
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3'd0: alu_o <= a & b; // TEST
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3'd2: alu_o <= ~b; // NOT
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3'd2: alu_o <= ~b; // NOT
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3'd3: alu_o <= -b; // NEG
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3'd3: alu_o <= -b; // NEG
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3'd4: alu_o <= w ? p32[15:0] : p16; // MUL
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3'd4: alu_o <= w ? p32[15:0] : p16; // MUL
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3'd5: alu_o <= w ? wp[15:0] : p[15:0]; // IMUL
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3'd5: alu_o <= w ? wp[15:0] : p[15:0]; // IMUL
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3'd6: alu_o <= 16'h0000; // DIV
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3'd6: alu_o <= 16'h0000; // DIV
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3'd7: alu_o <= 16'h0000; // IDIV
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3'd7: alu_o <= 16'h0000; // IDIV
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default: alu_o <= 16'h0000;
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default: alu_o <= 16'h0000;
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endcase
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endcase
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end
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`AAA:
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`AAA:
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if (al[3:0]>4'h9 || af) begin
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if (al[3:0]>4'h9 || af) begin
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alu_o[3:0] <= al[3:0] + 4'd6;
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alu_o[3:0] <= al[3:0] + 4'd6;
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alu_o[7:4] <= 4'h0;
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alu_o[7:4] <= 4'h0;
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alu_o[15:8] <= ah + 8'd1;
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alu_o[15:8] <= ah + 8'd1;
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end
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end
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else
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else
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alu_o <= ax;
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alu_o <= ax;
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`AAS:
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`AAS:
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if (al[3:0]>4'h9 || af) begin
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if (al[3:0]>4'h9 || af) begin
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alu_o[3:0] <= al[3:0] - 4'd6;
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alu_o[3:0] <= al[3:0] - 4'd6;
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alu_o[7:4] <= 4'h0;
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alu_o[7:4] <= 4'h0;
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alu_o[15:8] <= ah - 8'd1;
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alu_o[15:8] <= ah - 8'd1;
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end
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end
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else
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else
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alu_o <= ax;
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alu_o <= ax;
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// ToDo: fix +1 carry
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// ToDo: fix +1 carry
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`DAA:
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`DAA:
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begin
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begin
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alu_o <= 16'h0000;
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alu_o <= 16'h0000;
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if (al[3:0]>4'h9 || af) begin
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if (al[3:0]>4'h9 || af) begin
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alu_o[3:0] <= al[3:0] + 4'd6;
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alu_o[3:0] <= al[3:0] + 4'd6;
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end
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end
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if (al[7:4]>4'h9 || cf) begin
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if (al[7:4]>4'h9 || cf) begin
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alu_o[7:4] <= al[7:4] + 4'd6;
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alu_o[7:4] <= al[7:4] + 4'd6;
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end
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end
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end
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end
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// ToDo: fix +1 carry
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// ToDo: fix +1 carry
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`DAS:
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`DAS:
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begin
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begin
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alu_o <= 16'h0000;
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alu_o <= 16'h0000;
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if (al[3:0]>4'h9 || af) begin
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if (al[3:0]>4'h9 || af) begin
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alu_o[3:0] <= al[3:0] - 4'd6;
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alu_o[3:0] <= al[3:0] - 4'd6;
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end
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end
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if (al[7:4]>4'h9 || cf) begin
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if (al[7:4]>4'h9 || cf) begin
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alu_o[7:4] <= al[7:4] - 4'd6;
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alu_o[7:4] <= al[7:4] - 4'd6;
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end
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end
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end
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end
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`MORE1:
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`MORE1:
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casex(ir2)
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casex(ir2)
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`AAM:
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`AAM:
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begin
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begin
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alu_o[ 7:0] <= al - aldv10;
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alu_o[ 7:0] <= al - aldv10;
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alu_o[15:8] <= aldv10;
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alu_o[15:8] <= aldv10;
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end
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end
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default:
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default:
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alu_o <= 16'h0000;
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alu_o <= 16'h0000;
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endcase
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endcase
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`MORE2:
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`MORE2:
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casex(ir2)
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casex(ir2)
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`AAD:
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`AAD:
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begin
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begin
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alu_o[ 7:0] <= {ah,3'b0} + {ah,1'b0} + al;
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alu_o[ 7:0] <= {ah,3'b0} + {ah,1'b0} + al;
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alu_o[15:8] <= 8'h00;
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alu_o[15:8] <= 8'h00;
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end
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end
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default:
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default:
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alu_o <= 16'h0000;
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alu_o <= 16'h0000;
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endcase
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endcase
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default: alu_o <= 16'h0000;
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default: alu_o <= 16'h0000;
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endcase
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endcase
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end
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end
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|
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assign pres = ~^alu_o[7:0];
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assign pres = ~^alu_o[7:0];
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assign reszw = alu_o==16'h0000;
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assign reszw = alu_o==16'h0000;
|
assign reszb = alu_o[7:0]==8'h00;
|
assign reszb = alu_o[7:0]==8'h00;
|
assign resnb = alu_o[7];
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assign resnb = alu_o[7];
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assign resnw = alu_o[15];
|
assign resnw = alu_o[15];
|
|
|
assign resz = w ? reszw : reszb;
|
assign resz = w ? reszw : reszb;
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assign resn = w ? resnw : resnb;
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assign resn = w ? resnw : resnb;
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|
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