//============================================================================
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//============================================================================
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// DIVIDE.v
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// DIVIDE.v
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//
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//
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// (C) 2009-2012 Robert Finch
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// (C) 2009-2012 Robert Finch
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// Stratford
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// Stratford
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// robfinch<remove>@opencores.org
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// robfinch<remove>@opencores.org
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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// Check for divide by zero
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// Check for divide by zero
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// Load the divider
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// Load the divider
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DIVIDE1:
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DIVIDE1:
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begin
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begin
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state <= DIVIDE2;
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state <= DIVIDE2;
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// Check for divide by zero
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// Check for divide by zero
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if (w) begin
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if (w) begin
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if (b[15:0]==16'h0000) begin
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if (b[15:0]==16'h0000) begin
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$display("Divide by zero");
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$display("Divide by zero");
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int_num <= 8'h00;
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int_num <= 8'h00;
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state <= INT2;
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state <= INT2;
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end
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end
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else
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else
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ld_div32 <= 1'b1;
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ld_div32 <= 1'b1;
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end
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end
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else begin
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else begin
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if (b[7:0]==8'h00) begin
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if (b[7:0]==8'h00) begin
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$display("Divide by zero");
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$display("Divide by zero");
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int_num <= 8'h00;
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int_num <= 8'h00;
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state <= INT2;
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state <= INT2;
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end
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end
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else
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else
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ld_div16 <= 1'b1;
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ld_div16 <= 1'b1;
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end
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end
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end
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end
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DIVIDE2:
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DIVIDE2:
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begin
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begin
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$display("DIVIDE2");
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ld_div32 <= 1'b0;
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ld_div32 <= 1'b0;
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ld_div16 <= 1'b0;
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ld_div16 <= 1'b0;
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state <= DIVIDE2a;
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state <= DIVIDE2a;
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end
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end
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DIVIDE2a:
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DIVIDE2a:
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begin
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begin
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$display("DIVIDE2a");
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if (w & div32_done)
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if (w & div32_done)
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state <= DIVIDE3;
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state <= DIVIDE3;
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else if (!w & div16_done)
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else if (!w & div16_done)
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state <= DIVIDE3;
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state <= DIVIDE3;
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end
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end
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// Assign results to registers
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// Assign results to registers
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// Trap on divider overflow
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// Trap on divider overflow
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DIVIDE3:
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DIVIDE3:
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begin
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begin
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$display("DIVIDE3 state <= IFETCH");
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state <= IFETCH;
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state <= IFETCH;
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if (w) begin
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if (w) begin
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ax <= q32[15:0];
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ax <= q32[15:0];
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dx <= r32[15:0];
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dx <= r32[15:0];
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if (TTT[0]) begin
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if (TTT[0]) begin
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if (q32[31:16]!={16{q32[15]}}) begin
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if (q32[31:16]!={16{q32[15]}}) begin
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$display("DIVIDE Overflow");
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int_num <= 8'h00;
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int_num <= 8'h00;
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state <= INT2;
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state <= INT2;
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end
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end
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end
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end
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else begin
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else begin
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if (q32[31:16]!=16'h0000) begin
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if (q32[31:16]!=16'h0000) begin
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$display("DIVIDE Overflow");
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int_num <= 8'h00;
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int_num <= 8'h00;
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state <= INT2;
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state <= INT2;
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end
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end
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end
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end
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end
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end
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else begin
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else begin
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ax[ 7:0] <= q16[7:0];
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ax[ 7:0] <= q16[7:0];
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ax[15:8] <= r16;
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ax[15:8] <= r16;
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if (TTT[0]) begin
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if (TTT[0]) begin
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if (q16[15:8]!={8{q16[7]}}) begin
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if (q16[15:8]!={8{q16[7]}}) begin
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$display("DIVIDE Overflow");
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int_num <= 8'h00;
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int_num <= 8'h00;
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state <= INT2;
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state <= INT2;
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end
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end
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end
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end
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else begin
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else begin
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if (q16[15:8]!=8'h00) begin
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if (q16[15:8]!=8'h00) begin
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$display("DIVIDE Overflow");
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int_num <= 8'h00;
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int_num <= 8'h00;
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state <= INT2;
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state <= INT2;
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end
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end
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end
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end
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end
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end
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end
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end
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