// ============================================================================
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// ============================================================================
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// EACALC
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// EACALC
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// - calculation of effective address
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// - calculation of effective address
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//
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//
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//
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//
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// (C) 2009-2013 Robert Finch, Stratford
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// (C) 2009-2013 Robert Finch, Stratford
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// robfinch[remove]@finitron.ca
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// robfinch[remove]@finitron.ca
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// Verilog
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// Verilog
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//
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//
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// - the effective address calculation may need to fetch an additional
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// - the effective address calculation may need to fetch an additional
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// eight or sixteen bit displacement value in order to calculate the
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// eight or sixteen bit displacement value in order to calculate the
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// effective address.
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// effective address.
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// - the EA calc only needs to be done once as there is only ever a
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// - the EA calc only needs to be done once as there is only ever a
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// single memory operand address. Once the EA is calculated it is
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// single memory operand address. Once the EA is calculated it is
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// used for both the fetch and the store when memory is the target.
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// used for both the fetch and the store when memory is the target.
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// ============================================================================
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// ============================================================================
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//
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//
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EACALC:
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EACALC:
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// Terminate an outstanding MODRM fetch cycle
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// Terminate an outstanding MODRM fetch cycle
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if (cyc_o) begin
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if (cyc_o) begin
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if (ack_i) begin
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if (ack_i) begin
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`TERMINATE_CODE_READ
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term_code_read();
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mod <= dat_i[7:6];
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mod <= dat_i[7:6];
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rrr <= dat_i[5:3];
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rrr <= dat_i[5:3];
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sreg3 <= dat_i[5:3];
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sreg3 <= dat_i[5:3];
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TTT <= dat_i[5:3];
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TTT <= dat_i[5:3];
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rm <= dat_i[2:0];
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rm <= dat_i[2:0];
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$display("Mod/RM=%b_%b_%b", dat_i[7:6],dat_i[5:3],dat_i[2:0]);
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$display("Mod/RM=%b_%b_%b", dat_i[7:6],dat_i[5:3],dat_i[2:0]);
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end
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end
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end
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end
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else begin
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else begin
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disp16 <= 16'h0000;
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disp16 <= 16'h0000;
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case(mod)
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case(mod)
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2'b00:
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2'b00:
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begin
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begin
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state <= EACALC1;
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state <= EACALC1;
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// ToDo: error on stack state
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// ToDo: error on stack state
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case(rm)
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case(rm)
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3'd0: offset <= bx + si;
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3'd0: offset <= bx + si;
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3'd1: offset <= bx + di;
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3'd1: offset <= bx + di;
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3'd2: offset <= bp + si;
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3'd2: offset <= bp + si;
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3'd3: offset <= bp + di;
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3'd3: offset <= bp + di;
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3'd4: offset <= si;
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3'd4: offset <= si;
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3'd5: offset <= di;
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3'd5: offset <= di;
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3'd6: begin
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3'd6: begin
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state <= EACALC_DISP16;
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state <= EACALC_DISP16;
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offset <= 16'h0000;
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offset <= 16'h0000;
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end
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end
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3'd7: offset <= bx;
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3'd7: offset <= bx;
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endcase
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endcase
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end
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end
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2'b01:
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2'b01:
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begin
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begin
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state <= EACALC_DISP8;
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state <= EACALC_DISP8;
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case(rm)
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case(rm)
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3'd0: offset <= bx + si;
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3'd0: offset <= bx + si;
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3'd1: offset <= bx + di;
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3'd1: offset <= bx + di;
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3'd2: offset <= bp + si;
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3'd2: offset <= bp + si;
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3'd3: offset <= bp + di;
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3'd3: offset <= bp + di;
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3'd4: offset <= si;
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3'd4: offset <= si;
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3'd5: offset <= di;
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3'd5: offset <= di;
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3'd6: offset <= bp;
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3'd6: offset <= bp;
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3'd7: offset <= bx;
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3'd7: offset <= bx;
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endcase
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endcase
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end
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end
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2'b10:
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2'b10:
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begin
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begin
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state <= EACALC_DISP16;
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state <= EACALC_DISP16;
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case(rm)
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case(rm)
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3'd0: offset <= bx + si;
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3'd0: offset <= bx + si;
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3'd1: offset <= bx + di;
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3'd1: offset <= bx + di;
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3'd2: offset <= bp + si;
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3'd2: offset <= bp + si;
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3'd3: offset <= bp + di;
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3'd3: offset <= bp + di;
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3'd4: offset <= si;
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3'd4: offset <= si;
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3'd5: offset <= di;
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3'd5: offset <= di;
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3'd6: offset <= bp;
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3'd6: offset <= bp;
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3'd7: offset <= bx;
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3'd7: offset <= bx;
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endcase
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endcase
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end
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end
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2'b11:
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2'b11:
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begin
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begin
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state <= EXECUTE;
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state <= EXECUTE;
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case(ir)
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case(ir)
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`MOV_I8M:
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`MOV_I8M:
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begin
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begin
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rrr <= rm;
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rrr <= rm;
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if (rrr==3'd0) state <= FETCH_IMM8;
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if (rrr==3'd0) state <= FETCH_IMM8;
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end
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end
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`MOV_I16M:
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`MOV_I16M:
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begin
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begin
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rrr <= rm;
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rrr <= rm;
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if (rrr==3'd0) state <= FETCH_IMM16;
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if (rrr==3'd0) state <= FETCH_IMM16;
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end
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end
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`MOV_S2R:
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`MOV_S2R:
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begin
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begin
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a <= rfso;
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a <= rfso;
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b <= rfso;
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b <= rfso;
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end
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end
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`MOV_R2S:
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`MOV_R2S:
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begin
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begin
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a <= rmo;
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a <= rmo;
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b <= rmo;
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b <= rmo;
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end
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end
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`POP_MEM:
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`POP_MEM:
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begin
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begin
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ir <= 8'h58|rm;
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ir <= 8'h58|rm;
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state <= POP;
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state <= POP;
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end
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end
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`XCHG_MEM:
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`XCHG_MEM:
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begin
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begin
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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res <= rmo;
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res <= rmo;
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b <= rrro;
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b <= rrro;
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end
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end
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// shifts and rotates
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// shifts and rotates
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8'hD0,8'hD1,8'hD2,8'hD3:
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8'hD0,8'hD1,8'hD2,8'hD3:
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begin
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begin
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b <= rmo;
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b <= rmo;
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end
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end
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// The TEST instruction is the only one needing to fetch an immediate value.
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8'hF6,8'hF7:
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8'hF6,8'hF7:
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// 000 = TEST
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// 010 = NOT
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// 011 = NEG
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// 100 = MUL
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// 101 = IMUL
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// 110 = DIV
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// 111 = IDIV
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if (rrr==3'b000) begin // TEST
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a <= rmo;
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state <= w ? FETCH_IMM16 : FETCH_IMM8;
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end
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else
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b <= rmo;
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b <= rmo;
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default:
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default:
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begin
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begin
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if (d) begin
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if (d) begin
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a <= rmo;
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a <= rmo;
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b <= rrro;
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b <= rrro;
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end
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end
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else begin
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else begin
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a <= rrro;
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a <= rrro;
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b <= rmo;
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b <= rmo;
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end
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end
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end
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end
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endcase
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endcase
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hasFetchedData <= 1'b1;
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hasFetchedData <= 1'b1;
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end
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end
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endcase
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endcase
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end
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end
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Fetch 16 bit displacement
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// Fetch 16 bit displacement
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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//
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EACALC_DISP16:
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EACALC_DISP16:
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begin
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begin
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lock_o <= 1'b1;
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lock_o <= 1'b1;
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`INITIATE_CODE_READ
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code_read();
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state <= EACALC_DISP16_ACK;
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state <= EACALC_DISP16_ACK;
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end
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end
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EACALC_DISP16_ACK:
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EACALC_DISP16_ACK:
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if (ack_i) begin
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if (ack_i) begin
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`TERMINATE_CODE_READ
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term_code_read();
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disp16[7:0] <= dat_i;
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disp16[7:0] <= dat_i;
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state <= EACALC_DISP16a;
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state <= EACALC_DISP16a;
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end
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end
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EACALC_DISP16a:
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EACALC_DISP16a:
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begin
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begin
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`INITIATE_CODE_READ
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code_read();
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state <= EACALC_DISP16a_ACK;
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state <= EACALC_DISP16a_ACK;
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end
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end
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EACALC_DISP16a_ACK:
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EACALC_DISP16a_ACK:
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if (ack_i) begin
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if (ack_i) begin
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`TERMINATE_CODE_READ
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term_code_read();
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lock_o <= bus_locked;
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lock_o <= bus_locked;
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disp16[15:8] <= dat_i;
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disp16[15:8] <= dat_i;
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state <= EACALC1;
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state <= EACALC1;
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end
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end
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Fetch 8 bit displacement
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// Fetch 8 bit displacement
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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//
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EACALC_DISP8:
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EACALC_DISP8:
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begin
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begin
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`INITIATE_CODE_READ
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code_read();
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state <= EACALC_DISP8_ACK;
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state <= EACALC_DISP8_ACK;
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end
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end
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EACALC_DISP8_ACK:
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EACALC_DISP8_ACK:
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if (ack_i) begin
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if (ack_i) begin
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`TERMINATE_CODE_READ
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term_code_read();
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disp16 <= {{8{dat_i[7]}},dat_i};
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disp16 <= {{8{dat_i[7]}},dat_i};
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state <= EACALC1;
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state <= EACALC1;
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end
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end
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Add the displacement into the effective address
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// Add the displacement into the effective address
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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//
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EACALC1:
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EACALC1:
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begin
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begin
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casex(ir)
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casex(ir)
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`EXTOP:
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`EXTOP:
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casex(ir2)
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casex(ir2)
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8'h00:
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8'h00:
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begin
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begin
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case(rrr)
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case(rrr)
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3'b010: state <= FETCH_DESC; // LLDT
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3'b010: state <= FETCH_DESC; // LLDT
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3'b011: state <= FETCH_DATA; // LTR
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3'b011: state <= FETCH_DATA; // LTR
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default: state <= FETCH_DATA;
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default: state <= FETCH_DATA;
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endcase
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endcase
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if (w && (offsdisp==16'hFFFF)) begin
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if (w && (offsdisp==16'hFFFF)) begin
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int_num <= 8'h0d;
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int_num <= 8'h0d;
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state <= INT;
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state <= INT2;
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end
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end
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end
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end
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8'h01:
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8'h01:
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begin
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begin
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case(rrr)
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case(rrr)
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3'b010: state <= FETCH_DESC;
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3'b010: state <= FETCH_DESC;
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3'b011: state <= FETCH_DESC;
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3'b011: state <= FETCH_DESC;
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default: state <= FETCH_DATA;
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default: state <= FETCH_DATA;
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endcase
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endcase
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if (w && (offsdisp==16'hFFFF)) begin
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if (w && (offsdisp==16'hFFFF)) begin
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int_num <= 8'h0d;
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int_num <= 8'h0d;
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state <= INT;
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state <= INT2;
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end
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end
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end
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end
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8'h03:
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8'h03:
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if (w && (offsdisp==16'hFFFF)) begin
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if (w && (offsdisp==16'hFFFF)) begin
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int_num <= 8'h0d;
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int_num <= 8'h0d;
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state <= INT;
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state <= INT2;
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end
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end
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else
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else
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state <= FETCH_DATA;
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state <= FETCH_DATA;
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default:
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default:
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if (w && (offsdisp==16'hFFFF)) begin
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if (w && (offsdisp==16'hFFFF)) begin
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int_num <= 8'h0d;
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int_num <= 8'h0d;
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state <= INT;
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state <= INT2;
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end
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end
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else
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else
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state <= FETCH_DATA;
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state <= FETCH_DATA;
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endcase
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endcase
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`MOV_I8M: state <= FETCH_IMM8;
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`MOV_I8M: state <= FETCH_IMM8;
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`MOV_I16M:
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`MOV_I16M:
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if (ip==16'hFFFF) begin
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if (ip==16'hFFFF) begin
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int_num <= 8'h0d;
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int_num <= 8'h0d;
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state <= INT;
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state <= INT2;
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end
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end
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else
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else
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state <= FETCH_IMM16;
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state <= FETCH_IMM16;
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`POP_MEM:
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`POP_MEM:
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begin
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begin
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state <= POP;
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state <= POP;
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end
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end
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`XCHG_MEM:
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`XCHG_MEM:
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begin
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begin
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// bus_locked <= 1'b1;
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// bus_locked <= 1'b1;
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state <= FETCH_DATA;
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state <= FETCH_DATA;
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end
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end
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8'b1000100x: // Move to memory
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8'b1000100x: // Move to memory
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begin
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begin
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$display("EACALC1: state <= STORE_DATA");
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$display("EACALC1: state <= STORE_DATA");
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if (w && (offsdisp==16'hFFFF)) begin
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if (w && (offsdisp==16'hFFFF)) begin
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int_num <= 8'h0d;
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int_num <= 8'h0d;
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state <= INT;
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state <= INT2;
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end
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end
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else begin
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else begin
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res <= rrro;
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res <= rrro;
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state <= STORE_DATA;
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state <= STORE_DATA;
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end
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end
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end
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end
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default:
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default:
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begin
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begin
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$display("EACALC1: state <= FETCH_DATA");
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$display("EACALC1: state <= FETCH_DATA");
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if (w && (offsdisp==16'hFFFF)) begin
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if (w && (offsdisp==16'hFFFF)) begin
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int_num <= 8'h0d;
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int_num <= 8'h0d;
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state <= INT;
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state <= INT2;
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end
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end
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else
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else
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state <= FETCH_DATA;
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state <= FETCH_DATA;
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if (ir==8'hff) begin
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if (ir==8'hff) begin
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case(rrr)
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case(rrr)
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3'b011: state <= CALLF; // CAll FAR indirect
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3'b011: state <= CALLF; // CAll FAR indirect
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3'b101: state <= JUMP_VECTOR1; // JMP FAR indirect
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3'b101: state <= JUMP_VECTOR1; // JMP FAR indirect
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3'b110: begin d <= 1'b0; state <= FETCH_DATA; end// for a push
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3'b110: begin d <= 1'b0; state <= FETCH_DATA; end// for a push
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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end
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end
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endcase
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endcase
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// ea <= ea + disp16;
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// ea <= ea + disp16;
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ea <= {seg_reg,`SEG_SHIFT} + offsdisp; // offsdisp = offset + disp16
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ea <= {seg_reg,`SEG_SHIFT} + offsdisp; // offsdisp = offset + disp16
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end
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end
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