// ============================================================================
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// ============================================================================
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// (C) 2009,2010,2012 Robert Finch
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// (C) 2009,2010,2012 Robert Finch
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// robfinch<remove>@opencores.org
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// robfinch<remove>@opencores.org
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//
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//
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// EXECUTE
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// EXECUTE
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// - execute instruction
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// - execute instruction
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// Verilog
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// Verilog
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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EXECUTE:
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EXECUTE:
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begin
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begin
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casex(ir)
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casex(ir)
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`EXTOP:
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`EXTOP:
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casex(ir2)
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casex(ir2)
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`LxDT: state <= FETCH_DESC;
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`LxDT: state <= FETCH_DESC;
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endcase
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endcase
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`DAA:
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`DAA:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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`ALU_I2R8,`ALU_I2R16,`ADD,`ADD_ALI8,`ADD_AXI16,`ADC,`ADC_ALI8,`ADC_AXI16:
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`ALU_I2R8,`ALU_I2R16,`ADD,`ADD_ALI8,`ADD_AXI16,`ADC,`ADC_ALI8,`ADC_AXI16:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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res <= alu_o;
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res <= alu_o;
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pf <= pres;
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pf <= pres;
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af <= carry (1'b0,a[3],b[3],alu_o[3]);
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af <= carry (1'b0,a[3],b[3],alu_o[3]);
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cf <= carry (1'b0,amsb,bmsb,resn);
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cf <= carry (1'b0,amsb,bmsb,resn);
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vf <= overflow(1'b0,amsb,bmsb,resn);
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vf <= overflow(1'b0,amsb,bmsb,resn);
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sf <= resn;
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sf <= resn;
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zf <= resz;
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zf <= resz;
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end
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end
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`AND,`OR,`XOR,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`AND_AXI16,`OR_AXI16,`XOR_AXI16:
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`AND,`OR,`XOR,`AND_ALI8,`OR_ALI8,`XOR_ALI8,`AND_AXI16,`OR_AXI16,`XOR_AXI16:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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res <= alu_o;
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res <= alu_o;
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pf <= pres;
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pf <= pres;
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cf <= 1'b0;
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cf <= 1'b0;
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vf <= 1'b0;
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vf <= 1'b0;
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sf <= resn;
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sf <= resn;
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zf <= resz;
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zf <= resz;
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end
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end
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`TEST:
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`TEST:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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res <= alu_o;
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res <= alu_o;
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pf <= pres;
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pf <= pres;
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cf <= 1'b0;
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cf <= 1'b0;
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vf <= 1'b0;
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vf <= 1'b0;
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sf <= resn;
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sf <= resn;
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zf <= resz;
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zf <= resz;
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end
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end
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`CMP,`CMP_ALI8,`CMP_AXI16:
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`CMP,`CMP_ALI8,`CMP_AXI16:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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pf <= pres;
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pf <= pres;
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af <= carry (1'b1,a[3],b[3],alu_o[3]);
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af <= carry (1'b1,a[3],b[3],alu_o[3]);
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cf <= carry (1'b1,amsb,bmsb,resn);
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cf <= carry (1'b1,amsb,bmsb,resn);
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vf <= overflow(1'b1,amsb,bmsb,resn);
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vf <= overflow(1'b1,amsb,bmsb,resn);
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sf <= resn;
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sf <= resn;
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zf <= resz;
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zf <= resz;
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end
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end
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`SBB,`SUB,`SBB_ALI8,`SUB_ALI8,`SBB_AXI16,`SUB_AXI16:
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`SBB,`SUB,`SBB_ALI8,`SUB_ALI8,`SBB_AXI16,`SUB_AXI16:
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begin
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begin
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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state <= IFETCH;
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state <= IFETCH;
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res <= alu_o;
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res <= alu_o;
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pf <= pres;
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pf <= pres;
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af <= carry (1'b1,a[3],b[3],alu_o[3]);
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af <= carry (1'b1,a[3],b[3],alu_o[3]);
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cf <= carry (1'b1,amsb,bmsb,resn);
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cf <= carry (1'b1,amsb,bmsb,resn);
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vf <= overflow(1'b1,amsb,bmsb,resn);
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vf <= overflow(1'b1,amsb,bmsb,resn);
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sf <= resn;
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sf <= resn;
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zf <= resz;
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zf <= resz;
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end
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end
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8'hF6,8'hF7:
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8'hF6,8'hF7:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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res <= alu_o;
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res <= alu_o;
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case(TTT)
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case(TTT)
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3'd0: // TEST
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3'd0: // TEST
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begin
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begin
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pf <= pres;
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pf <= pres;
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cf <= 1'b0;
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cf <= 1'b0;
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vf <= 1'b0;
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vf <= 1'b0;
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sf <= resn;
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sf <= resn;
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zf <= resz;
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zf <= resz;
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end
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end
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3'd2: // NOT
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3'd2: // NOT
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begin
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begin
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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end
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end
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3'd3: // NEG
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3'd3: // NEG
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begin
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begin
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pf <= pres;
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pf <= pres;
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af <= carry (1'b1,1'b0,b[3],alu_o[3]);
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af <= carry (1'b1,1'b0,b[3],alu_o[3]);
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cf <= carry (1'b1,1'b0,bmsb,resn);
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cf <= carry (1'b1,1'b0,bmsb,resn);
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vf <= overflow(1'b1,1'b0,bmsb,resn);
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vf <= overflow(1'b1,1'b0,bmsb,resn);
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sf <= resn;
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sf <= resn;
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zf <= resz;
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zf <= resz;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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end
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end
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// Normally only a single register update is required, however with
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// Normally only a single register update is required, however with
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// multiply word both AX and DX need to be updated. So we bypass the
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// multiply word both AX and DX need to be updated. So we bypass the
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// regular update here.
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// regular update here.
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3'd4:
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3'd4:
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begin
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begin
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if (w) begin
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if (w) begin
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ax <= p32[15:0];
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ax <= p32[15:0];
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dx <= p32[31:16];
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dx <= p32[31:16];
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cf <= p32[31:16]!=16'd0;
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cf <= p32[31:16]!=16'd0;
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vf <= p32[31:16]!=16'd0;
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vf <= p32[31:16]!=16'd0;
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end
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end
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else begin
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else begin
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ax <= p16;
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ax <= p16;
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cf <= p16[15:8]!=8'd0;
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cf <= p16[15:8]!=8'd0;
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vf <= p16[15:8]!=8'd0;
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vf <= p16[15:8]!=8'd0;
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end
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end
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end
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end
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3'd5:
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3'd5:
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begin
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begin
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if (w) begin
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if (w) begin
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ax <= wp[15:0];
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ax <= wp[15:0];
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dx <= wp[31:16];
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dx <= wp[31:16];
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cf <= p32[31:16]!=16'd0;
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cf <= p32[31:16]!=16'd0;
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vf <= p32[31:16]!=16'd0;
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vf <= p32[31:16]!=16'd0;
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end
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end
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else begin
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else begin
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ax <= p;
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ax <= p;
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cf <= p[15:8]!=8'd0;
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cf <= p[15:8]!=8'd0;
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vf <= p[15:8]!=8'd0;
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vf <= p[15:8]!=8'd0;
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end
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end
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end
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end
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3'd6,3'd7:
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3'd6,3'd7:
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begin
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begin
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$display("state <= DIVIDE1");
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$display("state <= DIVIDE1");
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state <= DIVIDE1;
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state <= DIVIDE1;
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end
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end
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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`INC_REG:
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`INC_REG:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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w <= 1'b1;
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w <= 1'b1;
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res <= alu_o;
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res <= alu_o;
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pf <= pres;
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pf <= pres;
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af <= carry (1'b0,a[3],b[3],alu_o[3]);
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af <= carry (1'b0,a[3],b[3],alu_o[3]);
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vf <= overflow(1'b0,a[15],b[15],resnw);
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vf <= overflow(1'b0,a[15],b[15],resnw);
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sf <= resnw;
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sf <= resnw;
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zf <= reszw;
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zf <= reszw;
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end
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end
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`DEC_REG:
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`DEC_REG:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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w <= 1'b1;
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w <= 1'b1;
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res <= alu_o;
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res <= alu_o;
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pf <= pres;
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pf <= pres;
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af <= carry (1'b1,a[3],b[3],alu_o[3]);
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af <= carry (1'b1,a[3],b[3],alu_o[3]);
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vf <= overflow(1'b1,a[15],b[15],resnw);
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vf <= overflow(1'b1,a[15],b[15],resnw);
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sf <= resnw;
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sf <= resnw;
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zf <= reszw;
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zf <= reszw;
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end
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end
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`IMUL:
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// `IMUL:
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begin
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// begin
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state <= IFETCH;
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// state <= IFETCH;
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wrregs <= 1'b1;
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// wrregs <= 1'b1;
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w <= 1'b1;
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// w <= 1'b1;
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rrr <= 3'd0;
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// rrr <= 3'd0;
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res <= alu_o;
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// res <= alu_o;
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if (w) begin
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// if (w) begin
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cf <= wp[31:16]!={16{resnw}};
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// cf <= wp[31:16]!={16{resnw}};
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vf <= wp[31:16]!={16{resnw}};
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// vf <= wp[31:16]!={16{resnw}};
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dx <= wp[31:16];
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// dx <= wp[31:16];
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end
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// end
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else begin
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// else begin
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cf <= ah!={8{resnb}};
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// cf <= ah!={8{resnb}};
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vf <= ah!={8{resnb}};
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// vf <= ah!={8{resnb}};
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end
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// end
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end
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// end
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Memory Operations
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// Memory Operations
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// registers not allowed on LEA
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// registers not allowed on LEA
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// invalid opcode
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// invalid opcode
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//
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//
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`LEA:
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`LEA:
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begin
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begin
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w <= 1'b1;
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w <= 1'b1;
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res <= ea;
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res <= ea;
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if (mod==2'b11) begin
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if (mod==2'b11) begin
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int_num <= 8'h06;
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int_num <= 8'h06;
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state <= INT;
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state <= INT;
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end
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end
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else begin
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else begin
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state <= IFETCH;
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state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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end
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end
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end
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end
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`LDS:
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`LDS:
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begin
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begin
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wrsregs <= 1'b1;
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wrsregs <= 1'b1;
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res <= alu_o;
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res <= alu_o;
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rrr <= 3'd3;
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rrr <= 3'd3;
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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`LES:
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`LES:
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begin
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begin
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wrsregs <= 1'b1;
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wrsregs <= 1'b1;
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res <= alu_o;
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res <= alu_o;
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rrr <= 3'd0;
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rrr <= 3'd0;
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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`MOV_RR8,`MOV_RR16,
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`MOV_RR8,`MOV_RR16,
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`MOV_MR,
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`MOV_MR,
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`MOV_M2AL,`MOV_M2AX,
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`MOV_M2AL,`MOV_M2AX,
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`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
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`MOV_I2AL,`MOV_I2DL,`MOV_I2CL,`MOV_I2BL,`MOV_I2AH,`MOV_I2DH,`MOV_I2CH,`MOV_I2BH,
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`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
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`MOV_I2AX,`MOV_I2DX,`MOV_I2CX,`MOV_I2BX,`MOV_I2SP,`MOV_I2BP,`MOV_I2SI,`MOV_I2DI:
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begin
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begin
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state <= IFETCH;
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state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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res <= alu_o;
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res <= alu_o;
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end
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end
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`XCHG_MEM:
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`XCHG_MEM:
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begin
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begin
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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if (mod==2'b11) rrr <= rm;
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if (mod==2'b11) rrr <= rm;
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res <= alu_o;
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res <= alu_o;
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b <= rrro;
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b <= rrro;
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state <= mod==2'b11 ? IFETCH : XCHG_MEM;
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state <= mod==2'b11 ? IFETCH : XCHG_MEM;
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end
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end
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`MOV_I8M,`MOV_I16M:
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`MOV_I8M,`MOV_I16M:
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begin
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begin
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res <= alu_o;
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res <= alu_o;
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state <= rrr==3'd0 ? STORE_DATA : INVALID_OPCODE;
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state <= rrr==3'd0 ? STORE_DATA : INVALID_OPCODE;
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end
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end
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`MOV_S2R:
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`MOV_S2R:
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begin
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begin
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w <= 1'b1;
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w <= 1'b1;
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rrr <= rm;
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rrr <= rm;
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res <= b;
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res <= b;
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if (mod==2'b11) begin
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if (mod==2'b11) begin
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state <= IFETCH;
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state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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end
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end
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else
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else
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state <= STORE_DATA;
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state <= STORE_DATA;
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end
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end
|
`MOV_R2S:
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`MOV_R2S:
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begin
|
begin
|
wrsregs <= 1'b1;
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wrsregs <= 1'b1;
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res <= alu_o;
|
res <= alu_o;
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state <= IFETCH;
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state <= IFETCH;
|
end
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end
|
|
|
`LODSB:
|
`LODSB:
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begin
|
begin
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state <= IFETCH;
|
state <= IFETCH;
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wrregs <= 1'b1;
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wrregs <= 1'b1;
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w <= 1'b0;
|
w <= 1'b0;
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rrr <= 3'd0;
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rrr <= 3'd0;
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res <= a[7:0];
|
res <= a[7:0];
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if ( df) si <= si_dec;
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if ( df) si <= si_dec;
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if (!df) si <= si_inc;
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if (!df) si <= si_inc;
|
end
|
end
|
`LODSW:
|
`LODSW:
|
begin
|
begin
|
state <= IFETCH;
|
state <= IFETCH;
|
wrregs <= 1'b1;
|
wrregs <= 1'b1;
|
w <= 1'b1;
|
w <= 1'b1;
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rrr <= 3'd0;
|
rrr <= 3'd0;
|
res <= a;
|
res <= a;
|
if ( df) si <= si - 16'd2;
|
if ( df) si <= si - 16'd2;
|
if (!df) si <= si + 16'd2;
|
if (!df) si <= si + 16'd2;
|
end
|
end
|
|
|
8'hD0,8'hD1,8'hD2,8'hD3,8'hC0,8'hC1:
|
8'hD0,8'hD1,8'hD2,8'hD3,8'hC0,8'hC1:
|
begin
|
begin
|
state <= IFETCH;
|
state <= IFETCH;
|
wrregs <= 1'b1;
|
wrregs <= 1'b1;
|
rrr <= rm;
|
rrr <= rm;
|
if (w)
|
if (w)
|
case(rrr)
|
case(rrr)
|
3'b000: // ROL
|
3'b000: // ROL
|
begin
|
begin
|
res <= shlo[15:0]|shlo[31:16];
|
res <= shlo[15:0]|shlo[31:16];
|
cf <= bmsb;
|
cf <= bmsb;
|
vf <= bmsb^b[14];
|
vf <= bmsb^b[14];
|
end
|
end
|
3'b001: // ROR
|
3'b001: // ROR
|
begin
|
begin
|
res <= shruo[15:0]|shruo[31:16];
|
res <= shruo[15:0]|shruo[31:16];
|
cf <= b[0];
|
cf <= b[0];
|
vf <= cf^b[15];
|
vf <= cf^b[15];
|
end
|
end
|
3'b010: // RCL
|
3'b010: // RCL
|
begin
|
begin
|
res <= shlco[16:1]|shlco[32:17];
|
res <= shlco[16:1]|shlco[32:17];
|
cf <= b[15];
|
cf <= b[15];
|
vf <= b[15]^b[14];
|
vf <= b[15]^b[14];
|
end
|
end
|
3'b011: // RCR
|
3'b011: // RCR
|
begin
|
begin
|
res <= shrcuo[15:0]|shrcuo[31:16];
|
res <= shrcuo[15:0]|shrcuo[31:16];
|
cf <= b[0];
|
cf <= b[0];
|
vf <= cf^b[15];
|
vf <= cf^b[15];
|
end
|
end
|
3'b100: // SHL
|
3'b100: // SHL
|
begin
|
begin
|
res <= shlo[15:0];
|
res <= shlo[15:0];
|
cf <= shlo[16];
|
cf <= shlo[16];
|
vf <= b[15]^b[14];
|
vf <= b[15]^b[14];
|
end
|
end
|
3'b101: // SHR
|
3'b101: // SHR
|
begin
|
begin
|
res <= shruo[31:16];
|
res <= shruo[31:16];
|
cf <= shruo[15];
|
cf <= shruo[15];
|
vf <= b[15];
|
vf <= b[15];
|
end
|
end
|
3'b111: // SAR
|
3'b111: // SAR
|
begin
|
begin
|
res <= shro;
|
res <= shro;
|
cf <= b[0];
|
cf <= b[0];
|
vf <= 1'b0;
|
vf <= 1'b0;
|
end
|
end
|
endcase
|
endcase
|
else
|
else
|
case(rrr)
|
case(rrr)
|
3'b000: // ROL
|
3'b000: // ROL
|
begin
|
begin
|
res <= shlo8[7:0]|shlo8[15:8];
|
res <= shlo8[7:0]|shlo8[15:8];
|
cf <= b[7];
|
cf <= b[7];
|
vf <= b[7]^b[6];
|
vf <= b[7]^b[6];
|
end
|
end
|
3'b001: // ROR
|
3'b001: // ROR
|
begin
|
begin
|
res <= shruo8[15:8]|shruo8[7:0];
|
res <= shruo8[15:8]|shruo8[7:0];
|
cf <= b[0];
|
cf <= b[0];
|
vf <= cf^b[7];
|
vf <= cf^b[7];
|
end
|
end
|
3'b010: // RCL
|
3'b010: // RCL
|
begin
|
begin
|
res <= shlco8[8:1]|shlco8[16:9];
|
res <= shlco8[8:1]|shlco8[16:9];
|
cf <= b[7];
|
cf <= b[7];
|
vf <= b[7]^b[6];
|
vf <= b[7]^b[6];
|
end
|
end
|
3'b011: // RCR
|
3'b011: // RCR
|
begin
|
begin
|
res <= shrcuo8[15:8]|shrcuo8[7:0];
|
res <= shrcuo8[15:8]|shrcuo8[7:0];
|
cf <= b[0];
|
cf <= b[0];
|
vf <= cf^b[7];
|
vf <= cf^b[7];
|
end
|
end
|
3'b100: // SHL
|
3'b100: // SHL
|
begin
|
begin
|
res <= shlo8[7:0];
|
res <= shlo8[7:0];
|
cf <= shlo8[8];
|
cf <= shlo8[8];
|
vf <= b[7]^b[6];
|
vf <= b[7]^b[6];
|
end
|
end
|
3'b101: // SHR
|
3'b101: // SHR
|
begin
|
begin
|
res <= shruo8[15:8];
|
res <= shruo8[15:8];
|
cf <= shruo8[7];
|
cf <= shruo8[7];
|
vf <= b[7];
|
vf <= b[7];
|
end
|
end
|
3'b111: // SAR
|
3'b111: // SAR
|
begin
|
begin
|
res <= shro8;
|
res <= shro8;
|
cf <= b[0];
|
cf <= b[0];
|
vf <= 1'b0;
|
vf <= 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
`GRPFF:
|
`GRPFF:
|
begin
|
begin
|
case(rrr)
|
case(rrr)
|
3'b000: // INC
|
3'b000: // INC
|
begin
|
begin
|
state <= IFETCH;
|
state <= IFETCH;
|
wrregs <= 1'b1;
|
wrregs <= 1'b1;
|
af <= carry (1'b0,a[3],b[3],alu_o[3]);
|
af <= carry (1'b0,a[3],b[3],alu_o[3]);
|
vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
|
vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
|
w <= 1'b1;
|
w <= 1'b1;
|
res <= alu_o;
|
res <= alu_o;
|
rrr <= rm;
|
rrr <= rm;
|
pf <= pres;
|
pf <= pres;
|
sf <= resnw;
|
sf <= resnw;
|
zf <= reszw;
|
zf <= reszw;
|
end
|
end
|
3'b001: // DEC
|
3'b001: // DEC
|
begin
|
begin
|
state <= IFETCH;
|
state <= IFETCH;
|
wrregs <= 1'b1;
|
wrregs <= 1'b1;
|
af <= carry (1'b1,a[3],b[3],alu_o[3]);
|
af <= carry (1'b1,a[3],b[3],alu_o[3]);
|
vf <= overflow(1'b1,a[15],b[15],alu_o[15]);
|
vf <= overflow(1'b1,a[15],b[15],alu_o[15]);
|
w <= 1'b1;
|
w <= 1'b1;
|
res <= alu_o;
|
res <= alu_o;
|
rrr <= rm;
|
rrr <= rm;
|
pf <= pres;
|
pf <= pres;
|
sf <= resnw;
|
sf <= resnw;
|
zf <= reszw;
|
zf <= reszw;
|
end
|
end
|
3'b010: begin sp <= sp_dec; state <= CALL_IN; end
|
3'b010: begin sp <= sp_dec; state <= CALL_IN; end
|
// These two should not be reachable here, as they would
|
// These two should not be reachable here, as they would
|
// be trapped by the EACALC.
|
// be trapped by the EACALC.
|
3'b011: state <= CALL_FIN; // CALL FAR indirect
|
3'b011: state <= CALL_FIN; // CALL FAR indirect
|
3'b101: // JMP FAR indirect
|
3'b101: // JMP FAR indirect
|
begin
|
begin
|
ip <= offset;
|
ip <= offset;
|
cs <= selector;
|
cs <= selector;
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
3'b110: begin sp <= sp_dec; state <= PUSH; end
|
3'b110: begin sp <= sp_dec; state <= PUSH; end
|
default:
|
default:
|
begin
|
begin
|
af <= carry (1'b0,a[3],b[3],alu_o[3]);
|
af <= carry (1'b0,a[3],b[3],alu_o[3]);
|
vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
|
vf <= overflow(1'b0,a[15],b[15],alu_o[15]);
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
default:
|
default:
|
state <= IFETCH;
|
state <= IFETCH;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
