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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [IFETCH.v] - Diff between revs 2 and 4

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//=============================================================================
//=============================================================================
//  Fetch instruction
//  Fetch instruction
//
//
//
//
//  (C) 2009,2010,2012 Robert Finch, Stratford
//  (C) 2009,2010,2012 Robert Finch, Stratford
//  robfinch<remove>@opencores.org
//  robfinch<remove>@opencores.org
//
//
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
// (at your option) any later version.                                      
//                                                                          
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
// GNU General Public License for more details.                             
//                                                                          
//                                                                          
// You should have received a copy of the GNU General Public License        
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
//
//
//
// - All of the state control flags are reset.
// - All of the state control flags are reset.
//
//
// - If the current instruction is a prefix then we want to shift it
// - If the current instruction is a prefix then we want to shift it
//   into the prefix buffer before fetching the instruction. Also
//   into the prefix buffer before fetching the instruction. Also
//   interrupts are blocked if the previous instruction is a prefix.
//   interrupts are blocked if the previous instruction is a prefix.
//
//
// - two bytes are fetched at once if the instruction is aligned on
// - two bytes are fetched at once if the instruction is aligned on
//   an even address. This saves a bus cycle most of the time.
//   an even address. This saves a bus cycle most of the time.
//
//
// ToDo:
// ToDo:
// - add an exception if more than two prefixes are present.
// - add an exception if more than two prefixes are present.
//
//
//=============================================================================
//=============================================================================
//
//
IFETCH:
IFETCH:
        begin
        begin
                // Reset all instruction processing flags at instruction fetch
                // Reset all instruction processing flags at instruction fetch
                cyc_type <= `CT_PASSIVE;
                cyc_type <= `CT_PASSIVE;
                mod <= 2'd0;
                mod <= 2'd0;
                rrr <= 3'd0;
                rrr <= 3'd0;
                rm <= 3'd0;
                rm <= 3'd0;
                sxi <= 1'b0;
                sxi <= 1'b0;
                hasFetchedModrm <= 1'b0;
                hasFetchedModrm <= 1'b0;
                hasFetchedDisp8 <= 1'b0;
                hasFetchedDisp8 <= 1'b0;
                hasFetchedDisp16 <= 1'b0;
                hasFetchedDisp16 <= 1'b0;
                hasFetchedVector <= 1'b0;
                hasFetchedVector <= 1'b0;
                hasStoredData <= 1'b0;
                hasStoredData <= 1'b0;
                hasFetchedData <= 1'b0;
                hasFetchedData <= 1'b0;
                data16 <= 16'h0000;
                data16 <= 16'h0000;
                cnt <= 7'd0;
                cnt <= 7'd0;
//              if (prefix1!=8'h00 && prefix2 !=8'h00 && is_prefix)
//              if (prefix1!=8'h00 && prefix2 !=8'h00 && is_prefix)
//                      state <= TRIPLE_PREFIX;
//                      state <= TRIPLE_PREFIX;
                if (is_prefix) begin
                if (is_prefix) begin
                        prefix1 <= ir;
                        prefix1 <= ir;
                        prefix2 <= prefix1;
                        prefix2 <= prefix1;
                end
                end
                else begin
                else begin
                        prefix1 <= 8'h00;
                        prefix1 <= 8'h00;
                        prefix2 <= 8'h00;
                        prefix2 <= 8'h00;
                end
                end
 
 
        if (pe_nmi & checkForInts) begin
        if (pe_nmi & checkForInts) begin
            state <= INT2;
            state <= INT2;
            rst_nmi <= 1'b1;
            rst_nmi <= 1'b1;
            int_num <= 8'h02;
            int_num <= 8'h02;
            ir <= `NOP;
            ir <= `NOP;
        end
        end
        else if (irq_i & ie & checkForInts) begin
        else if (irq_i & ie & checkForInts) begin
            state <= INTA0;
            state <= INTA0;
            ir <= `NOP;
            ir <= `NOP;
        end
        end
        else if (ir==`HLT) begin
        else if (ir==`HLT) begin
                        state <= IFETCH;
                        state <= IFETCH;
                cyc_type <= `CT_HALT;
                cyc_type <= `CT_HALT;
        end
        end
        else begin
        else begin
                        state <= IFETCH_ACK;
                        state <= IFETCH_ACK;
                        `INITIATE_CODE_READ
                        `INITIATE_CODE_READ
                        inta_o <= 1'b0;
                        inta_o <= 1'b0;
                        mio_o <= 1'b1;
                        mio_o <= 1'b1;
                        lock_o <= bus_locked;
                        lock_o <= bus_locked;
                end
                end
        end
        end
 
 
IFETCH_ACK:
IFETCH_ACK:
        if (ack_i) begin
        if (ack_i) begin
                `TERMINATE_CODE_READ
                `TERMINATE_CODE_READ
                ir <= dat_i;
                ir <= dat_i;
                $display("IR: %h",dat_i);
                $display("IR: %h",dat_i);
                if (!hasPrefix)
                if (!hasPrefix)
                        ir_ip <= ip;
                        ir_ip <= ip;
//              ir_ip <= dat_i;
//              ir_ip <= dat_i;
                w <= dat_i[0];
                w <= dat_i[0];
                d <= dat_i[1];
                d <= dat_i[1];
 
                v <= dat_i[1];
                sxi <= dat_i[1];
                sxi <= dat_i[1];
                sreg2 <= dat_i[4:3];
                sreg2 <= dat_i[4:3];
                sreg3 <= {1'b0,dat_i[4:3]};
                sreg3 <= {1'b0,dat_i[4:3]};
                ir2 <= 8'h00;
                ir2 <= 8'h00;
                state <= DECODE;
                state <= DECODE;
        end
        end
 
 
// Fetch extended opcode
// Fetch extended opcode
//
//
XI_FETCH:
XI_FETCH:
        begin
        begin
                `INITIATE_CODE_READ
                `INITIATE_CODE_READ
                state <= XI_FETCH_ACK;
                state <= XI_FETCH_ACK;
        end
        end
 
 
XI_FETCH_ACK:
XI_FETCH_ACK:
        if (ack_i) begin
        if (ack_i) begin
                `TERMINATE_CODE_READ
                `TERMINATE_CODE_READ
                ir2 <= dat_i;
                ir2 <= dat_i;
                state <= DECODER2;
                state <= DECODER2;
        end
        end
 
 

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