//=============================================================================
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//=============================================================================
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// Fetch instruction
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// Fetch instruction
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//
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//
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//
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//
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// (C) 2009,2010,2012 Robert Finch, Stratford
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// (C) 2009,2010,2012,2013 Robert Finch, Stratford
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// robfinch<remove>@opencores.org
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// robfinch<remove>@finitron.ca
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// - All of the state control flags are reset.
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// - All of the state control flags are reset.
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//
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//
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// - If the current instruction is a prefix then we want to shift it
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// - If the current instruction is a prefix then we want to shift it
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// into the prefix buffer before fetching the instruction. Also
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// into the prefix buffer before fetching the instruction. Also
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// interrupts are blocked if the previous instruction is a prefix.
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// interrupts are blocked if the previous instruction is a prefix.
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//
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//
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// - two bytes are fetched at once if the instruction is aligned on
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// - two bytes are fetched at once if the instruction is aligned on
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// an even address. This saves a bus cycle most of the time.
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// an even address. This saves a bus cycle most of the time.
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//
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//
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// ToDo:
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// ToDo:
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// - add an exception if more than two prefixes are present.
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// - add an exception if more than two prefixes are present.
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//
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//
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//=============================================================================
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//=============================================================================
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//
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//
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IFETCH:
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IFETCH:
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begin
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begin
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$display("\r\n******************************************************");
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$display("time: %d", $time);
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$display("CSIP: %h", csip);
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$display("CSIP: %h", csip);
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$display("AX=%h SI=%h", ax, si);
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$display("BX=%h DI=%h", bx, di);
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$display("CX=%h BP=%h", cx, bp);
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$display("DX=%h SP=%h", dx, sp);
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// Reset all instruction processing flags at instruction fetch
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// Reset all instruction processing flags at instruction fetch
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cyc_type <= `CT_PASSIVE;
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cyc_type <= `CT_PASSIVE;
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mod <= 2'd0;
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mod <= 2'd0;
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rrr <= 3'd0;
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rrr <= 3'd0;
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rm <= 3'd0;
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rm <= 3'd0;
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sxi <= 1'b0;
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sxi <= 1'b0;
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hasFetchedModrm <= 1'b0;
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hasFetchedModrm <= 1'b0;
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hasFetchedDisp8 <= 1'b0;
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hasFetchedDisp8 <= 1'b0;
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hasFetchedDisp16 <= 1'b0;
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hasFetchedDisp16 <= 1'b0;
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hasFetchedVector <= 1'b0;
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hasFetchedVector <= 1'b0;
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hasStoredData <= 1'b0;
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hasStoredData <= 1'b0;
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hasFetchedData <= 1'b0;
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hasFetchedData <= 1'b0;
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data16 <= 16'h0000;
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data16 <= 16'h0000;
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cnt <= 7'd0;
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cnt <= 7'd0;
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// if (prefix1!=8'h00 && prefix2 !=8'h00 && is_prefix)
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// if (prefix1!=8'h00 && prefix2 !=8'h00 && is_prefix)
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// state <= TRIPLE_PREFIX;
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// state <= TRIPLE_PREFIX;
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if (is_prefix) begin
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if (is_prefix) begin
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prefix1 <= ir;
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prefix1 <= ir;
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prefix2 <= prefix1;
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prefix2 <= prefix1;
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end
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end
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else begin
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else begin
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prefix1 <= 8'h00;
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prefix1 <= 8'h00;
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prefix2 <= 8'h00;
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prefix2 <= 8'h00;
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end
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end
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if (pe_nmi & checkForInts) begin
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if (pe_nmi & checkForInts) begin
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state <= INT2;
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state <= INT2;
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rst_nmi <= 1'b1;
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rst_nmi <= 1'b1;
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int_num <= 8'h02;
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int_num <= 8'h02;
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ir <= `NOP;
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ir <= `NOP;
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end
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end
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else if (irq_i & ie & checkForInts) begin
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else if (irq_i & ie & checkForInts) begin
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state <= INTA0;
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state <= INTA0;
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ir <= `NOP;
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ir <= `NOP;
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end
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end
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else if (ir==`HLT) begin
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else if (ir==`HLT) begin
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state <= IFETCH;
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state <= IFETCH;
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cyc_type <= `CT_HALT;
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cyc_type <= `CT_HALT;
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end
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end
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else begin
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else begin
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state <= IFETCH_ACK;
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state <= IFETCH_ACK;
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read(`CT_CODE,csip);
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read(`CT_CODE,csip);
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inta_o <= 1'b0;
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inta_o <= 1'b0;
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mio_o <= 1'b1;
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mio_o <= 1'b1;
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lock_o <= bus_locked;
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lock_o <= bus_locked;
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end
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end
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end
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end
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IFETCH_ACK:
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IFETCH_ACK:
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if (ack_i) begin
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if (ack_i) begin
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nack_ir();
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nack_ir();
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$display("IR: %h",dat_i);
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$display("CSIP: %h IR: %h",csip,dat_i);
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if (!hasPrefix)
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if (!hasPrefix)
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ir_ip <= ip;
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ir_ip <= ip;
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// ir_ip <= dat_i;
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// ir_ip <= dat_i;
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w <= dat_i[0];
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w <= dat_i[0];
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d <= dat_i[1];
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d <= dat_i[1];
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v <= dat_i[1];
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v <= dat_i[1];
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sxi <= dat_i[1];
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sxi <= dat_i[1];
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sreg2 <= dat_i[4:3];
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sreg2 <= dat_i[4:3];
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sreg3 <= {1'b0,dat_i[4:3]};
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sreg3 <= {1'b0,dat_i[4:3]};
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ir2 <= 8'h00;
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ir2 <= 8'h00;
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state <= DECODE;
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state <= DECODE;
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end
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end
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// Fetch extended opcode
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// Fetch extended opcode
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//
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//
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XI_FETCH:
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XI_FETCH:
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begin
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begin
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read(`CT_CODE,csip);
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read(`CT_CODE,csip);
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state <= XI_FETCH_ACK;
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state <= XI_FETCH_ACK;
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end
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end
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XI_FETCH_ACK:
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XI_FETCH_ACK:
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if (ack_i) begin
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if (ack_i) begin
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nack_ir2();
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nack_ir2();
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state <= DECODER2;
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state <= DECODER2;
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end
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end
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