//=============================================================================
|
//=============================================================================
|
// LODS
|
// LODS
|
// Fetch string data from memory.
|
// Fetch string data from memory.
|
//
|
//
|
//
|
//
|
// 2009,2010 Robert Finch
|
// 2009,2010,2013 Robert Finch
|
// Stratford
|
// Stratford
|
// robfinch<remove>@opencores.org
|
// robfinch<remove>@finitron.ca
|
//
|
//
|
//
|
//
|
// This source file is free software: you can redistribute it and/or modify
|
// This source file is free software: you can redistribute it and/or modify
|
// it under the terms of the GNU Lesser General Public License as published
|
// it under the terms of the GNU Lesser General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or
|
// by the Free Software Foundation, either version 3 of the License, or
|
// (at your option) any later version.
|
// (at your option) any later version.
|
//
|
//
|
// This source file is distributed in the hope that it will be useful,
|
// This source file is distributed in the hope that it will be useful,
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// GNU General Public License for more details.
|
// GNU General Public License for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
//=============================================================================
|
//=============================================================================
|
//
|
//
|
LODS:
|
LODS:
|
if (w && (si==16'hFFFF) && !df) begin
|
if (w && (si==16'hFFFF) && !df) begin
|
ir <= `NOP;
|
ir <= `NOP;
|
int_num <= 8'd13;
|
int_num <= 8'd13;
|
state <= INT1;
|
state <= INT2;
|
end
|
end
|
else begin
|
else begin
|
cyc_type <= `CT_RDMEM;
|
cyc_type <= `CT_RDMEM;
|
lock_o <= w;
|
lock_o <= w;
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b0;
|
we_o <= 1'b0;
|
adr_o <= {seg_reg,`SEG_SHIFT} + si;
|
adr_o <= {seg_reg,`SEG_SHIFT} + si;
|
state <= LODS_NACK;
|
state <= LODS_NACK;
|
end
|
end
|
LODS_NACK:
|
LODS_NACK:
|
if (ack_i) begin
|
if (ack_i) begin
|
cyc_type <= `CT_PASSIVE;
|
cyc_type <= `CT_PASSIVE;
|
lock_o <= w;
|
lock_o <= w;
|
cyc_o <= w;
|
cyc_o <= w;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
if (df) begin
|
if (df) begin
|
si <= si_dec;
|
si <= si_dec;
|
if (w)
|
if (w)
|
b[15:8] <= dat_i;
|
b[15:8] <= dat_i;
|
else begin
|
else begin
|
b[ 7:0] <= dat_i;
|
b[ 7:0] <= dat_i;
|
b[15:8] <= {8{dat_i[7]}};
|
b[15:8] <= {8{dat_i[7]}};
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
si <= si_inc;
|
si <= si_inc;
|
b[ 7:0] <= dat_i;
|
b[ 7:0] <= dat_i;
|
b[15:8] <= {8{dat_i[7]}};
|
b[15:8] <= {8{dat_i[7]}};
|
end
|
end
|
state <= w ? LODS1 : EXECUTE;
|
state <= w ? LODS1 : EXECUTE;
|
end
|
end
|
|
|
LODS1:
|
LODS1:
|
begin
|
begin
|
cyc_type <= `CT_RDMEM;
|
cyc_type <= `CT_RDMEM;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
adr_o <= {seg_reg,`SEG_SHIFT} + si;
|
adr_o <= {seg_reg,`SEG_SHIFT} + si;
|
state <= LODS1_NACK;
|
state <= LODS1_NACK;
|
end
|
end
|
LODS1_NACK:
|
LODS1_NACK:
|
if (ack_i) begin
|
if (ack_i) begin
|
cyc_type <= `CT_PASSIVE;
|
cyc_type <= `CT_PASSIVE;
|
lock_o <= 1'b0;
|
lock_o <= 1'b0;
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
if (df) begin
|
if (df) begin
|
si <= si_dec;
|
si <= si_dec;
|
b[7:0] <= dat_i;
|
b[7:0] <= dat_i;
|
end
|
end
|
else begin
|
else begin
|
si <= si_inc;
|
si <= si_inc;
|
b[15:8] <= dat_i;
|
b[15:8] <= dat_i;
|
end
|
end
|
state <= EXECUTE;
|
state <= EXECUTE;
|
end
|
end
|
|
|
|
|
