// ============================================================================
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// ============================================================================
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// (C) 2007,2011,2013 Robert Finch
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// (C) 2007,2011,2013,2015 Robert Finch
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// All rights reserved.
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// All rights reserved.
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// robfinch@<remove>finitron.ca
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// robfinch@<remove>finitron.ca
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//
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//
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// rtfSimpleUart.v
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// rtfSimpleUart.v
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// Basic uart with baud rate generator based on a harmonic
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// Basic uart with baud rate generator based on a harmonic
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// frequency synthesizer.
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// frequency synthesizer.
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//
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//
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the <organization> nor the
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// * Neither the name of the <organization> nor the
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// names of its contributors may be used to endorse or promote products
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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// derived from this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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//
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//
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// To use:
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// To use:
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//
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//
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// Set the pClkFreq parameter to the frequency of the system
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// Set the pClkFreq parameter to the frequency of the system
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// clock (clk_i). This can be done when the core is instanced.
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// clock (clk_i). This can be done when the core is instanced.
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//
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//
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// 1) set the baud rate value in the clock multiplier
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// 1) set the baud rate value in the clock multiplier
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// registers (CM1,2,3). A default multiplier value may
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// registers (CM1,2,3). A default multiplier value may
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// be specified using the pClkMul parameter, so it
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// be specified using the pClkMul parameter, so it
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// doesn't have to be programmed at run time. (Note the
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// doesn't have to be programmed at run time. (Note the
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// pBaud parameter may also be set, but it doesn't work
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// pBaud parameter may also be set, but it doesn't work
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// in all cases due to arithmetic limitations).
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// in all cases due to arithmetic limitations).
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// 2) enable communication by activating the rts, and
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// 2) enable communication by activating the rts, and
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// dtr signals in the modem control register. These
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// dtr signals in the modem control register. These
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// signals are defaulted to be active on reset, so they
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// signals are defaulted to be active on reset, so they
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// may not need to be set. The pRts and pDtr parameters
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// may not need to be set. The pRts and pDtr parameters
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// may be used to change the default setting.
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// may be used to change the default setting.
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// 3) use interrupts or poll the status register to
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// 3) use interrupts or poll the status register to
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// determine when to transmit or receive a byte of data
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// determine when to transmit or receive a byte of data
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// 4) read / write the transmit / recieve data buffer
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// 4) read / write the transmit / recieve data buffer
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// for communication.
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// for communication.
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//
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//
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// Notes:
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// Notes:
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// This core only supports a single transmission /
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// This core only supports a single transmission /
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// reception format: 1 start, 8 data, and 1 stop bit (no
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// reception format: 1 start, 8 data, and 1 stop bit (no
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// parity).
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// parity).
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// The baud rate generator uses a 24 bit harmonic
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// The baud rate generator uses a 24 bit harmonic
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// frequency synthesizer. Compute the multiplier value
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// frequency synthesizer. Compute the multiplier value
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// as if a 32 bit value was needed, then take the upper
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// as if a 32 bit value was needed, then take the upper
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// 24 bits of the value. (The number of significant bits
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// 24 bits of the value. (The number of significant bits
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// in the value determine the minimum frequency
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// in the value determine the minimum frequency
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// resolution or the precision of the value).
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// resolution or the precision of the value).
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//
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//
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// baud rate * 16
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// baud rate * 16
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// value = -----------------------
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// value = -----------------------
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// (clock frequency / 2^32)
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// (clock frequency / 2^32)
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//
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//
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// eg 38400 * 16
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// eg 38400 * 16
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// value = -----------------------
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// value = -----------------------
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// (28.63636MHz / 2^32)
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// (28.63636MHz / 2^32)
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//
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//
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// = 92149557.65
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// = 92149557.65
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// = 057E1736 (hex)
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// = 057E1736 (hex)
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//
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//
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//
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//
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// taking the upper 24 bits
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// taking the upper 24 bits
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// top 24 = 057E17
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// top 24 = 057E17
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// = 359959
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// = 359959
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//
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//
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// so the value needed to be programmed into the register
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// so the value needed to be programmed into the register
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// for 38.4k baud is 57E17 (hex)
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// for 38.4k baud is 57E17 (hex)
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// eg CM0 = 0 (not used)
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// eg CM0 = 0 (not used)
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// CM1 = 17 hex
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// CM1 = 17 hex
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// CM2 = 7E hex
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// CM2 = 7E hex
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// CM3 = 05 hex
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// CM3 = 05 hex
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//
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//
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//
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//
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// Register Description
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// Register Description
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//
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//
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// reg
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// reg
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// 0 read / write (RW)
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// 0 read / write (RW)
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// TRB - transmit / receive buffer
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// TRB - transmit / receive buffer
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// transmit / receive buffer
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// transmit / receive buffer
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// write - write to transmit buffer
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// write - write to transmit buffer
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// read - read from receive buffer
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// read - read from receive buffer
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//
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//
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// 1 read only (RO)
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// 1 read only (RO)
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// LS - line status register
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// LS - line status register
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// bit 0 = receiver not empty, this bit is set if there is
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// bit 0 = receiver not empty, this bit is set if there is
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// any data available in the receiver fifo
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// any data available in the receiver fifo
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// bit 1 = overrun, this bit is set if receiver overrun occurs
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// bit 1 = overrun, this bit is set if receiver overrun occurs
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// bit 3 = framing error, this bit is set if there was a
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// bit 3 = framing error, this bit is set if there was a
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// framing error with the current byte in the receiver
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// framing error with the current byte in the receiver
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// buffer.
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// buffer.
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// bit 5 = transmitter not full, this bit is set if the transmitter
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// bit 5 = transmitter not full, this bit is set if the transmitter
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// can accept more data
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// can accept more data
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// bit 6 = transmitter empty, this bit is set if the transmitter is
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// bit 6 = transmitter empty, this bit is set if the transmitter is
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// completely empty
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// completely empty
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//
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//
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// 2 MS - modem status register (RO)
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// 2 MS - modem status register (RO)
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// writing to the modem status register clears the change
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// writing to the modem status register clears the change
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// indicators, which should clear a modem status interrupt
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// indicators, which should clear a modem status interrupt
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// bit 3 = change on dcd signal
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// bit 3 = change on dcd signal
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// bit 4 = cts signal level
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// bit 4 = cts signal level
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// bit 5 = dsr signal level
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// bit 5 = dsr signal level
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// bit 6 = ri signal level
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// bit 6 = ri signal level
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// bit 7 = dcd signal level
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// bit 7 = dcd signal level
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//
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//
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// 3 IS - interrupt status register (RO)
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// 3 IS - interrupt status register (RO)
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// bit 0-4 = mailbox number
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// bit 0-4 = mailbox number
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// bit 0,1 = 00
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// bit 0,1 = 00
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// bit 2-4 = encoded interrupt value
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// bit 2-4 = encoded interrupt value
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// bit 5-6 = not used, reserved
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// bit 5-6 = not used, reserved
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// bit 7 = 1 = interrupt pending, 0 = no interrupt
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// bit 7 = 1 = interrupt pending, 0 = no interrupt
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//
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//
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// 4 IE - interrupt enable register (RW)
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// 4 IE - interrupt enable register (RW)
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// bit 0 = receive interrupt (data present)
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// bit 0 = receive interrupt (data present)
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// bit 1 = transmit interrupt (data empty)
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// bit 1 = transmit interrupt (data empty)
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// bit 3 = modem status (dcd) register change
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// bit 3 = modem status (dcd) register change
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// bit 5-7 = unused, reserved
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// bit 5-7 = unused, reserved
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//
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//
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// 5 FF - frame format register (RW)
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// 5 FF - frame format register (RW)
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// this register doesn't do anything in the simpleUart
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// this register doesn't do anything in the simpleUart
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// but is reserved for compatiblity with the more
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// but is reserved for compatiblity with the more
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// advanced uart
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// advanced uart
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//
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//
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// 6 MC - modem control register (RW)
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// 6 MC - modem control register (RW)
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// bit 0 = dtr signal level output
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// bit 0 = dtr signal level output
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// bit 1 = rts signal level output
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// bit 1 = rts signal level output
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//
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//
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// 7 - control register
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// 7 - control register
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// bit 0 = hardware flow control,
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// bit 0 = hardware flow control,
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// when this bit is set, the transmitter output is
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// when this bit is set, the transmitter output is
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// controlled by the cts signal line automatically
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// controlled by the cts signal line automatically
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//
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//
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//
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//
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// * Clock multiplier steps the 16xbaud clock frequency
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// * Clock multiplier steps the 16xbaud clock frequency
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// in increments of 1/2^32 of the clk_i input using a
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// in increments of 1/2^32 of the clk_i input using a
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// harmonic frequency synthesizer
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// harmonic frequency synthesizer
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// eg. to get a 9600 baud 16x clock (153.6 kHz) with a
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// eg. to get a 9600 baud 16x clock (153.6 kHz) with a
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// 27.175 MHz clock input,
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// 27.175 MHz clock input,
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// value = upper24(9600 * 16 / (27.175MHz / 2^32))
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// value = upper24(9600 * 16 / (27.175MHz / 2^32))
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// Higher frequency baud rates will exhibit more jitter
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// Higher frequency baud rates will exhibit more jitter
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// on the 16x clock, but this will mostly be masked by the
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// on the 16x clock, but this will mostly be masked by the
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// 16x clock factor.
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// 16x clock factor.
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//
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//
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// 8 CM0 - Clock Multiplier byte 0 (RW)
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// 8 CM0 - Clock Multiplier byte 0 (RW)
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// this is the least significant byte
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// this is the least significant byte
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// of the clock multiplier value
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// of the clock multiplier value
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// this register is not used unless the clock
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// this register is not used unless the clock
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// multiplier is set to contain 32 bit values
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// multiplier is set to contain 32 bit values
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//
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//
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// 9 CM1 - Clock Multiplier byte 1 (RW)
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// 9 CM1 - Clock Multiplier byte 1 (RW)
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// this is the third most significant byte
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// this is the third most significant byte
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// of the clock multiplier value
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// of the clock multiplier value
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// this register is not used unless the clock
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// this register is not used unless the clock
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// multiplier is set to contain 24 or 32 bit values
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// multiplier is set to contain 24 or 32 bit values
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//
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//
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// 10 CM2 - Clock Multiplier byte 2 (RW)
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// 10 CM2 - Clock Multiplier byte 2 (RW)
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// this is the second most significant byte of the clock
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// this is the second most significant byte of the clock
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// multiplier value
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// multiplier value
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//
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//
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// 11 CM3 - Clock Multiplier byte 3 (RW)
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// 11 CM3 - Clock Multiplier byte 3 (RW)
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// this is the most significant byte of the multiplier value
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// this is the most significant byte of the multiplier value
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//
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//
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// 12 FC - Fifo control register (RW)
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// 12 FC - Fifo control register (RW)
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// this register doesnt' do anything in the simpleUart
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// this register doesnt' do anything in the simpleUart
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// but is reserved for compatibility with the more
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// but is reserved for compatibility with the more
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// advanced uart
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// advanced uart
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//
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//
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// 13-14 reserved registers
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// 13-14 reserved registers
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//
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//
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// 15 SPR - scratch pad register (RW)
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// 15 SPR - scratch pad register (RW)
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//
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//
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//
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//
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |WISHBONE Datasheet
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// |WISHBONE Datasheet
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// |WISHBONE SoC Architecture Specification, Revision B.3
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// |WISHBONE SoC Architecture Specification, Revision B.3
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// |
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// |
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// |Description: Specifications:
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// |Description: Specifications:
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |General Description: simple UART core
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// |General Description: simple UART core
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Supported Cycles: SLAVE,READ/WRITE
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// |Supported Cycles: SLAVE,READ/WRITE
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// | SLAVE,BLOCK READ/WRITE
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// | SLAVE,BLOCK READ/WRITE
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// | SLAVE,RMW
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// | SLAVE,RMW
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Data port, size: 8 bit
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// |Data port, size: 8 bit
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// |Data port, granularity: 8 bit
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// |Data port, granularity: 8 bit
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// |Data port, maximum operand size: 8 bit
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// |Data port, maximum operand size: 8 bit
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// |Data transfer ordering: Undefined
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// |Data transfer ordering: Undefined
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// |Data transfer sequencing: Undefined
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// |Data transfer sequencing: Undefined
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Clock frequency constraints: none
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// |Clock frequency constraints: none
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Supported signal list and Signal Name WISHBONE equiv.
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// |Supported signal list and Signal Name WISHBONE equiv.
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// |cross reference to equivalent ack_o ACK_O
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// |cross reference to equivalent ack_o ACK_O
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// |WISHBONE signals adr_i[3:0] ADR_I()
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// |WISHBONE signals adr_i[3:0] ADR_I()
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// | clk_i CLK_I
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// | clk_i CLK_I
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// | rst_i RST_I()
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// | rst_i RST_I()
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// | dat_i(7:0) DAT_I()
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// | dat_i(7:0) DAT_I()
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// | dat_o(7:0) DAT_O()
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// | dat_o(7:0) DAT_O()
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// | cyc_i CYC_I
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// | cyc_i CYC_I
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// | stb_i STB_I
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// | stb_i STB_I
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// | we_i WE_I
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// | we_i WE_I
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// |
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// |
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Special requirements:
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// |Special requirements:
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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//
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//=============================================================================
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//=============================================================================
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`define UART_TRB 4'd0 // transmit/receive buffer
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`define UART_TRB 4'd0 // transmit/receive buffer
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`define UART_LS 4'd1 // line status register
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`define UART_LS 4'd1 // line status register
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`define UART_MS 4'd2 // modem status register
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`define UART_MS 4'd2 // modem status register
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`define UART_IS 4'd3 // interrupt status register
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`define UART_IS 4'd3 // interrupt status register
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`define UART_IER 4'd4 // interrupt enable
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`define UART_IER 4'd4 // interrupt enable
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`define UART_FF 4'd5 // frame format register
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`define UART_FF 4'd5 // frame format register
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`define UART_MC 4'd6 // modem control register
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`define UART_MC 4'd6 // modem control register
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`define UART_CTRL 4'd7 // control register
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`define UART_CTRL 4'd7 // control register
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`define UART_CLKM0 4'd8 // clock multiplier byte 0
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`define UART_CLKM0 4'd8 // clock multiplier byte 0
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`define UART_CLKM1 4'd9 // clock multiplier byte 1
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`define UART_CLKM1 4'd9 // clock multiplier byte 1
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`define UART_CLKM2 4'd10 // clock multiplier byte 2
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`define UART_CLKM2 4'd10 // clock multiplier byte 2
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`define UART_CLKM3 4'd11 // clock multiplier byte 3
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`define UART_CLKM3 4'd11 // clock multiplier byte 3
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`define UART_FC 4'd12 // fifo control register
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`define UART_FC 4'd12 // fifo control register
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|
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module rtfSimpleUart(
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module rtfSimpleUart(
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// WISHBONE Slave interface
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// WISHBONE Slave interface
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input rst_i, // reset
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input rst_i, // reset
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input clk_i, // eg 100.7MHz
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input clk_i, // eg 100.7MHz
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input cyc_i, // cycle valid
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input cyc_i, // cycle valid
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input stb_i, // strobe
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input stb_i, // strobe
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input we_i, // 1 = write
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input we_i, // 1 = write
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input [31:0] adr_i, // register address
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input [31:0] adr_i, // register address
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input [7:0] dat_i, // data input bus
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input [7:0] dat_i, // data input bus
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output reg [7:0] dat_o, // data output bus
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output reg [7:0] dat_o, // data output bus
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output ack_o, // transfer acknowledge
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output ack_o, // transfer acknowledge
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output vol_o, // volatile register selected
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output vol_o, // volatile register selected
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output irq_o, // interrupt request
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output irq_o, // interrupt request
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//----------------
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//----------------
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input cts_ni, // clear to send - active low - (flow control)
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input cts_ni, // clear to send - active low - (flow control)
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output reg rts_no, // request to send - active low - (flow control)
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output reg rts_no, // request to send - active low - (flow control)
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input dsr_ni, // data set ready - active low
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input dsr_ni, // data set ready - active low
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input dcd_ni, // data carrier detect - active low
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input dcd_ni, // data carrier detect - active low
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output reg dtr_no, // data terminal ready - active low
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output reg dtr_no, // data terminal ready - active low
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input rxd_i, // serial data in
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input rxd_i, // serial data in
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output txd_o, // serial data out
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output txd_o, // serial data out
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output data_present_o
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output data_present_o,
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//----------------
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|
output baud16_clk
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);
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);
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parameter pClkFreq = 20000000; // clock frequency in MHz
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parameter pClkFreq = 20000000; // clock frequency in MHz
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parameter pBaud = 19200;
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parameter pBaud = 19200;
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parameter pClkMul = (4096 * pBaud) / (pClkFreq / 65536);
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parameter pClkMul = (4096 * pBaud) / (pClkFreq / 65536);
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parameter pRts = 1; // default to active
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parameter pRts = 1; // default to active
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parameter pDtr = 1;
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parameter pDtr = 1;
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|
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wire cs = cyc_i && stb_i && (adr_i[31:4]==28'hFFDC_0A0);
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wire cs = cyc_i && stb_i && (adr_i[31:4]==28'hFFDC_0A0);
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assign ack_o = cs;
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assign ack_o = cs;
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assign vol_o = cs && adr_i[3:2]==2'b00;
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assign vol_o = cs && adr_i[3:2]==2'b00;
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|
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//-------------------------------------------
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//-------------------------------------------
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// variables
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// variables
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reg [23:0] c; // current count
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reg [23:0] c; // current count
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reg [23:0] ck_mul; // baud rate clock multiplier
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reg [23:0] ck_mul; // baud rate clock multiplier
|
wire tx_empty;
|
wire tx_empty;
|
wire baud16; // edge detector (active one cycle only!)
|
wire baud16; // edge detector (active one cycle only!)
|
reg rx_present_ie;
|
reg rx_present_ie;
|
reg tx_empty_ie;
|
reg tx_empty_ie;
|
reg dcd_ie;
|
reg dcd_ie;
|
reg hwfc; // hardware flow control enable
|
reg hwfc; // hardware flow control enable
|
wire clear = cyc_i && stb_i && we_i && adr_i==4'd13;
|
wire clear = cyc_i && stb_i && we_i && adr_i==4'd13;
|
wire frame_err; // receiver char framing error
|
wire frame_err; // receiver char framing error
|
wire over_run; // receiver over run
|
wire over_run; // receiver over run
|
reg [1:0] ctsx; // cts_ni sampling
|
reg [1:0] ctsx; // cts_ni sampling
|
reg [1:0] dcdx;
|
reg [1:0] dcdx;
|
reg [1:0] dsrx;
|
reg [1:0] dsrx;
|
wire dcd_chg = dcdx[1]^dcdx[0];
|
wire dcd_chg = dcdx[1]^dcdx[0];
|
|
|
|
|
wire rxIRQ = data_present_o & rx_present_ie;
|
wire rxIRQ = data_present_o & rx_present_ie;
|
wire txIRQ = tx_empty & tx_empty_ie;
|
wire txIRQ = tx_empty & tx_empty_ie;
|
wire msIRQ = dcd_chg & dcd_ie;
|
wire msIRQ = dcd_chg & dcd_ie;
|
|
|
assign irq_o =
|
assign irq_o =
|
rxIRQ
|
rxIRQ
|
| txIRQ
|
| txIRQ
|
| msIRQ
|
| msIRQ
|
;
|
;
|
|
assign baud16_clk = baud16;
|
|
|
wire [2:0] irqenc =
|
wire [2:0] irqenc =
|
rxIRQ ? 1 :
|
rxIRQ ? 1 :
|
txIRQ ? 3 :
|
txIRQ ? 3 :
|
msIRQ ? 4 :
|
msIRQ ? 4 :
|
0;
|
0;
|
|
|
wire [7:0] rx_do;
|
wire [7:0] rx_do;
|
wire txrx = cs && adr_i[3:0]==4'd0;
|
wire txrx = cs && adr_i[3:0]==4'd0;
|
|
|
rtfSimpleUartRx uart_rx0(
|
rtfSimpleUartRx uart_rx0(
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.cyc_i(cyc_i),
|
.cyc_i(cyc_i),
|
.stb_i(stb_i),
|
.stb_i(stb_i),
|
.cs_i(txrx),
|
.cs_i(txrx),
|
.we_i(we_i),
|
.we_i(we_i),
|
.dat_o(rx_do),
|
.dat_o(rx_do),
|
.baud16x_ce(baud16),
|
.baud16x_ce(baud16),
|
.clear(clear),
|
.clear(clear),
|
.rxd(rxd_i),
|
.rxd(rxd_i),
|
.data_present(data_present_o),
|
.data_present(data_present_o),
|
.frame_err(frame_err),
|
.frame_err(frame_err),
|
.overrun(over_run)
|
.overrun(over_run)
|
);
|
);
|
|
|
rtfSimpleUartTx uart_tx0(
|
rtfSimpleUartTx uart_tx0(
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.cyc_i(cyc_i),
|
.cyc_i(cyc_i),
|
.stb_i(stb_i),
|
.stb_i(stb_i),
|
.cs_i(txrx),
|
.cs_i(txrx),
|
.we_i(we_i),
|
.we_i(we_i),
|
.dat_i(dat_i),
|
.dat_i(dat_i),
|
.baud16x_ce(baud16),
|
.baud16x_ce(baud16),
|
.cts(ctsx[1]|~hwfc),
|
.cts(ctsx[1]|~hwfc),
|
.txd(txd_o),
|
.txd(txd_o),
|
.empty(tx_empty)
|
.empty(tx_empty)
|
);
|
);
|
|
|
// mux the reg outputs
|
// mux the reg outputs
|
always @*
|
always @*
|
if (cs) begin
|
if (cs) begin
|
case(adr_i[3:0]) // synopsys full_case parallel_case
|
case(adr_i[3:0]) // synopsys full_case parallel_case
|
`UART_MS: dat_o <= {dcdx[1],1'b0,dsrx[1],ctsx[1],dcd_chg,3'b0};
|
`UART_MS: dat_o <= {dcdx[1],1'b0,dsrx[1],ctsx[1],dcd_chg,3'b0};
|
`UART_IS: dat_o <= {irq_o, 2'b0, irqenc, 2'b0};
|
`UART_IS: dat_o <= {irq_o, 2'b0, irqenc, 2'b0};
|
`UART_LS: dat_o <= {1'b0, tx_empty, tx_empty, 1'b0, frame_err, 1'b0, over_run, data_present_o};
|
`UART_LS: dat_o <= {1'b0, tx_empty, tx_empty, 1'b0, frame_err, 1'b0, over_run, data_present_o};
|
default: dat_o <= rx_do;
|
default: dat_o <= rx_do;
|
endcase
|
endcase
|
end
|
end
|
else
|
else
|
dat_o <= 8'b0;
|
dat_o <= 8'b0;
|
|
|
// Note: baud clock should pulse high for only a single
|
// Note: baud clock should pulse high for only a single
|
// cycle!
|
// cycle!
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (rst_i)
|
if (rst_i)
|
c <= 0;
|
c <= 0;
|
else
|
else
|
c <= c + ck_mul;
|
c <= c + ck_mul;
|
|
|
// for detecting an edge on the msb
|
// for detecting an edge on the msb
|
edge_det ed0(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(c[23]), .pe(baud16), .ne(), .ee() );
|
edge_det ed0(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(c[23]), .pe(baud16), .ne(), .ee() );
|
|
|
// register updates
|
// register updates
|
always @(posedge clk_i) begin
|
always @(posedge clk_i) begin
|
if (rst_i) begin
|
if (rst_i) begin
|
rts_no <= ~pRts;
|
rts_no <= ~pRts;
|
rx_present_ie <= 1'b0;
|
rx_present_ie <= 1'b0;
|
tx_empty_ie <= 1'b0;
|
tx_empty_ie <= 1'b0;
|
dcd_ie <= 1'b0;
|
dcd_ie <= 1'b0;
|
hwfc <= 1'b1;
|
hwfc <= 1'b1;
|
dtr_no <= ~pDtr;
|
dtr_no <= ~pDtr;
|
ck_mul <= pClkMul;
|
ck_mul <= pClkMul;
|
end
|
end
|
else if (cs & we_i) begin
|
else if (cs & we_i) begin
|
case (adr_i)
|
case (adr_i)
|
`UART_IER:
|
`UART_IER:
|
begin
|
begin
|
rx_present_ie <= dat_i[0];
|
rx_present_ie <= dat_i[0];
|
tx_empty_ie <= dat_i[1];
|
tx_empty_ie <= dat_i[1];
|
dcd_ie <= dat_i[3];
|
dcd_ie <= dat_i[3];
|
end
|
end
|
`UART_MC:
|
`UART_MC:
|
begin
|
begin
|
dtr_no <= ~dat_i[0];
|
dtr_no <= ~dat_i[0];
|
rts_no <= ~dat_i[1];
|
rts_no <= ~dat_i[1];
|
end
|
end
|
`UART_CTRL: hwfc <= dat_i[0];
|
`UART_CTRL: hwfc <= dat_i[0];
|
`UART_CLKM1: ck_mul[7:0] <= dat_i;
|
`UART_CLKM1: ck_mul[7:0] <= dat_i;
|
`UART_CLKM2: ck_mul[15:8] <= dat_i;
|
`UART_CLKM2: ck_mul[15:8] <= dat_i;
|
`UART_CLKM3: ck_mul[23:16] <= dat_i;
|
`UART_CLKM3: ck_mul[23:16] <= dat_i;
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
// synchronize external signals
|
// synchronize external signals
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
ctsx <= {ctsx[0],~cts_ni};
|
ctsx <= {ctsx[0],~cts_ni};
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
dcdx <= {dcdx[0],~dcd_ni};
|
dcdx <= {dcdx[0],~dcd_ni};
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
dsrx <= {dsrx[0],~dsr_ni};
|
dsrx <= {dsrx[0],~dsr_ni};
|
|
|
endmodule
|
endmodule
|
|
|
|
|
