Simply RISC S1 Core - OpenSPARC sources updating
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S1 Core - OpenSPARC sources updating
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====================================
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To update the source files of the SPARC Core to the latest
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To update the source files of the SPARC Core to the latest
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version provided by Sun Microsystems with their OpenSPARC
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version provided by Sun Microsystems with their OpenSPARC
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T1 project, please perform the following steps:
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T1 project, please perform the following steps:
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- download the latest chip design from www.opensparc.net
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- download the latest chip design from www.opensparc.net
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(requires free registration and takes a while);
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(requires free registration and takes a while);
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- unpack the tarball, for instance under ~/opensparc-t1 ;
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- unpack the tarball, for instance under ~/opensparc-t1 ;
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- make the T1_ROOT enviroment variable contained in your
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- make the T1_ROOT enviroment variable contained in your
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top-most $S1_ROOT/sourceme file match the directory
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top-most $S1_ROOT/sourceme file match the directory
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you used in the previous step;
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you used in the previous step;
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- source the sourceme file in a fresh opened shell.
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- source the sourceme file in a fresh opened shell.
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Now you are ready to perform the updating; a script named
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Now you are ready to perform the updating; a script named
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"update_sparccore" is provided and it can be called using
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"update_sparccore" is provided and it can be called using
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the following syntax:
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the following syntax:
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update_sparccore -me
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update_sparccore -me
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or
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or
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update_sparccore -se
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update_sparccore -se
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or
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or
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update_sparccore -ee
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update_sparccore -ee
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From now on, all the commands you use to simulate or to
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From now on, all the commands you use to simulate or to
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synthesize the design will refer to the SPARC Core version
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synthesize the design will refer to the SPARC Core version
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you are using.
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you are using.
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NOTE: in order to call the "update_sparccore" installed you
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NOTE: in order to call the "update_sparccore" installed you
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*MUST* have Icarus Verilog installed, since it is used to
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*MUST* have Icarus Verilog installed, since it is used to
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preprocess the Verilog files; no matter you want to use
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preprocess the Verilog files; no matter you want to use
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another simulator for functional verification.
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another simulator for functional verification.
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The argument to the script works as follows:
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The argument to the script works as follows:
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- S1 Core ME (Memory-less Edition): one thread, no cache;
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- S1 Core ME (Memory-less Edition): one thread, no cache;
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- S1 Core SE (Single-thread Edition): one thread, usual 16K+8K L1 caches;
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- S1 Core SE (Single-thread Edition): one thread, usual 16K+8K L1 caches;
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- S1 Core EE (Elite Edition): four threads, usual 16K+8K L1 caches.
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- S1 Core EE (Elite Edition): four threads, usual 16K+8K L1 caches.
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