/*
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/*
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* Simply RISC CacheDir
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* CacheDir
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*
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*
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* (C) Copyleft 2007 Simply RISC LLP
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* (C) Copyleft 2007 Fabrizio Fazzino
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* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
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*
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*
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* LICENSE:
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* LICENSE:
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* This is a Free Hardware Design; you can redistribute it and/or
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* This is a Free Hardware Design; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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* version 2 as published by the Free Software Foundation.
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* The above named program is distributed in the hope that it will
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* The above named program is distributed in the hope that it will
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* be useful, but WITHOUT ANY WARRANTY; without even the implied
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* be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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* See the GNU General Public License for more details.
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*
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*
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* DESCRIPTION:
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* DESCRIPTION:
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* Replica of the 'cachedir' module used by Dmitry for his advanced
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* Replica of the 'cachedir' module used by Dmitry for his advanced
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* bridge, the original one was from an Altera Memory Megafunction.
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* bridge, the original one was from an Altera Memory Megafunction.
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*/
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*/
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`timescale 1ns/100ps
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`timescale 1ns/100ps
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`define CACHEDIR_ADDR_WIDTH 9
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`define CACHEDIR_ADDR_WIDTH 9
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`define CACHEDIR_DATA_WIDTH 29
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`define CACHEDIR_DATA_WIDTH 29
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module cachedir(
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module cachedir(
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// System
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// System
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input clock,
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input clock,
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input enable,
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input enable,
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// Port A
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// Port A
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input wren_a,
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input wren_a,
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input [(`CACHEDIR_ADDR_WIDTH-1):0] address_a,
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input [(`CACHEDIR_ADDR_WIDTH-1):0] address_a,
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input [(`CACHEDIR_DATA_WIDTH-1):0] data_a,
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input [(`CACHEDIR_DATA_WIDTH-1):0] data_a,
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output [(`CACHEDIR_DATA_WIDTH-1):0] q_a,
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output [(`CACHEDIR_DATA_WIDTH-1):0] q_a,
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// Port B
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// Port B
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input wren_b,
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input wren_b,
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input [(`CACHEDIR_ADDR_WIDTH-1):0] address_b,
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input [(`CACHEDIR_ADDR_WIDTH-1):0] address_b,
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input [(`CACHEDIR_DATA_WIDTH-1):0] data_b,
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input [(`CACHEDIR_DATA_WIDTH-1):0] data_b,
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output [(`CACHEDIR_DATA_WIDTH-1):0] q_b
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output [(`CACHEDIR_DATA_WIDTH-1):0] q_b
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);
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);
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// Memory Array
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// Memory Array
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logic [(`CACHEDIR_DATA_WIDTH-1):0] mem[(1<<`CACHEDIR_ADDR_WIDTH)-1];
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logic [(`CACHEDIR_DATA_WIDTH-1):0] mem[(1<<`CACHEDIR_ADDR_WIDTH)-1];
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// Read Logic (TODO: may be gate by enable to save power)
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// Read Logic (TODO: may be gate by enable to save power)
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assign q_a = mem[address_a];
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assign q_a = mem[address_a];
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assign q_b = mem[address_b];
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assign q_b = mem[address_b];
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// Write Process (TODO: may be gated by some reset)
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// Write Process (TODO: may be gated by some reset)
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always @(posedge clock) begin
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always @(posedge clock) begin
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if(wren_a) begin
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if(wren_a) begin
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`ifdef SIMPLY_RISC_DEBUG
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`ifdef SIMPLY_RISC_DEBUG
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$display("CacheDir Write Enable Port A");
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$display("CacheDir Write Enable Port A");
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`endif
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`endif
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mem[address_a] <= data_a;
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mem[address_a] <= data_a;
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end
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end
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if(wren_b) begin
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if(wren_b) begin
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`ifdef SIMPLY_RISC_DEBUG
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`ifdef SIMPLY_RISC_DEBUG
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$display("CacheDir Write Enable Port B");
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$display("CacheDir Write Enable Port B");
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`endif
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`endif
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mem[address_b] <= data_b;
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mem[address_b] <= data_b;
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end
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end
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end
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end
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endmodule // cachedir
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endmodule // cachedir
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