/*
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/*
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* Reset Controller
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* S1 Reset Controller
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*
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*
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* (C) Copyleft 2007 Simply RISC LLP
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* (C) Copyleft 2007 Fabrizio Fazzino
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* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
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*
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*
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* LICENSE:
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* LICENSE:
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* This is a Free Hardware Design; you can redistribute it and/or
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* This is a Free Hardware Design; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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* version 2 as published by the Free Software Foundation.
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* The above named program is distributed in the hope that it will
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* The above named program is distributed in the hope that it will
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* be useful, but WITHOUT ANY WARRANTY; without even the implied
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* be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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* See the GNU General Public License for more details.
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*
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*
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* DESCRIPTION:
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* DESCRIPTION:
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* This block implements the Reset Controller used by the S1 Core
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* This block implements the Reset Controller used by the S1 Core
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* to wake up the SPARC Core of the OpenSPARC T1; its behavior was
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* to wake up the SPARC Core of the OpenSPARC T1; its behavior was
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* reverse-engineered from the OpenSPARC waveforms.
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* reverse-engineered from the OpenSPARC waveforms.
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*/
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*/
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`include "s1_defs.h"
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`include "s1_defs.h"
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module rst_ctrl (
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module rst_ctrl (
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sys_clock_i, sys_reset_i,
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sys_clock_i, sys_reset_i,
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cluster_cken_o, gclk_o, cmp_grst_o, cmp_arst_o,
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cluster_cken_o, gclk_o, cmp_grst_o, cmp_arst_o,
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ctu_tst_pre_grst_o, adbginit_o, gdbginit_o,
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ctu_tst_pre_grst_o, adbginit_o, gdbginit_o,
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sys_reset_final_o
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sys_reset_final_o
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);
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);
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/*
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/*
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* Inputs
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* Inputs
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*/
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*/
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// System inputs
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// System inputs
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input sys_clock_i; // System Clock
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input sys_clock_i; // System Clock
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input sys_reset_i; // System Reset
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input sys_reset_i; // System Reset
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/*
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/*
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* Registered Outputs
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* Registered Outputs
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*/
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*/
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output gclk_o;
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output gclk_o;
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/*
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/*
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* Registered Outputs
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* Registered Outputs
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*/
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*/
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// SPARC Core inputs
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// SPARC Core inputs
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output cluster_cken_o;
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output cluster_cken_o;
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reg cluster_cken_o;
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reg cluster_cken_o;
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output cmp_grst_o;
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output cmp_grst_o;
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reg cmp_grst_o;
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reg cmp_grst_o;
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output cmp_arst_o;
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output cmp_arst_o;
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reg cmp_arst_o;
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reg cmp_arst_o;
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output ctu_tst_pre_grst_o;
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output ctu_tst_pre_grst_o;
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reg ctu_tst_pre_grst_o;
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reg ctu_tst_pre_grst_o;
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output adbginit_o;
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output adbginit_o;
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reg adbginit_o;
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reg adbginit_o;
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output gdbginit_o;
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output gdbginit_o;
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reg gdbginit_o;
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reg gdbginit_o;
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output sys_reset_final_o;
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output sys_reset_final_o;
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reg sys_reset_final_o;
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reg sys_reset_final_o;
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/*
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/*
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* Registers
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* Registers
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*/
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*/
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// Counter used as a timer to strobe the reset signals
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// Counter used as a timer to strobe the reset signals
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reg[`TIMER_BITS-1:0] cycle_counter;
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reg[`TIMER_BITS-1:0] cycle_counter;
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/*
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/*
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* Procedural blocks
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* Procedural blocks
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*/
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*/
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// This process handles the timer counter
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// This process handles the timer counter
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always @(posedge sys_clock_i)
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always @(posedge sys_clock_i)
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begin
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begin
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if(sys_reset_i==1'b1)
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if(sys_reset_i==1'b1)
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begin
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begin
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cycle_counter = 0;
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cycle_counter = 0;
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end
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end
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else
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else
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begin
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begin
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if(cycle_counter[`TIMER_BITS-1]==1'b0)
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if(cycle_counter[`TIMER_BITS-1]==1'b0)
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begin
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begin
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cycle_counter = cycle_counter+1;
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cycle_counter = cycle_counter+1;
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end
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end
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end
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end
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end
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end
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// This other process assigns the proper values to the outputs
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// This other process assigns the proper values to the outputs
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// (that are used as system inputs by the SPARC Core)
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// (that are used as system inputs by the SPARC Core)
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always @(posedge sys_clock_i)
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always @(posedge sys_clock_i)
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begin
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begin
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if(sys_reset_i==1)
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if(sys_reset_i==1)
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begin
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begin
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cluster_cken_o <= 0;
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cluster_cken_o <= 0;
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cmp_grst_o <= 0;
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cmp_grst_o <= 0;
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cmp_arst_o <= 0;
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cmp_arst_o <= 0;
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ctu_tst_pre_grst_o <= 0;
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ctu_tst_pre_grst_o <= 0;
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adbginit_o <= 0;
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adbginit_o <= 0;
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gdbginit_o <= 0;
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gdbginit_o <= 0;
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sys_reset_final_o <= 1;
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sys_reset_final_o <= 1;
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end
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end
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else
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else
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begin
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begin
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if(cycle_counter<`RESET_CYCLES_1)
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if(cycle_counter<`RESET_CYCLES_1)
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begin
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begin
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cluster_cken_o <= 0;
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cluster_cken_o <= 0;
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cmp_grst_o <= 0;
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cmp_grst_o <= 0;
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cmp_arst_o <= 0;
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cmp_arst_o <= 0;
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ctu_tst_pre_grst_o <= 0;
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ctu_tst_pre_grst_o <= 0;
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adbginit_o <= 0;
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adbginit_o <= 0;
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gdbginit_o <= 0;
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gdbginit_o <= 0;
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sys_reset_final_o <= 1;
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sys_reset_final_o <= 1;
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end
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end
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else
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else
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if(cycle_counter<`RESET_CYCLES_2)
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if(cycle_counter<`RESET_CYCLES_2)
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begin
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begin
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cluster_cken_o <= 0;
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cluster_cken_o <= 0;
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cmp_grst_o <= 0;
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cmp_grst_o <= 0;
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cmp_arst_o <= 1; // <--
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cmp_arst_o <= 1; // <--
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ctu_tst_pre_grst_o <= 0;
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ctu_tst_pre_grst_o <= 0;
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adbginit_o <= 1; // <--
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adbginit_o <= 1; // <--
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gdbginit_o <= 0;
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gdbginit_o <= 0;
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sys_reset_final_o <= 1;
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sys_reset_final_o <= 1;
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end
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end
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else
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else
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if(cycle_counter<`RESET_CYCLES_3)
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if(cycle_counter<`RESET_CYCLES_3)
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begin
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begin
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cluster_cken_o <= 1; // <--
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cluster_cken_o <= 1; // <--
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cmp_grst_o <= 0;
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cmp_grst_o <= 0;
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cmp_arst_o <= 1;
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cmp_arst_o <= 1;
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ctu_tst_pre_grst_o <= 1; // <--
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ctu_tst_pre_grst_o <= 1; // <--
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adbginit_o <= 1;
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adbginit_o <= 1;
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gdbginit_o <= 0;
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gdbginit_o <= 0;
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sys_reset_final_o <= 1;
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sys_reset_final_o <= 1;
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end
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end
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else
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else
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if(cycle_counter<`RESET_CYCLES_4)
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if(cycle_counter<`RESET_CYCLES_4)
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begin
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begin
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cluster_cken_o <= 1;
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cluster_cken_o <= 1;
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cmp_grst_o <= 1; // <--
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cmp_grst_o <= 1; // <--
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cmp_arst_o <= 1;
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cmp_arst_o <= 1;
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ctu_tst_pre_grst_o <= 1;
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ctu_tst_pre_grst_o <= 1;
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adbginit_o <= 1;
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adbginit_o <= 1;
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gdbginit_o <= 1; // <--
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gdbginit_o <= 1; // <--
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sys_reset_final_o <= 1;
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sys_reset_final_o <= 1;
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end
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end
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else
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else
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begin
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begin
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cluster_cken_o <= 1;
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cluster_cken_o <= 1;
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cmp_grst_o <= 1;
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cmp_grst_o <= 1;
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cmp_arst_o <= 1;
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cmp_arst_o <= 1;
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ctu_tst_pre_grst_o <= 1;
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ctu_tst_pre_grst_o <= 1;
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adbginit_o <= 1;
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adbginit_o <= 1;
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gdbginit_o <= 1;
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gdbginit_o <= 1;
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sys_reset_final_o <= 0; // <--
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sys_reset_final_o <= 0; // <--
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end
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end
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end
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end
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end
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end
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assign gclk_o = (cycle_counter>`GCLK_CYCLES) & sys_clock_i;
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assign gclk_o = (cycle_counter>`GCLK_CYCLES) & sys_clock_i;
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endmodule
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endmodule
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