/*
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/*
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* Simply RISC S1 Core Top-Level
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* S1 Core Top-Level
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*
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*
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* (C) 2007 Simply RISC LLP
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* (C) 2007 Fabrizio Fazzino
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* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
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*
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*
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* LICENSE:
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* LICENSE:
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* This is a Free Hardware Design; you can redistribute it and/or
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* This is a Free Hardware Design; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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* version 2 as published by the Free Software Foundation.
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* The above named program is distributed in the hope that it will
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* The above named program is distributed in the hope that it will
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* be useful, but WITHOUT ANY WARRANTY; without even the implied
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* be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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* See the GNU General Public License for more details.
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*
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*
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* DESCRIPTION:
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* DESCRIPTION:
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* This block implements the top-level of the S1 Core.
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* This block implements the top-level of the S1 Core.
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* It is just a schematic with four instances:
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* It is just a schematic with four instances:
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* 1) one single SPARC Core of the OpenSPARC T1;
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* 1) one single SPARC Core of the OpenSPARC T1;
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* 2) a SPARC Core to Wishbone Master bridge;
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* 2) a SPARC Core to Wishbone Master bridge;
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* 3) a Reset Controller;
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* 3) a Reset Controller;
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* 4) an Interrupt Controller;
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* 4) an Interrupt Controller;
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* 5) a Floating-Point Unit from the OpenSPARC SoC.
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* 5) a Floating-Point Unit from the OpenSPARC SoC.
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*/
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*/
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`include "s1_defs.h"
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`include "s1_defs.h"
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module s1_top (
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module s1_top (
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/*
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/*
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* Inputs
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* Inputs
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*/
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*/
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// System inputs
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// System inputs
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input sys_clock_i, // System Clock
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input sys_clock_i, // System Clock
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input sys_reset_i, // System Reset
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input sys_reset_i, // System Reset
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input[63:0] sys_irq_i, // Interrupt Requests
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input[63:0] sys_irq_i, // Interrupt Requests
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|
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// Wishbone Interconnect Master Interface inputs
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// Wishbone Interconnect Master Interface inputs
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input wbm_ack_i, // Ack
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input wbm_ack_i, // Ack
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input[(`WB_DATA_WIDTH-1):0] wbm_data_i, // Data In
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input[(`WB_DATA_WIDTH-1):0] wbm_data_i, // Data In
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/*
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/*
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* Outputs
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* Outputs
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*/
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*/
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// Wishbone Interconnect Master Interface outputs
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// Wishbone Interconnect Master Interface outputs
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output wbm_cycle_o, // Cycle Start
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output wbm_cycle_o, // Cycle Start
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output wbm_strobe_o, // Strobe Request
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output wbm_strobe_o, // Strobe Request
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output wbm_we_o, // Write Enable
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output wbm_we_o, // Write Enable
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output[`WB_ADDR_WIDTH-1:0] wbm_addr_o, // Address Bus
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output[`WB_ADDR_WIDTH-1:0] wbm_addr_o, // Address Bus
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output[`WB_DATA_WIDTH-1:0] wbm_data_o, // Data Out
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output[`WB_DATA_WIDTH-1:0] wbm_data_o, // Data Out
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output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o // Select Output
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output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o // Select Output
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);
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);
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/*
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/*
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* Wires
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* Wires
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*/
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*/
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// Wires connected to SPARC Core outputs
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// Wires connected to SPARC Core outputs
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// pcx
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// pcx
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wire [4:0] spc_pcx_req_pq; // processor to pcx request
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wire [4:0] spc_pcx_req_pq; // processor to pcx request
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wire spc_pcx_atom_pq; // processor to pcx atomic request
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wire spc_pcx_atom_pq; // processor to pcx atomic request
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wire [`PCX_WIDTH-1:0] spc_pcx_data_pa; // processor to pcx packet
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wire [`PCX_WIDTH-1:0] spc_pcx_data_pa; // processor to pcx packet
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// shadow scan
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// shadow scan
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wire spc_sscan_so; // From ifu of sparc_ifu.v
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wire spc_sscan_so; // From ifu of sparc_ifu.v
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wire spc_scanout0; // From test_stub of test_stub_bist.v
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wire spc_scanout0; // From test_stub of test_stub_bist.v
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wire spc_scanout1; // From test_stub of test_stub_bist.v
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wire spc_scanout1; // From test_stub of test_stub_bist.v
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// bist
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// bist
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wire tst_ctu_mbist_done; // From test_stub of test_stub_two_bist.v
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wire tst_ctu_mbist_done; // From test_stub of test_stub_two_bist.v
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wire tst_ctu_mbist_fail; // From test_stub of test_stub_two_bist.v
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wire tst_ctu_mbist_fail; // From test_stub of test_stub_two_bist.v
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// fuse
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// fuse
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wire spc_efc_ifuse_data; // From ifu of sparc_ifu.v
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wire spc_efc_ifuse_data; // From ifu of sparc_ifu.v
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wire spc_efc_dfuse_data; // From ifu of sparc_ifu.v
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wire spc_efc_dfuse_data; // From ifu of sparc_ifu.v
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// Wires connected to SPARC Core inputs
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// Wires connected to SPARC Core inputs
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// cpx interface
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// cpx interface
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wire [4:0] pcx_spc_grant_px; // pcx to processor grant info
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wire [4:0] pcx_spc_grant_px; // pcx to processor grant info
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wire cpx_spc_data_rdy_cx2; // cpx data inflight to sparc
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wire cpx_spc_data_rdy_cx2; // cpx data inflight to sparc
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wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2; // cpx to sparc data packet
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wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2; // cpx to sparc data packet
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wire [3:0] const_cpuid;
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wire [3:0] const_cpuid;
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wire [7:0] const_maskid; // To ifu of sparc_ifu.v
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wire [7:0] const_maskid; // To ifu of sparc_ifu.v
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// sscan
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// sscan
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wire ctu_tck; // To ifu of sparc_ifu.v
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wire ctu_tck; // To ifu of sparc_ifu.v
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wire ctu_sscan_se; // To ifu of sparc_ifu.v
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wire ctu_sscan_se; // To ifu of sparc_ifu.v
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wire ctu_sscan_snap; // To ifu of sparc_ifu.v
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wire ctu_sscan_snap; // To ifu of sparc_ifu.v
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wire [3:0] ctu_sscan_tid; // To ifu of sparc_ifu.v
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wire [3:0] ctu_sscan_tid; // To ifu of sparc_ifu.v
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// bist
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// bist
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wire ctu_tst_mbist_enable; // To test_stub of test_stub_bist.v
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wire ctu_tst_mbist_enable; // To test_stub of test_stub_bist.v
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// efuse
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// efuse
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wire efc_spc_fuse_clk1;
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wire efc_spc_fuse_clk1;
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wire efc_spc_fuse_clk2;
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wire efc_spc_fuse_clk2;
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wire efc_spc_ifuse_ashift;
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wire efc_spc_ifuse_ashift;
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wire efc_spc_ifuse_dshift;
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wire efc_spc_ifuse_dshift;
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wire efc_spc_ifuse_data;
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wire efc_spc_ifuse_data;
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wire efc_spc_dfuse_ashift;
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wire efc_spc_dfuse_ashift;
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wire efc_spc_dfuse_dshift;
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wire efc_spc_dfuse_dshift;
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wire efc_spc_dfuse_data;
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wire efc_spc_dfuse_data;
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// scan and macro test
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// scan and macro test
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wire ctu_tst_macrotest; // To test_stub of test_stub_bist.v
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wire ctu_tst_macrotest; // To test_stub of test_stub_bist.v
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wire ctu_tst_scan_disable; // To test_stub of test_stub_bist.v
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wire ctu_tst_scan_disable; // To test_stub of test_stub_bist.v
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wire ctu_tst_short_chain; // To test_stub of test_stub_bist.v
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wire ctu_tst_short_chain; // To test_stub of test_stub_bist.v
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wire global_shift_enable; // To test_stub of test_stub_two_bist.v
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wire global_shift_enable; // To test_stub of test_stub_two_bist.v
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wire ctu_tst_scanmode; // To test_stub of test_stub_two_bist.v
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wire ctu_tst_scanmode; // To test_stub of test_stub_two_bist.v
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wire spc_scanin0;
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wire spc_scanin0;
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wire spc_scanin1;
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wire spc_scanin1;
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// clk
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// clk
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wire cluster_cken; // To spc_hdr of cluster_header.v
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wire cluster_cken; // To spc_hdr of cluster_header.v
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wire gclk; // To spc_hdr of cluster_header.v
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wire gclk; // To spc_hdr of cluster_header.v
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// reset
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// reset
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wire cmp_grst_l;
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wire cmp_grst_l;
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wire cmp_arst_l;
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wire cmp_arst_l;
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wire ctu_tst_pre_grst_l; // To test_stub of test_stub_bist.v
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wire ctu_tst_pre_grst_l; // To test_stub of test_stub_bist.v
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wire adbginit_l; // To spc_hdr of cluster_header.v
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wire adbginit_l; // To spc_hdr of cluster_header.v
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wire gdbginit_l; // To spc_hdr of cluster_header.v
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wire gdbginit_l; // To spc_hdr of cluster_header.v
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// Reset signal from the reset controller to the bridge
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// Reset signal from the reset controller to the bridge
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wire sys_reset_final;
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wire sys_reset_final;
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// Interrupt Source from the interrupt controller to the bridge
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// Interrupt Source from the interrupt controller to the bridge
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wire[5:0] sys_interrupt_source;
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wire[5:0] sys_interrupt_source;
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// FIFO
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// FIFO
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reg [4:0] pcx_spc_grant_px_fifo;
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reg [4:0] pcx_spc_grant_px_fifo;
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`ifdef DMITRY
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`ifdef DMITRY
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// Floating-Point Unit
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// Floating-Point Unit
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wire fp_req;
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wire fp_req;
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wire [123:0] fp_pcx;
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wire [123:0] fp_pcx;
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wire [ 7:0] fp_rdy;
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wire [ 7:0] fp_rdy;
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wire [144:0] fp_cpx;
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wire [144:0] fp_cpx;
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`endif
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`endif
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/*
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/*
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* SPARC Core module instance
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* SPARC Core module instance
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*/
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*/
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sparc sparc_0 (
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sparc sparc_0 (
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// Wires connected to SPARC Core outputs
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// Wires connected to SPARC Core outputs
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.spc_pcx_req_pq(spc_pcx_req_pq),
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.spc_pcx_req_pq(spc_pcx_req_pq),
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.spc_pcx_atom_pq(spc_pcx_atom_pq),
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.spc_pcx_atom_pq(spc_pcx_atom_pq),
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.spc_pcx_data_pa(spc_pcx_data_pa),
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.spc_pcx_data_pa(spc_pcx_data_pa),
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.spc_sscan_so(spc_sscan_so),
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.spc_sscan_so(spc_sscan_so),
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.spc_scanout0(spc_scanout0),
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.spc_scanout0(spc_scanout0),
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.spc_scanout1(spc_scanout1),
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.spc_scanout1(spc_scanout1),
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.tst_ctu_mbist_done(tst_ctu_mbist_done),
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.tst_ctu_mbist_done(tst_ctu_mbist_done),
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.tst_ctu_mbist_fail(tst_ctu_mbist_fail),
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.tst_ctu_mbist_fail(tst_ctu_mbist_fail),
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.spc_efc_ifuse_data(spc_efc_ifuse_data),
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.spc_efc_ifuse_data(spc_efc_ifuse_data),
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.spc_efc_dfuse_data(spc_efc_dfuse_data),
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.spc_efc_dfuse_data(spc_efc_dfuse_data),
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// Wires connected to SPARC Core inputs
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// Wires connected to SPARC Core inputs
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.pcx_spc_grant_px(pcx_spc_grant_px),
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.pcx_spc_grant_px(pcx_spc_grant_px),
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.cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
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.cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
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.cpx_spc_data_cx2(cpx_spc_data_cx2),
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.cpx_spc_data_cx2(cpx_spc_data_cx2),
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.const_cpuid(const_cpuid),
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.const_cpuid(const_cpuid),
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.const_maskid(const_maskid),
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.const_maskid(const_maskid),
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.ctu_tck(ctu_tck),
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.ctu_tck(ctu_tck),
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.ctu_sscan_se(ctu_sscan_se),
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.ctu_sscan_se(ctu_sscan_se),
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.ctu_sscan_snap(ctu_sscan_snap),
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.ctu_sscan_snap(ctu_sscan_snap),
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.ctu_sscan_tid(ctu_sscan_tid),
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.ctu_sscan_tid(ctu_sscan_tid),
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.ctu_tst_mbist_enable(ctu_tst_mbist_enable),
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.ctu_tst_mbist_enable(ctu_tst_mbist_enable),
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.efc_spc_fuse_clk1(efc_spc_fuse_clk1),
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.efc_spc_fuse_clk1(efc_spc_fuse_clk1),
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.efc_spc_fuse_clk2(efc_spc_fuse_clk2),
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.efc_spc_fuse_clk2(efc_spc_fuse_clk2),
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.efc_spc_ifuse_ashift(efc_spc_ifuse_ashift),
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.efc_spc_ifuse_ashift(efc_spc_ifuse_ashift),
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.efc_spc_ifuse_dshift(efc_spc_ifuse_dshift),
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.efc_spc_ifuse_dshift(efc_spc_ifuse_dshift),
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.efc_spc_ifuse_data(efc_spc_ifuse_data),
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.efc_spc_ifuse_data(efc_spc_ifuse_data),
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.efc_spc_dfuse_ashift(efc_spc_dfuse_ashift),
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.efc_spc_dfuse_ashift(efc_spc_dfuse_ashift),
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.efc_spc_dfuse_dshift(efc_spc_dfuse_dshift),
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.efc_spc_dfuse_dshift(efc_spc_dfuse_dshift),
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.efc_spc_dfuse_data(efc_spc_dfuse_data),
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.efc_spc_dfuse_data(efc_spc_dfuse_data),
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.ctu_tst_macrotest(ctu_tst_macrotest),
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.ctu_tst_macrotest(ctu_tst_macrotest),
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.ctu_tst_scan_disable(ctu_tst_scan_disable),
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.ctu_tst_scan_disable(ctu_tst_scan_disable),
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.ctu_tst_short_chain(ctu_tst_short_chain),
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.ctu_tst_short_chain(ctu_tst_short_chain),
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.global_shift_enable(global_shift_enable),
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.global_shift_enable(global_shift_enable),
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.ctu_tst_scanmode(ctu_tst_scanmode),
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.ctu_tst_scanmode(ctu_tst_scanmode),
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.spc_scanin0(spc_scanin0),
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.spc_scanin0(spc_scanin0),
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.spc_scanin1(spc_scanin1),
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.spc_scanin1(spc_scanin1),
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.cluster_cken(cluster_cken),
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.cluster_cken(cluster_cken),
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.gclk(gclk),
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.gclk(gclk),
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.cmp_grst_l(cmp_grst_l),
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.cmp_grst_l(cmp_grst_l),
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.cmp_arst_l(cmp_arst_l),
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.cmp_arst_l(cmp_arst_l),
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.ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
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.ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
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.adbginit_l(adbginit_l),
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.adbginit_l(adbginit_l),
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.gdbginit_l(gdbginit_l)
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.gdbginit_l(gdbginit_l)
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);
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);
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/*
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/*
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* SPARC Core to Wishbone Master bridge
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* SPARC Core to Wishbone Master bridge
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*/
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*/
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`ifdef DMITRY
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`ifdef DMITRY
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os2wb os2wb_0 (
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os2wb os2wb_0 (
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// Top-level system inputs
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// Top-level system inputs
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.clk(sys_clock_i),
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.clk(sys_clock_i),
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.rstn(~sys_reset_final),
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.rstn(~sys_reset_final),
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// Bridge inputs connected to SPARC Core outputs
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// Bridge inputs connected to SPARC Core outputs
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.pcx_req(spc_pcx_req_pq),
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.pcx_req(spc_pcx_req_pq),
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.pcx_atom(spc_pcx_atom_pq),
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.pcx_atom(spc_pcx_atom_pq),
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.pcx_data(spc_pcx_data_pa),
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.pcx_data(spc_pcx_data_pa),
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// Bridge outputs connected to SPARC Core inputs
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// Bridge outputs connected to SPARC Core inputs
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.pcx_grant(pcx_spc_grant_px),
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.pcx_grant(pcx_spc_grant_px),
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.cpx_ready(cpx_spc_data_rdy_cx2),
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.cpx_ready(cpx_spc_data_rdy_cx2),
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.cpx_packet(cpx_spc_data_cx2),
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.cpx_packet(cpx_spc_data_cx2),
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// Top-level Wishbone Interconnect inputs
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// Top-level Wishbone Interconnect inputs
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.wb_data_i(wbm_data_i),
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.wb_data_i(wbm_data_i),
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.wb_ack(wbm_ack_i),
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.wb_ack(wbm_ack_i),
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// Top-level Wishbone Interconnect outputs
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// Top-level Wishbone Interconnect outputs
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.wb_cycle(wbm_cycle_o),
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.wb_cycle(wbm_cycle_o),
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.wb_strobe(wbm_strobe_o),
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.wb_strobe(wbm_strobe_o),
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.wb_we(wbm_we_o),
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.wb_we(wbm_we_o),
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.wb_sel(wbm_sel_o),
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.wb_sel(wbm_sel_o),
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.wb_addr(wbm_addr_o),
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.wb_addr(wbm_addr_o),
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.wb_data_o(wbm_data_o),
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.wb_data_o(wbm_data_o),
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.fp_pcx(fp_pcx),
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.fp_pcx(fp_pcx),
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.fp_req(fp_req),
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.fp_req(fp_req),
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.fp_cpx(fp_cpx),
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.fp_cpx(fp_cpx),
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.fp_rdy(fp_rdy!=8'h00),
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.fp_rdy(fp_rdy!=8'h00),
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.eth_int(sys_interrupt_source[0])
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.eth_int(sys_interrupt_source[0])
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);
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);
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`else
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`else
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spc2wbm spc2wbm_0 (
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spc2wbm spc2wbm_0 (
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// System inputs
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// System inputs
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.sys_clock_i(sys_clock_i),
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.sys_clock_i(sys_clock_i),
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.sys_reset_i(sys_reset_final),
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.sys_reset_i(sys_reset_final),
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.sys_interrupt_source_i(sys_interrupt_source),
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.sys_interrupt_source_i(sys_interrupt_source),
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// Bridge inputs connected to SPARC Core outputs
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// Bridge inputs connected to SPARC Core outputs
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.spc_req_i(spc_pcx_req_pq),
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.spc_req_i(spc_pcx_req_pq),
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.spc_atom_i(spc_pcx_atom_pq),
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.spc_atom_i(spc_pcx_atom_pq),
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.spc_packetout_i(spc_pcx_data_pa),
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.spc_packetout_i(spc_pcx_data_pa),
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// Bridge outputs connected to SPARC Core inputs
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// Bridge outputs connected to SPARC Core inputs
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.spc_grant_o(pcx_spc_grant_px),
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.spc_grant_o(pcx_spc_grant_px),
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.spc_ready_o(cpx_spc_data_rdy_cx2),
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.spc_ready_o(cpx_spc_data_rdy_cx2),
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.spc_packetin_o(cpx_spc_data_cx2),
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.spc_packetin_o(cpx_spc_data_cx2),
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// Top-level Wishbone Interconnect inputs
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// Top-level Wishbone Interconnect inputs
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.wbm_ack_i(wbm_ack_i),
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.wbm_ack_i(wbm_ack_i),
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.wbm_data_i(wbm_data_i),
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.wbm_data_i(wbm_data_i),
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|
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// Top-level Wishbone Interconnect outputs
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// Top-level Wishbone Interconnect outputs
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.wbm_cycle_o(wbm_cycle_o),
|
.wbm_cycle_o(wbm_cycle_o),
|
.wbm_strobe_o(wbm_strobe_o),
|
.wbm_strobe_o(wbm_strobe_o),
|
.wbm_we_o(wbm_we_o),
|
.wbm_we_o(wbm_we_o),
|
.wbm_addr_o(wbm_addr_o),
|
.wbm_addr_o(wbm_addr_o),
|
.wbm_data_o(wbm_data_o),
|
.wbm_data_o(wbm_data_o),
|
.wbm_sel_o(wbm_sel_o)
|
.wbm_sel_o(wbm_sel_o)
|
);
|
);
|
`endif
|
`endif
|
/*
|
/*
|
* Floating-Point Unit
|
* Floating-Point Unit
|
*/
|
*/
|
`ifdef DMITRY
|
`ifdef DMITRY
|
fpu fpu_0 (
|
fpu fpu_0 (
|
.pcx_fpio_data_rdy_px2(fp_req),
|
.pcx_fpio_data_rdy_px2(fp_req),
|
.pcx_fpio_data_px2(fp_pcx),
|
.pcx_fpio_data_px2(fp_pcx),
|
.arst_l(cmp_arst_l),
|
.arst_l(cmp_arst_l),
|
.grst_l(cmp_grst_l),
|
.grst_l(cmp_grst_l),
|
.gclk(gclk),
|
.gclk(gclk),
|
.cluster_cken(cluster_cken),
|
.cluster_cken(cluster_cken),
|
|
|
.fp_cpx_req_cq(fp_rdy),
|
.fp_cpx_req_cq(fp_rdy),
|
.fp_cpx_data_ca(fp_cpx),
|
.fp_cpx_data_ca(fp_cpx),
|
|
|
.ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
|
.ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
|
.global_shift_enable(global_shift_enable),
|
.global_shift_enable(global_shift_enable),
|
.ctu_tst_scan_disable(ctu_tst_scan_disable),
|
.ctu_tst_scan_disable(ctu_tst_scan_disable),
|
.ctu_tst_scanmode(ctu_tst_scanmode),
|
.ctu_tst_scanmode(ctu_tst_scanmode),
|
.ctu_tst_macrotest(ctu_tst_macrotest),
|
.ctu_tst_macrotest(ctu_tst_macrotest),
|
.ctu_tst_short_chain(ctu_tst_short_chain),
|
.ctu_tst_short_chain(ctu_tst_short_chain),
|
|
|
.si(1'b0),
|
.si(1'b0),
|
.so()
|
.so()
|
);
|
);
|
`endif
|
`endif
|
/*
|
/*
|
* Reset Controller
|
* Reset Controller
|
*/
|
*/
|
|
|
rst_ctrl rst_ctrl_0 (
|
rst_ctrl rst_ctrl_0 (
|
|
|
// Top-level system inputs
|
// Top-level system inputs
|
.sys_clock_i(sys_clock_i),
|
.sys_clock_i(sys_clock_i),
|
.sys_reset_i(sys_reset_i),
|
.sys_reset_i(sys_reset_i),
|
|
|
// Reset Controller outputs connected to SPARC Core inputs
|
// Reset Controller outputs connected to SPARC Core inputs
|
.cluster_cken_o(cluster_cken),
|
.cluster_cken_o(cluster_cken),
|
.gclk_o(gclk),
|
.gclk_o(gclk),
|
.cmp_grst_o(cmp_grst_l),
|
.cmp_grst_o(cmp_grst_l),
|
.cmp_arst_o(cmp_arst_l),
|
.cmp_arst_o(cmp_arst_l),
|
.ctu_tst_pre_grst_o(ctu_tst_pre_grst_l),
|
.ctu_tst_pre_grst_o(ctu_tst_pre_grst_l),
|
.adbginit_o(adbginit_l),
|
.adbginit_o(adbginit_l),
|
.gdbginit_o(gdbginit_l),
|
.gdbginit_o(gdbginit_l),
|
.sys_reset_final_o(sys_reset_final)
|
.sys_reset_final_o(sys_reset_final)
|
|
|
);
|
);
|
|
|
/*
|
/*
|
* Interrupt Controller
|
* Interrupt Controller
|
*/
|
*/
|
|
|
int_ctrl int_ctrl_0 (
|
int_ctrl int_ctrl_0 (
|
|
|
// Top-level system inputs
|
// Top-level system inputs
|
.sys_clock_i(sys_clock_i),
|
.sys_clock_i(sys_clock_i),
|
.sys_reset_i(sys_reset_final),
|
.sys_reset_i(sys_reset_final),
|
.sys_irq_i(sys_irq_i),
|
.sys_irq_i(sys_irq_i),
|
|
|
// Interrupt Controller outputs connected to bridge inputs
|
// Interrupt Controller outputs connected to bridge inputs
|
.sys_interrupt_source_o(sys_interrupt_source)
|
.sys_interrupt_source_o(sys_interrupt_source)
|
|
|
);
|
);
|
|
|
/*
|
/*
|
* Continuous assignments
|
* Continuous assignments
|
*/
|
*/
|
|
|
assign const_cpuid = 4'h0;
|
assign const_cpuid = 4'h0;
|
assign const_maskid = 8'h20;
|
assign const_maskid = 8'h20;
|
|
|
// sscan
|
// sscan
|
assign ctu_tck = 1'b0;
|
assign ctu_tck = 1'b0;
|
assign ctu_sscan_se = 1'b0;
|
assign ctu_sscan_se = 1'b0;
|
assign ctu_sscan_snap = 1'b0;
|
assign ctu_sscan_snap = 1'b0;
|
assign ctu_sscan_tid = 4'h1;
|
assign ctu_sscan_tid = 4'h1;
|
|
|
// bist
|
// bist
|
assign ctu_tst_mbist_enable = 1'b0;
|
assign ctu_tst_mbist_enable = 1'b0;
|
|
|
// efuse
|
// efuse
|
assign efc_spc_fuse_clk1 = 1'b0; // Activity
|
assign efc_spc_fuse_clk1 = 1'b0; // Activity
|
assign efc_spc_fuse_clk2 = 1'b0; // Activity
|
assign efc_spc_fuse_clk2 = 1'b0; // Activity
|
assign efc_spc_ifuse_ashift = 1'b0;
|
assign efc_spc_ifuse_ashift = 1'b0;
|
assign efc_spc_ifuse_dshift = 1'b0;
|
assign efc_spc_ifuse_dshift = 1'b0;
|
assign efc_spc_ifuse_data = 1'b0; // Activity
|
assign efc_spc_ifuse_data = 1'b0; // Activity
|
assign efc_spc_dfuse_ashift = 1'b0;
|
assign efc_spc_dfuse_ashift = 1'b0;
|
assign efc_spc_dfuse_dshift = 1'b0;
|
assign efc_spc_dfuse_dshift = 1'b0;
|
assign efc_spc_dfuse_data = 1'b0; // Activity
|
assign efc_spc_dfuse_data = 1'b0; // Activity
|
|
|
// scan and macro test
|
// scan and macro test
|
assign ctu_tst_macrotest = 1'b0;
|
assign ctu_tst_macrotest = 1'b0;
|
assign ctu_tst_scan_disable = 1'b0;
|
assign ctu_tst_scan_disable = 1'b0;
|
assign ctu_tst_short_chain = 1'b0;
|
assign ctu_tst_short_chain = 1'b0;
|
assign global_shift_enable = 1'b0;
|
assign global_shift_enable = 1'b0;
|
assign ctu_tst_scanmode = 1'b0;
|
assign ctu_tst_scanmode = 1'b0;
|
assign spc_scanin0 = 1'b0;
|
assign spc_scanin0 = 1'b0;
|
assign spc_scanin1 = 1'b0;
|
assign spc_scanin1 = 1'b0;
|
|
|
endmodule
|
endmodule
|
|
|