// Empty module for cacheless Simply RISC S1 Core
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// Empty module for cacheless S1 Core
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module bw_r_idct(rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so, rclk, se,
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module bw_r_idct(rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so, rclk, se,
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si, reset_l, sehold, rst_tri_en, index0_x, index1_x, index_sel_x,
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si, reset_l, sehold, rst_tri_en, index0_x, index1_x, index_sel_x,
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dec_wrway_x, rdreq_x, wrreq_x, wrtag_w0_y, wrtag_w1_y, wrtag_w2_y,
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dec_wrway_x, rdreq_x, wrreq_x, wrtag_w0_y, wrtag_w1_y, wrtag_w2_y,
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wrtag_w3_y, adj);
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wrtag_w3_y, adj);
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input rclk;
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input rclk;
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input se;
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input se;
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input si;
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input si;
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input reset_l;
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input reset_l;
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input sehold;
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input sehold;
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input rst_tri_en;
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input rst_tri_en;
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input [6:0] index0_x;
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input [6:0] index0_x;
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input [6:0] index1_x;
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input [6:0] index1_x;
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input index_sel_x;
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input index_sel_x;
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input [3:0] dec_wrway_x;
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input [3:0] dec_wrway_x;
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input rdreq_x;
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input rdreq_x;
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input wrreq_x;
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input wrreq_x;
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input [32:0] wrtag_w0_y;
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input [32:0] wrtag_w0_y;
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input [32:0] wrtag_w1_y;
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input [32:0] wrtag_w1_y;
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input [32:0] wrtag_w2_y;
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input [32:0] wrtag_w2_y;
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input [32:0] wrtag_w3_y;
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input [32:0] wrtag_w3_y;
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input [3:0] adj;
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input [3:0] adj;
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output [32:0] rdtag_w0_y;
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output [32:0] rdtag_w0_y;
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output [32:0] rdtag_w1_y;
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output [32:0] rdtag_w1_y;
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output [32:0] rdtag_w2_y;
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output [32:0] rdtag_w2_y;
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output [32:0] rdtag_w3_y;
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output [32:0] rdtag_w3_y;
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output so;
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output so;
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endmodule
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endmodule
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