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-- Company: OPL Aerospatiale AG
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-- Company: OPL Aerospatiale AG
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-- Engineer: Owen Lynn <lynn0p@hotmail.com>
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-- Engineer: Owen Lynn <lynn0p@hotmail.com>
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--
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--
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-- Create Date: 16:30:07 09/03/2009
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-- Create Date: 16:30:07 09/03/2009
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-- Design Name:
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-- Design Name:
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-- Module Name: sdram_reader - impl
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-- Module Name: sdram_reader - impl
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description: Logic to capture data from the chip after issuing a read command.
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-- Description: Logic to capture data from the chip after issuing a read command.
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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-- Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>
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-- Copyright (c) 2009 Owen Lynn <lynn0p@hotmail.com>
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-- Released under the GNU Lesser General Public License, Version 3
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-- Released under the GNU Lesser General Public License, Version 3
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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-- I strongly suggest you run this in the post-PAR simulator first and then start making changes to it
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-- I strongly suggest you run this in the post-PAR simulator first and then start making changes to it
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-- after looking at what goes on at the post-PAR level. Don't say I didn't warn you.
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-- after looking at what goes on at the post-PAR level. Don't say I didn't warn you.
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-- Why didn't I use the IDDR2 primitives? Map'nPack keeps bitching about how it won't fit into the IOBs
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-- Why didn't I use the IDDR2 primitives? Map'nPack keeps bitching about how it won't fit into the IOBs
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-- with the ODDR2 primitives. I decided the ODDR2s were more important to keep.
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-- with the ODDR2 primitives. I decided the ODDR2s were more important to keep.
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-- I'm just capturing the front side of the burst, and letting the back side of the burst fall on the
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-- I'm just capturing the front side of the burst, and letting the back side of the burst fall on the
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-- floor. If you want to support both sides of the 2 burst or bigger bursts, you'll need to rework this.
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-- floor. If you want to support both sides of the 2 burst or bigger bursts, you'll need to rework this.
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entity sdram_reader is
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entity sdram_reader is
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port(
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port(
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clk000 : in std_logic;
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clk270 : in std_logic;
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clk270 : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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dq : in std_logic_vector(15 downto 0);
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dq : in std_logic_vector(15 downto 0);
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data0 : out std_logic_vector(7 downto 0);
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data0 : out std_logic_vector(7 downto 0);
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data1 : out std_logic_vector(7 downto 0)
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data1 : out std_logic_vector(7 downto 0)
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);
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);
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end sdram_reader;
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end sdram_reader;
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architecture impl of sdram_reader is
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architecture impl of sdram_reader is
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type FSM0_STATES is ( FSM0_START, FSM0_WAIT0, FSM0_CAPTURE, FSM0_END );
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type FSM0_STATES is ( FSM0_START, FSM0_WAIT0, FSM0_CAPTURE, FSM0_END );
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signal fsm0_state : FSM0_STATES;
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signal fsm0_state : FSM0_STATES;
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signal reg0 : std_logic_vector(7 downto 0);
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signal reg0 : std_logic_vector(7 downto 0);
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signal reg1 : std_logic_vector(7 downto 0);
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signal reg1 : std_logic_vector(7 downto 0);
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begin
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begin
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data0 <= reg0;
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data0 <= reg0;
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data1 <= reg1;
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data1 <= reg1;
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process(clk270,rst)
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process(clk270,rst)
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begin
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begin
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if (rst = '1') then
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if (rst = '1') then
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fsm0_state <= FSM0_START;
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fsm0_state <= FSM0_START;
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elsif (rising_edge(clk270)) then
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elsif (rising_edge(clk270)) then
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case fsm0_state is
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case fsm0_state is
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when FSM0_START =>
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when FSM0_START =>
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fsm0_state <= FSM0_WAIT0;
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fsm0_state <= FSM0_WAIT0;
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when FSM0_WAIT0 =>
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when FSM0_WAIT0 =>
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fsm0_state <= FSM0_CAPTURE;
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fsm0_state <= FSM0_CAPTURE;
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when FSM0_CAPTURE =>
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when FSM0_CAPTURE =>
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reg0 <= dq(7 downto 0);
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reg0 <= dq(7 downto 0);
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reg1 <= dq(15 downto 8);
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reg1 <= dq(15 downto 8);
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fsm0_state <= FSM0_END;
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fsm0_state <= FSM0_END;
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when others =>
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when others =>
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fsm0_state <= fsm0_state;
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fsm0_state <= fsm0_state;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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