////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: llsdspi.v
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// Filename: llsdspi.v
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//
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//
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// Project: SD-Card controller, using a shared SPI interface
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// Project: SD-Card controller, using a shared SPI interface
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//
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//
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// Purpose: This file implements the "lower-level" interface to the
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// Purpose: This file implements the "lower-level" interface to the
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// SD-Card controller. Specifically, it turns byte-level
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// SD-Card controller. Specifically, it turns byte-level
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// interaction requests into SPI bit-wise interactions. Further, it
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// interaction requests into SPI bit-wise interactions. Further, it
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// handles the request and grant for the SPI wires (i.e., it requests
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// handles the request and grant for the SPI wires (i.e., it requests
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// the SPI port by pulling o_cs_n low, and then waits for i_bus_grant
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// the SPI port by pulling o_cs_n low, and then waits for i_bus_grant
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// to be true before continuing.). Finally, the speed/clock rate of the
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// to be true before continuing.). Finally, the speed/clock rate of the
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// communication is adjustable as a division of the current clock rate.
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// communication is adjustable as a division of the current clock rate.
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//
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//
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// i_speed
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// i_speed
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// This is the number of clocks (minus one) between SPI clock
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// This is the number of clocks (minus one) between SPI clock
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// transitions. Hence a '0' (not tested, doesn't work) would
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// transitions. Hence a '0' (not tested, doesn't work) would
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// result in a SPI clock that alternated on every input clock
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// result in a SPI clock that alternated on every input clock
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// equivalently dividing the input clock by two, whereas a '1'
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// equivalently dividing the input clock by two, whereas a '1'
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// would divide the input clock by four.
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// would divide the input clock by four.
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//
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//
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// In general, the SPI clock frequency will be given by the
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// In general, the SPI clock frequency will be given by the
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// master clock frequency divided by twice this number plus one.
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// master clock frequency divided by twice this number plus one.
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// In other words,
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// In other words,
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//
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//
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// SPIFREQ=(i_clk FREQ) / (2*(i_speed+1))
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// SPIFREQ=(i_clk FREQ) / (2*(i_speed+1))
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//
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//
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// i_stb
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// i_stb
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// True if the master controller is requesting to send a byte.
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// True if the master controller is requesting to send a byte.
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// This will be ignored unless o_idle is false.
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// This will be ignored unless o_idle is false.
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//
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//
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// i_byte
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// i_byte
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// The byte that the master controller wishes to send across the
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// The byte that the master controller wishes to send across the
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// interface.
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// interface.
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//
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//
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// (The external SPI interface)
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// (The external SPI interface)
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//
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//
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// o_stb
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// o_stb
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// Only true for one clock--when a byte is valid coming in from the
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// Only true for one clock--when a byte is valid coming in from the
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// interface, this will be true for one clock (a strobe) indicating
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// interface, this will be true for one clock (a strobe) indicating
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// that a valid byte is ready to be read.
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// that a valid byte is ready to be read.
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//
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//
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// o_byte
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// o_byte
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// The value of the byte coming in.
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// The value of the byte coming in.
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//
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//
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// o_idle
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// o_idle
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// True if this low-level device handler is ready to accept a
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// True if this low-level device handler is ready to accept a
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// byte from the incoming interface, false otherwise.
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// byte from the incoming interface, false otherwise.
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//
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//
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// i_bus_grant
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// i_bus_grant
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// True if the SPI bus has been granted to this interface, false
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// True if the SPI bus has been granted to this interface, false
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// otherwise. This has been placed here so that the interface of
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// otherwise. This has been placed here so that the interface of
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// the XuLA2 board may be shared between SPI-Flash and the SPI
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// the XuLA2 board may be shared between SPI-Flash and the SPI
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// based SDCard. An external arbiter will determine which of the
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// based SDCard. An external arbiter will determine which of the
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// two gets to control the clock and mosi outputs given their
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// two gets to control the clock and mosi outputs given their
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// cs_n requests. If control is not granted, i_bus_grant will
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// cs_n requests. If control is not granted, i_bus_grant will
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// remain low as will the actual cs_n going out of the FPGA.
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// remain low as will the actual cs_n going out of the FPGA.
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//
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`default_nettype none
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//
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`define LLSDSPI_IDLE 4'h0
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`define LLSDSPI_IDLE 4'h0
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`define LLSDSPI_HOTIDLE 4'h1
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`define LLSDSPI_HOTIDLE 4'h1
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`define LLSDSPI_WAIT 4'h2
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`define LLSDSPI_WAIT 4'h2
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`define LLSDSPI_START 4'h3
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`define LLSDSPI_START 4'h3
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//
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//
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module llsdspi(i_clk, i_speed, i_cs, i_stb, i_byte,
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module llsdspi(i_clk, i_speed, i_cs, i_stb, i_byte,
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o_cs_n, o_sclk, o_mosi, i_miso,
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o_cs_n, o_sclk, o_mosi, i_miso,
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o_stb, o_byte, o_idle, i_bus_grant);
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o_stb, o_byte, o_idle, i_bus_grant);
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parameter SPDBITS = 7;
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parameter SPDBITS = 7;
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//
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//
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input i_clk;
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input wire i_clk;
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// Parameters/setup
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// Parameters/setup
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input [(SPDBITS-1):0] i_speed;
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input wire [(SPDBITS-1):0] i_speed;
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// The incoming interface
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// The incoming interface
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input i_cs;
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input wire i_cs;
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input i_stb;
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input wire i_stb;
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input [7:0] i_byte;
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input wire [7:0] i_byte;
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// The actual SPI interface
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// The actual SPI interface
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output reg o_cs_n, o_sclk, o_mosi;
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output reg o_cs_n, o_sclk, o_mosi;
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input i_miso;
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input wire i_miso;
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// The outgoing interface
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// The outgoing interface
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output reg o_stb;
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output reg o_stb;
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output reg [7:0] o_byte;
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output reg [7:0] o_byte;
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output wire o_idle;
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output wire o_idle;
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// And whether or not we actually own the interface (yet)
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// And whether or not we actually own the interface (yet)
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input i_bus_grant;
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input wire i_bus_grant;
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reg r_z_counter;
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reg r_z_counter;
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reg [(SPDBITS-1):0] r_clk_counter;
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reg [(SPDBITS-1):0] r_clk_counter;
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reg r_idle;
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reg r_idle;
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reg [3:0] r_state;
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reg [3:0] r_state;
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reg [7:0] r_byte, r_ireg;
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reg [7:0] r_byte, r_ireg;
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wire byte_accepted;
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wire byte_accepted;
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assign byte_accepted = (i_stb)&&(o_idle);
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assign byte_accepted = (i_stb)&&(o_idle);
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initial r_clk_counter = 7'h0;
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initial r_clk_counter = 7'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((~i_cs)||(~i_bus_grant))
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if ((!i_cs)||(!i_bus_grant))
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r_clk_counter <= 0;
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r_clk_counter <= 0;
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else if (byte_accepted)
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else if (byte_accepted)
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r_clk_counter <= i_speed;
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r_clk_counter <= i_speed;
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else if (~r_z_counter)
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else if (!r_z_counter)
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r_clk_counter <= (r_clk_counter - {{(SPDBITS-1){1'b0}},1'b1});
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r_clk_counter <= (r_clk_counter - {{(SPDBITS-1){1'b0}},1'b1});
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else if ((r_state != `LLSDSPI_IDLE)&&(r_state != `LLSDSPI_HOTIDLE))
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else if ((r_state != `LLSDSPI_IDLE)&&(r_state != `LLSDSPI_HOTIDLE))
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r_clk_counter <= (i_speed);
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r_clk_counter <= (i_speed);
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// else
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// else
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// r_clk_counter <= 16'h00;
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// r_clk_counter <= 16'h00;
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end
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end
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initial r_z_counter = 1'b1;
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initial r_z_counter = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((~i_cs)||(~i_bus_grant))
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if ((!i_cs)||(!i_bus_grant))
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r_z_counter <= 1'b1;
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r_z_counter <= 1'b1;
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else if (byte_accepted)
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else if (byte_accepted)
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r_z_counter <= 1'b0;
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r_z_counter <= 1'b0;
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else if (~r_z_counter)
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else if (!r_z_counter)
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r_z_counter <= (r_clk_counter == 1);
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r_z_counter <= (r_clk_counter == 1);
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else if ((r_state != `LLSDSPI_IDLE)&&(r_state != `LLSDSPI_HOTIDLE))
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else if ((r_state != `LLSDSPI_IDLE)&&(r_state != `LLSDSPI_HOTIDLE))
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r_z_counter <= 1'b0;
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r_z_counter <= 1'b0;
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end
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end
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initial r_state = `LLSDSPI_IDLE;
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initial r_state = `LLSDSPI_IDLE;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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o_stb <= 1'b0;
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o_stb <= 1'b0;
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o_cs_n <= ~i_cs;
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o_cs_n <= !i_cs;
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if (~i_cs)
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if (!i_cs)
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begin
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begin
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r_state <= `LLSDSPI_IDLE;
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r_state <= `LLSDSPI_IDLE;
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r_idle <= 1'b0;
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r_idle <= 1'b0;
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o_sclk <= 1'b1;
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o_sclk <= 1'b1;
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end else if (~r_z_counter)
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end else if (!r_z_counter)
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begin
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begin
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r_idle <= 1'b0;
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r_idle <= 1'b0;
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if (byte_accepted)
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if (byte_accepted)
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begin // Will only happen within a hot idle state
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begin // Will only happen within a hot idle state
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r_byte <= { i_byte[6:0], 1'b1 };
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r_byte <= { i_byte[6:0], 1'b1 };
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r_state <= `LLSDSPI_START+1;
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r_state <= `LLSDSPI_START+1;
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o_mosi <= i_byte[7];
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o_mosi <= i_byte[7];
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end
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end
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end else if (r_state == `LLSDSPI_IDLE)
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end else if (r_state == `LLSDSPI_IDLE)
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begin
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begin
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o_sclk <= 1'b1;
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o_sclk <= 1'b1;
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if (byte_accepted)
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if (byte_accepted)
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begin
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begin
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r_byte <= i_byte[7:0];
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r_byte <= i_byte[7:0];
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r_state <= (i_bus_grant)?`LLSDSPI_START:`LLSDSPI_WAIT;
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r_state <= (i_bus_grant)?`LLSDSPI_START:`LLSDSPI_WAIT;
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r_idle <= 1'b0;
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r_idle <= 1'b0;
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o_mosi <= i_byte[7];
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o_mosi <= i_byte[7];
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end else begin
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end else begin
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r_idle <= 1'b1;
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r_idle <= 1'b1;
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end
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end
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end else if (r_state == `LLSDSPI_WAIT)
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end else if (r_state == `LLSDSPI_WAIT)
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begin
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begin
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r_idle <= 1'b0;
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r_idle <= 1'b0;
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if (i_bus_grant)
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if (i_bus_grant)
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r_state <= `LLSDSPI_START;
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r_state <= `LLSDSPI_START;
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end else if (r_state == `LLSDSPI_HOTIDLE)
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end else if (r_state == `LLSDSPI_HOTIDLE)
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begin
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begin
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// The clock is low, the bus is granted, we're just
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// The clock is low, the bus is granted, we're just
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// waiting for the next byte to transmit
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// waiting for the next byte to transmit
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o_sclk <= 1'b0;
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o_sclk <= 1'b0;
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if (byte_accepted)
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if (byte_accepted)
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begin
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begin
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r_byte <= i_byte[7:0];
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r_byte <= i_byte[7:0];
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r_state <= `LLSDSPI_START;
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r_state <= `LLSDSPI_START;
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r_idle <= 1'b0;
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r_idle <= 1'b0;
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o_mosi <= i_byte[7];
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o_mosi <= i_byte[7];
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end else
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end else
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r_idle <= 1'b1;
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r_idle <= 1'b1;
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// end else if (r_state == `LLSDSPI_START)
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// end else if (r_state == `LLSDSPI_START)
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// begin
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// begin
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// o_sclk <= 1'b0;
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// o_sclk <= 1'b0;
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// r_state <= r_state + 1;
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// r_state <= r_state + 1;
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end else if (o_sclk)
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end else if (o_sclk)
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begin
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begin
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o_mosi <= r_byte[7];
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o_mosi <= r_byte[7];
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r_byte <= { r_byte[6:0], 1'b1 };
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r_byte <= { r_byte[6:0], 1'b1 };
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r_state <= r_state + 1;
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r_state <= r_state + 1;
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o_sclk <= 1'b0;
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o_sclk <= 1'b0;
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if (r_state >= `LLSDSPI_START+8)
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if (r_state >= `LLSDSPI_START+8)
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begin
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begin
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r_state <= `LLSDSPI_HOTIDLE;
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r_state <= `LLSDSPI_HOTIDLE;
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r_idle <= 1'b1;
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r_idle <= 1'b1;
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o_stb <= 1'b1;
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o_stb <= 1'b1;
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o_byte <= r_ireg;
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o_byte <= r_ireg;
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end else
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end else
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r_state <= r_state + 1;
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r_state <= r_state + 1;
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end else begin
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end else begin
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r_ireg <= { r_ireg[6:0], i_miso };
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r_ireg <= { r_ireg[6:0], i_miso };
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o_sclk <= 1'b1;
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o_sclk <= 1'b1;
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end
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end
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end
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end
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assign o_idle = (r_idle)&&( (i_cs)&&(i_bus_grant) );
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assign o_idle = (r_idle)&&( (i_cs)&&(i_bus_grant) );
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endmodule
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endmodule
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