URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 134 |
Rev 135 |
|
|
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
Mos6502
|
Mos6502
|
cpu
|
cpu
|
def_tb
|
def_tb
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
gen_verilog
|
104.0
|
104.0
|
none
|
none
|
common
|
:*common:*
|
./tools/verilog/gen_verilog
|
tools/verilog/gen_verilog
|
|
|
|
|
destination
|
destination
|
cpu_def_tb
|
cpu_def_tb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VEC_TABLE8'hff
|
VEC_TABLE8'hff
|
BOOT_VEC8'hfc
|
BOOT_VEC8'hfc
|
CPU_ADD16
|
CPU_ADD16
|
UART_MODEL_CLKCNT4'b1100
|
UART_MODEL_CLKCNT4'b1100
|
UART_MODEL_SIZE4
|
UART_MODEL_SIZE4
|
STARTUP"NONE"
|
STARTUP"NONE"
|
FONT"NONE"
|
FONT"NONE"
|
RAM_ADD11
|
RAM_ADD11
|
RAM_WORDS2048
|
RAM_WORDS2048
|
ROM_ADD12
|
ROM_ADD12
|
ROM_WORDS4096
|
ROM_WORDS4096
|
ROM_FILE"NONE"
|
ROM_FILE"NONE"
|
PROG_ROM_ADDROM_ADD
|
PROG_ROM_ADDROM_ADD
|
PROG_ROM_WORDSROM_WORDS
|
PROG_ROM_WORDSROM_WORDS
|
PROG_ROM_FILEROM_FILE
|
PROG_ROM_FILEROM_FILE
|
|
|
|
|
|
|
|
|
|
|
|
|
Dut
|
Dut
|
|
|
|
|
spirit:library="Mos6502"
|
ipxact:library="Mos6502"
|
spirit:name="cpu"
|
ipxact:name="cpu"
|
spirit:version="def_dut.params"/>
|
ipxact:version="def_dut.params"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
Bfm
|
Bfm
|
|
|
spirit:library="Mos6502"
|
ipxact:library="Mos6502"
|
spirit:name="cpu"
|
ipxact:name="cpu"
|
spirit:version="bfm.design"/>
|
ipxact:version="bfm.design"/>
|
|
|
|
|
|
|
|
|
icarus
|
icarus
|
|
|
|
|
spirit:library="Testbench"
|
ipxact:library="Testbench"
|
spirit:name="toolflow"
|
ipxact:name="toolflow"
|
spirit:version="icarus"/>
|
ipxact:version="icarus"/>
|
|
|
|
|
|
|
|
|
|
|
commoncommon
|
common:*common:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-common
|
fs-common
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
sim:*Simulation:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
lint:*Lint:*
|
lint:*Lint:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-lint
|
fs-lint
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
fs-common
|
|
|
|
|
|
|
|
|
../verilog/sram.load
|
../verilog/sram.load
|
verilogSourcefragment
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
../verilog/top.rtl
|
../verilog/top.rtl
|
verilogSourcefragment
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
../verilog/top.irq
|
../verilog/top.irq
|
verilogSourcefragment
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
../verilog/common/cpu_def_tb
|
../verilog/common/cpu_def_tb
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-lint
|
fs-lint
|
|
|
|
|
|
|
|
|
|
|
../verilog/common/cpu_def_tb
|
../verilog/common/cpu_def_tb
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.