/**********************************************************************/
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/**********************************************************************/
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/* */
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/* */
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/* */
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/* */
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/* Copyright (c) 2012 Ouabache Design Works */
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/* Copyright (c) 2012 Ouabache Design Works */
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/* */
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/* */
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/* All Rights Reserved Worldwide */
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/* All Rights Reserved Worldwide */
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/* */
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/* */
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/* Licensed under the Apache License,Version2.0 (the'License'); */
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/* Licensed under the Apache License,Version2.0 (the'License'); */
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/* you may not use this file except in compliance with the License. */
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/* you may not use this file except in compliance with the License. */
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/* You may obtain a copy of the License at */
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/* You may obtain a copy of the License at */
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/* */
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/* */
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/* http://www.apache.org/licenses/LICENSE-2.0 */
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/* http://www.apache.org/licenses/LICENSE-2.0 */
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/* */
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/* */
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/* Unless required by applicable law or agreed to in */
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/* Unless required by applicable law or agreed to in */
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/* writing, software distributed under the License is */
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/* writing, software distributed under the License is */
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/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */
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/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */
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/* OR CONDITIONS OF ANY KIND, either express or implied. */
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/* OR CONDITIONS OF ANY KIND, either express or implied. */
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/* See the License for the specific language governing */
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/* See the License for the specific language governing */
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/* permissions and limitations under the License. */
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/* permissions and limitations under the License. */
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/**********************************************************************/
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/**********************************************************************/
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module
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module
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cde_jtag_tap
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cde_jtag_tap
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#( parameter
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#( parameter
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BYPASS=4'b1111,
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BYPASS=4'b1111,
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CHIP_ID_ACCESS=4'b0011,
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CHIP_ID_ACCESS=4'b0011,
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CHIP_ID_VAL=32'h12345678,
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CHIP_ID_VAL=32'h12345678,
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CLAMP=4'b1000,
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CLAMP=4'b1000,
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EXTEST=4'b0000,
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EXTEST=4'b0000,
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HIGHZ_MODE=4'b0010,
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HIGHZ_MODE=4'b0010,
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INST_LENGTH=4,
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INST_LENGTH=4,
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INST_RESET=4'b1111,
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INST_RESET=4'b1111,
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INST_RETURN=4'b1101,
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INST_RETURN=4'b1101,
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NUM_USER=2,
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NUM_USER=2,
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RPC_ADD=4'b1001,
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RPC_ADD=4'b1001,
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RPC_DATA=4'b1010,
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RPC_DATA=4'b1010,
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SAMPLE=4'b0001,
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SAMPLE=4'b0001,
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USER=8'b1010_1001)
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USER=8'b1010_1001)
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(
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(
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input wire aux_tdo_i,
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input wire aux_tdo_i,
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input wire bsr_tdo_i,
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input wire bsr_tdo_i,
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input wire tclk_pad_in,
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input wire tclk_pad_in,
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input wire tdi_pad_in,
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input wire tdi_pad_in,
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input wire tdo_i,
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input wire tdo_i,
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input wire tms_pad_in,
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input wire tms_pad_in,
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input wire trst_n_pad_in,
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input wire trst_n_pad_in,
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output reg bsr_output_mode,
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output reg bsr_output_mode,
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output reg capture_dr_o,
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output reg capture_dr_o,
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output reg shift_dr_o,
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output reg shift_dr_o,
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output reg tap_highz_mode,
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output reg tap_highz_mode,
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output reg test_logic_reset_o,
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output reg test_logic_reset_o,
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output reg update_dr_o,
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output reg update_dr_o,
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output wire aux_capture_dr_o,
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output wire aux_capture_dr_o,
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output wire aux_select_o,
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output wire aux_select_o,
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output wire aux_shift_dr_o,
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output wire aux_shift_dr_o,
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output wire aux_shiftcapture_dr_clk_o,
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output wire aux_shiftcapture_dr_clk_o,
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output wire aux_tdi_o,
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output wire aux_tdi_o,
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output wire aux_test_logic_reset_o,
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output wire aux_test_logic_reset_o,
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output wire aux_update_dr_clk_o,
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output wire aux_update_dr_clk_o,
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output wire tdi_o,
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output wire tdi_o,
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output wire select_o,
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output wire select_o,
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output wire tdo_pad_oe,
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output wire tdo_pad_oe,
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output wire tdo_pad_out,
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output wire tdo_pad_out,
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output wire jtag_clk,
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output wire jtag_clk,
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output wire update_dr_clk_o,
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output wire update_dr_clk_o,
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output wire shiftcapture_dr_clk_o,
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output wire shiftcapture_dr_clk_o,
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output wire bsr_select_o
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output wire bsr_select_o
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);
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);
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reg bypass_tdo;
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reg bypass_tdo;
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reg capture_ir;
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reg capture_ir;
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reg next_tdo;
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reg next_tdo;
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reg shift_ir;
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reg shift_ir;
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reg update_ir;
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reg update_ir;
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reg [ 3 : 0] next_tap_state;
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reg [ 3 : 0] next_tap_state;
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reg [ 3 : 0] tap_state;
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reg [ 3 : 0] tap_state;
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wire bypass_select;
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wire bypass_select;
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wire chip_id_select;
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wire chip_id_select;
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wire chip_id_tdo;
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wire chip_id_tdo;
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wire clamp;
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wire clamp;
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wire extest;
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wire extest;
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wire sample;
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wire sample;
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wire tclk;
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wire tclk;
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wire tclk_n;
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wire tclk_n;
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wire trst_pad_in;
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wire trst_pad_in;
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wire jtag_shift_clk;
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wire jtag_shift_clk;
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wire aux_update_dr_o;
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wire aux_update_dr_o;
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wire aux_jtag_clk;
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wire aux_jtag_clk;
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////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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cde_clock_gater
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cde_clock_gater
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clk_gater_jtag_shift_clk
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clk_gater_jtag_shift_clk
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(
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(
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.atg_clk_mode (1'b0),
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.atg_clk_mode (1'b0),
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.clk_in (tclk),
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.clk_in (tclk),
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.clk_out (jtag_shift_clk),
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.clk_out (jtag_shift_clk),
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.enable (shiftcapture_dr));
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.enable (shiftcapture_dr));
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cde_clock_gater
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cde_clock_gater
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clk_gater_jtag_update_clk
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clk_gater_jtag_update_clk
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(
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(
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.atg_clk_mode (1'b0),
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.atg_clk_mode (1'b0),
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.clk_in (tclk),
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.clk_in (tclk),
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.clk_out (update_dr_clk_o),
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.clk_out (update_dr_clk_o),
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.enable (update_dr_o));
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.enable (update_dr_o));
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cde_clock_gater
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cde_clock_gater
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clk_gater_jtag_clk
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clk_gater_jtag_clk
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(
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(
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.atg_clk_mode (1'b0),
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.atg_clk_mode (1'b0),
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.clk_in (tclk),
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.clk_in (tclk),
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.clk_out (jtag_clk),
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.clk_out (jtag_clk),
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.enable (1'b1));
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.enable (1'b1));
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cde_jtag_rpc_in_reg
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cde_jtag_rpc_in_reg
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#( .BITS (32),
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#( .BITS (32),
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.RESET_VALUE (CHIP_ID_VAL))
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.RESET_VALUE (CHIP_ID_VAL))
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chip_id_reg
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chip_id_reg
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(
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(
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.capture_dr (capture_dr_o),
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.capture_dr (capture_dr_o),
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.capture_value (CHIP_ID_VAL),
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.capture_value (CHIP_ID_VAL),
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.clk (jtag_clk),
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.clk (jtag_clk),
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.reset (trst_pad_in),
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.reset (trst_pad_in),
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.select (chip_id_select),
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.select (chip_id_select),
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.shift_dr (shift_dr_o),
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.shift_dr (shift_dr_o),
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.tdi (tdi_pad_in),
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.tdi (tdi_pad_in),
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.tdo (chip_id_tdo));
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.tdo (chip_id_tdo));
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//********************************************************************
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//********************************************************************
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//*** assignments for 2nd channel
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//*** assignments for 2nd channel
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//********************************************************************
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//********************************************************************
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assign aux_jtag_clk = jtag_clk;
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assign aux_jtag_clk = jtag_clk;
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assign aux_update_dr_clk_o = update_dr_clk_o;
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assign aux_update_dr_clk_o = update_dr_clk_o;
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assign aux_shiftcapture_dr_clk_o = shiftcapture_dr_clk_o;
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assign aux_shiftcapture_dr_clk_o = shiftcapture_dr_clk_o;
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assign aux_test_logic_reset_o = test_logic_reset_o;
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assign aux_test_logic_reset_o = test_logic_reset_o;
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assign aux_tdi_o = tdi_o;
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assign aux_tdi_o = tdi_o;
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assign aux_capture_dr_o = capture_dr_o;
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assign aux_capture_dr_o = capture_dr_o;
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assign aux_shift_dr_o = shift_dr_o;
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assign aux_shift_dr_o = shift_dr_o;
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assign aux_update_dr_o = update_dr_o;
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assign aux_update_dr_o = update_dr_o;
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//********************************************************************
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//********************************************************************
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//*** TAP Controller State Machine
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//*** TAP Controller State Machine
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//********************************************************************
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//********************************************************************
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// TAP state parameters
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// TAP state parameters
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localparam TEST_LOGIC_RESET = 4'b1111,
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localparam TEST_LOGIC_RESET = 4'b1111,
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RUN_TEST_IDLE = 4'b1100,
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RUN_TEST_IDLE = 4'b1100,
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SELECT_DR_SCAN = 4'b0111,
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SELECT_DR_SCAN = 4'b0111,
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CAPTURE_DR = 4'b0110,
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CAPTURE_DR = 4'b0110,
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SHIFT_DR = 4'b0010,
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SHIFT_DR = 4'b0010,
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EXIT1_DR = 4'b0001,
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EXIT1_DR = 4'b0001,
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PAUSE_DR = 4'b0011,
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PAUSE_DR = 4'b0011,
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EXIT2_DR = 4'b0000,
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EXIT2_DR = 4'b0000,
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UPDATE_DR = 4'b0101,
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UPDATE_DR = 4'b0101,
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SELECT_IR_SCAN = 4'b0100,
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SELECT_IR_SCAN = 4'b0100,
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CAPTURE_IR = 4'b1110,
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CAPTURE_IR = 4'b1110,
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SHIFT_IR = 4'b1010,
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SHIFT_IR = 4'b1010,
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EXIT1_IR = 4'b1001,
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EXIT1_IR = 4'b1001,
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PAUSE_IR = 4'b1011,
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PAUSE_IR = 4'b1011,
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EXIT2_IR = 4'b1000,
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EXIT2_IR = 4'b1000,
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UPDATE_IR = 4'b1101;
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UPDATE_IR = 4'b1101;
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// next state decode for tap controller
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// next state decode for tap controller
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always @(*)
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always @(*)
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case (tap_state) // synopsys parallel_case
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case (tap_state) // synopsys parallel_case
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TEST_LOGIC_RESET: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
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TEST_LOGIC_RESET: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
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RUN_TEST_IDLE: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
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RUN_TEST_IDLE: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
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SELECT_DR_SCAN: next_tap_state = tms_pad_in ? SELECT_IR_SCAN : CAPTURE_DR;
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SELECT_DR_SCAN: next_tap_state = tms_pad_in ? SELECT_IR_SCAN : CAPTURE_DR;
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CAPTURE_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR;
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CAPTURE_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR;
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SHIFT_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR;
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SHIFT_DR: next_tap_state = tms_pad_in ? EXIT1_DR : SHIFT_DR;
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EXIT1_DR: next_tap_state = tms_pad_in ? UPDATE_DR : PAUSE_DR;
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EXIT1_DR: next_tap_state = tms_pad_in ? UPDATE_DR : PAUSE_DR;
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PAUSE_DR: next_tap_state = tms_pad_in ? EXIT2_DR : PAUSE_DR;
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PAUSE_DR: next_tap_state = tms_pad_in ? EXIT2_DR : PAUSE_DR;
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EXIT2_DR: next_tap_state = tms_pad_in ? UPDATE_DR : SHIFT_DR;
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EXIT2_DR: next_tap_state = tms_pad_in ? UPDATE_DR : SHIFT_DR;
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UPDATE_DR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
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UPDATE_DR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
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SELECT_IR_SCAN: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : CAPTURE_IR;
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SELECT_IR_SCAN: next_tap_state = tms_pad_in ? TEST_LOGIC_RESET : CAPTURE_IR;
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CAPTURE_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR;
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CAPTURE_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR;
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SHIFT_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR;
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SHIFT_IR: next_tap_state = tms_pad_in ? EXIT1_IR : SHIFT_IR;
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EXIT1_IR: next_tap_state = tms_pad_in ? UPDATE_IR : PAUSE_IR;
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EXIT1_IR: next_tap_state = tms_pad_in ? UPDATE_IR : PAUSE_IR;
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PAUSE_IR: next_tap_state = tms_pad_in ? EXIT2_IR : PAUSE_IR;
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PAUSE_IR: next_tap_state = tms_pad_in ? EXIT2_IR : PAUSE_IR;
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EXIT2_IR: next_tap_state = tms_pad_in ? UPDATE_IR : SHIFT_IR;
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EXIT2_IR: next_tap_state = tms_pad_in ? UPDATE_IR : SHIFT_IR;
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UPDATE_IR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
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UPDATE_IR: next_tap_state = tms_pad_in ? SELECT_DR_SCAN : RUN_TEST_IDLE;
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endcase
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endcase
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//********************************************************************
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//********************************************************************
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//*** TAP Controller State Machine Register
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//*** TAP Controller State Machine Register
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//********************************************************************
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//********************************************************************
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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if (!trst_n_pad_in) tap_state <= TEST_LOGIC_RESET;
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if (!trst_n_pad_in) tap_state <= TEST_LOGIC_RESET;
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else tap_state <= next_tap_state;
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else tap_state <= next_tap_state;
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// Decode tap_state to get Shift, Update, and Capture signals
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// Decode tap_state to get Shift, Update, and Capture signals
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always @(*)
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always @(*)
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begin
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begin
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shift_ir = (tap_state == SHIFT_IR);
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shift_ir = (tap_state == SHIFT_IR);
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shift_dr_o = (tap_state == SHIFT_DR);
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shift_dr_o = (tap_state == SHIFT_DR);
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update_ir = (tap_state == UPDATE_IR);
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update_ir = (tap_state == UPDATE_IR);
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update_dr_o = (tap_state == UPDATE_DR);
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update_dr_o = (tap_state == UPDATE_DR);
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capture_dr_o = (tap_state == CAPTURE_DR);
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capture_dr_o = (tap_state == CAPTURE_DR);
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capture_ir = (tap_state == CAPTURE_IR);
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capture_ir = (tap_state == CAPTURE_IR);
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end
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end
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// Decode tap_state to get test_logic_reset signal
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// Decode tap_state to get test_logic_reset signal
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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if (!trst_n_pad_in) test_logic_reset_o <= 1'b1;
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if (!trst_n_pad_in) test_logic_reset_o <= 1'b1;
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else
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else
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if (next_tap_state == TEST_LOGIC_RESET) test_logic_reset_o <= 1'b1;
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if (next_tap_state == TEST_LOGIC_RESET) test_logic_reset_o <= 1'b1;
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else test_logic_reset_o <= 1'b0;
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else test_logic_reset_o <= 1'b0;
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//******************************************************
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//******************************************************
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//*** Instruction Register
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//*** Instruction Register
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//******************************************************
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//******************************************************
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reg [INST_LENGTH-1:0] instruction_buffer;
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reg [INST_LENGTH-1:0] instruction_buffer;
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reg [INST_LENGTH-1:0] instruction;
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reg [INST_LENGTH-1:0] instruction;
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// buffer the instruction register while shifting
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// buffer the instruction register while shifting
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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if (!trst_n_pad_in) instruction_buffer <= INST_RESET;
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if (!trst_n_pad_in) instruction_buffer <= INST_RESET;
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else
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else
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if (capture_ir) instruction_buffer <= INST_RETURN;
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if (capture_ir) instruction_buffer <= INST_RETURN;
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else
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else
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if (shift_ir) instruction_buffer <= {tdi_pad_in,instruction_buffer[INST_LENGTH-1:1]};
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if (shift_ir) instruction_buffer <= {tdi_pad_in,instruction_buffer[INST_LENGTH-1:1]};
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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if (!trst_n_pad_in) instruction <= INST_RESET;
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if (!trst_n_pad_in) instruction <= INST_RESET;
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else
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else
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if (tap_state == TEST_LOGIC_RESET) instruction <= INST_RESET;
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if (tap_state == TEST_LOGIC_RESET) instruction <= INST_RESET;
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else
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else
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if (update_ir) instruction <= instruction_buffer;
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if (update_ir) instruction <= instruction_buffer;
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assign tclk = tclk_pad_in;
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assign tclk = tclk_pad_in;
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assign tclk_n = !tclk_pad_in;
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assign tclk_n = !tclk_pad_in;
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assign shiftcapture_dr = shift_dr_o || capture_dr_o;
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assign shiftcapture_dr = shift_dr_o || capture_dr_o;
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assign tdi_o = tdi_pad_in;
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assign tdi_o = tdi_pad_in;
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assign trst_pad_in = !trst_n_pad_in;
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assign trst_pad_in = !trst_n_pad_in;
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// Instruction Decoder
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// Instruction Decoder
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assign extest = ( instruction == EXTEST );
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assign extest = ( instruction == EXTEST );
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assign sample = ( instruction == SAMPLE );
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assign sample = ( instruction == SAMPLE );
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assign clamp = ( instruction == CLAMP );
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assign clamp = ( instruction == CLAMP );
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assign chip_id_select = ( instruction == CHIP_ID_ACCESS );
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assign chip_id_select = ( instruction == CHIP_ID_ACCESS );
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// bypass anytime we are not doing a defined instructions, or if in clamp or bypass mode
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// bypass anytime we are not doing a defined instructions, or if in clamp or bypass mode
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assign bypass_select = ( instruction == CLAMP ) || ( instruction == BYPASS );
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assign bypass_select = ( instruction == CLAMP ) || ( instruction == BYPASS );
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assign shiftcapture_dr_clk_o = jtag_shift_clk;
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assign shiftcapture_dr_clk_o = jtag_shift_clk;
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assign select_o = ( instruction == RPC_ADD );
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assign select_o = ( instruction == RPC_ADD );
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assign aux_select_o = ( instruction == RPC_DATA );
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assign aux_select_o = ( instruction == RPC_DATA );
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assign bsr_select_o = ( instruction == EXTEST ) || ( instruction == SAMPLE ) ;
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assign bsr_select_o = ( instruction == EXTEST ) || ( instruction == SAMPLE ) ;
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//**********************************************************
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//**********************************************************
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//** Boundary scan control signals
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//** Boundary scan control signals
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//**********************************************************
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//**********************************************************
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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if (!trst_n_pad_in) bsr_output_mode <= 1'b0;
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if (!trst_n_pad_in) bsr_output_mode <= 1'b0;
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else
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else
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if (tap_state == TEST_LOGIC_RESET) bsr_output_mode <= 1'b0;
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if (tap_state == TEST_LOGIC_RESET) bsr_output_mode <= 1'b0;
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else
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else
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if (update_ir) bsr_output_mode <= (instruction_buffer == EXTEST)
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if (update_ir) bsr_output_mode <= (instruction_buffer == EXTEST)
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|| (instruction_buffer == CLAMP);
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|| (instruction_buffer == CLAMP);
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// Control chip pads when we are in highz_mode
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// Control chip pads when we are in highz_mode
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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if (!trst_n_pad_in) tap_highz_mode <= 1'b0;
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if (!trst_n_pad_in) tap_highz_mode <= 1'b0;
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else if (tap_state == TEST_LOGIC_RESET) tap_highz_mode <= 1'b0;
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else if (tap_state == TEST_LOGIC_RESET) tap_highz_mode <= 1'b0;
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else if (update_ir) tap_highz_mode <= (instruction_buffer == HIGHZ_MODE);
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else if (update_ir) tap_highz_mode <= (instruction_buffer == HIGHZ_MODE);
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//**********************************************************
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//**********************************************************
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//*** Bypass register
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//*** Bypass register
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//**********************************************************
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//**********************************************************
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|
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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always @(posedge jtag_clk or negedge trst_n_pad_in)
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if (!trst_n_pad_in) bypass_tdo <= 1'b0;
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if (!trst_n_pad_in) bypass_tdo <= 1'b0;
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else
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else
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if (capture_dr_o) bypass_tdo <= 1'b0;
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if (capture_dr_o) bypass_tdo <= 1'b0;
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else
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else
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if (shift_dr_o) bypass_tdo <= tdi_pad_in;
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if (shift_dr_o) bypass_tdo <= tdi_pad_in;
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else bypass_tdo <= bypass_tdo;
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else bypass_tdo <= bypass_tdo;
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//****************************************************************
|
//****************************************************************
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//*** Choose what goes out on the TDO pin
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//*** Choose what goes out on the TDO pin
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//****************************************************************
|
//****************************************************************
|
|
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// output the instruction register when tap_state[3] is 1, else
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// output the instruction register when tap_state[3] is 1, else
|
// put out the appropriate data register.
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// put out the appropriate data register.
|
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always@(*)
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always@(*)
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begin
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begin
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if( tap_state[3] ) next_tdo = instruction_buffer[0];
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if( tap_state[3] ) next_tdo = instruction_buffer[0];
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else
|
else
|
if(bypass_select) next_tdo = bypass_tdo;
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if(bypass_select) next_tdo = bypass_tdo;
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else
|
else
|
if(chip_id_select) next_tdo = chip_id_tdo;
|
if(chip_id_select) next_tdo = chip_id_tdo;
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else
|
else
|
if(select_o) next_tdo = tdo_i;
|
if(select_o) next_tdo = tdo_i;
|
else
|
else
|
if(aux_select_o) next_tdo = aux_tdo_i;
|
if(aux_select_o) next_tdo = aux_tdo_i;
|
else next_tdo = 1'b0;
|
else next_tdo = 1'b0;
|
end
|
end
|
|
|
|
|
reg tdo_pad_out_reg;
|
reg tdo_pad_out_reg;
|
reg tdo_pad_oe_reg;
|
reg tdo_pad_oe_reg;
|
|
|
always @(posedge tclk_n or negedge trst_n_pad_in)
|
always @(posedge tclk_n or negedge trst_n_pad_in)
|
if (!trst_n_pad_in) tdo_pad_out_reg <= 1'b0;
|
if (!trst_n_pad_in) tdo_pad_out_reg <= 1'b0;
|
else tdo_pad_out_reg <= next_tdo;
|
else tdo_pad_out_reg <= next_tdo;
|
|
|
|
|
|
|
// output enable for TDO pad
|
// output enable for TDO pad
|
|
|
always @(posedge tclk_n or negedge trst_n_pad_in)
|
always @(posedge tclk_n or negedge trst_n_pad_in)
|
if ( !trst_n_pad_in ) tdo_pad_oe_reg <= 1'b0;
|
if ( !trst_n_pad_in ) tdo_pad_oe_reg <= 1'b0;
|
else tdo_pad_oe_reg <= ( (tap_state == SHIFT_DR) || (tap_state == SHIFT_IR) );
|
else tdo_pad_oe_reg <= ( (tap_state == SHIFT_DR) || (tap_state == SHIFT_IR) );
|
|
|
|
|
|
|
assign tdo_pad_out = tdo_pad_out_reg;
|
assign tdo_pad_out = tdo_pad_out_reg;
|
assign tdo_pad_oe = tdo_pad_oe_reg;
|
assign tdo_pad_oe = tdo_pad_oe_reg;
|
|
|
`ifndef SYNTHESYS
|
`ifndef SYNTHESIS
|
|
|
reg [8*16-1:0] tap_string;
|
reg [8*16-1:0] tap_string;
|
|
|
always @(tap_state) begin
|
always @(tap_state) begin
|
case (tap_state)
|
case (tap_state)
|
TEST_LOGIC_RESET: tap_string = "TEST_LOGIC_RESET";
|
TEST_LOGIC_RESET: tap_string = "TEST_LOGIC_RESET";
|
RUN_TEST_IDLE: tap_string = "RUN_TEST_IDLE";
|
RUN_TEST_IDLE: tap_string = "RUN_TEST_IDLE";
|
SELECT_DR_SCAN: tap_string = "SELECT_DR_SCAN";
|
SELECT_DR_SCAN: tap_string = "SELECT_DR_SCAN";
|
CAPTURE_DR: tap_string = "CAPTURE_DR";
|
CAPTURE_DR: tap_string = "CAPTURE_DR";
|
SHIFT_DR: tap_string = "SHIFT_DR";
|
SHIFT_DR: tap_string = "SHIFT_DR";
|
EXIT1_DR: tap_string = "EXIT1_DR";
|
EXIT1_DR: tap_string = "EXIT1_DR";
|
PAUSE_DR: tap_string = "PAUSE_DR";
|
PAUSE_DR: tap_string = "PAUSE_DR";
|
EXIT2_DR: tap_string = "EXIT2_DR";
|
EXIT2_DR: tap_string = "EXIT2_DR";
|
UPDATE_DR: tap_string = "UPDATE_DR";
|
UPDATE_DR: tap_string = "UPDATE_DR";
|
SELECT_IR_SCAN: tap_string = "SELECT_IR_SCAN";
|
SELECT_IR_SCAN: tap_string = "SELECT_IR_SCAN";
|
CAPTURE_IR: tap_string = "CAPTURE_IR";
|
CAPTURE_IR: tap_string = "CAPTURE_IR";
|
SHIFT_IR: tap_string = "SHIFT_IR";
|
SHIFT_IR: tap_string = "SHIFT_IR";
|
EXIT1_IR: tap_string = "EXIT1_IR";
|
EXIT1_IR: tap_string = "EXIT1_IR";
|
PAUSE_IR: tap_string = "PAUSE_IR";
|
PAUSE_IR: tap_string = "PAUSE_IR";
|
EXIT2_IR: tap_string = "EXIT2_IR";
|
EXIT2_IR: tap_string = "EXIT2_IR";
|
UPDATE_IR: tap_string = "UPDATE_IR";
|
UPDATE_IR: tap_string = "UPDATE_IR";
|
default: tap_string = "-XXXXXX-";
|
default: tap_string = "-XXXXXX-";
|
endcase
|
endcase
|
|
|
$display("%t %m Tap State = %s",$realtime, tap_string);
|
$display("%t %m Tap State = %s",$realtime, tap_string);
|
end
|
end
|
|
|
|
|
|
|
|
|
reg [8*16-1:0] inst_string;
|
reg [8*16-1:0] inst_string;
|
|
|
always @(instruction) begin
|
always @(instruction) begin
|
case (instruction)
|
case (instruction)
|
EXTEST: inst_string = "EXTEST";
|
EXTEST: inst_string = "EXTEST";
|
SAMPLE: inst_string = "SAMPLE";
|
SAMPLE: inst_string = "SAMPLE";
|
HIGHZ_MODE: inst_string = "HIGHZ_MODE";
|
HIGHZ_MODE: inst_string = "HIGHZ_MODE";
|
CHIP_ID_ACCESS: inst_string = "CHIP_ID_ACCESS";
|
CHIP_ID_ACCESS: inst_string = "CHIP_ID_ACCESS";
|
CLAMP: inst_string = "CLAMP";
|
CLAMP: inst_string = "CLAMP";
|
RPC_DATA: inst_string = "RPC_DATA";
|
RPC_DATA: inst_string = "RPC_DATA";
|
RPC_ADD: inst_string = "RPC_ADD";
|
RPC_ADD: inst_string = "RPC_ADD";
|
BYPASS: inst_string = "BYPASS";
|
BYPASS: inst_string = "BYPASS";
|
default: inst_string = "-XXXXXX-";
|
default: inst_string = "-XXXXXX-";
|
endcase
|
endcase
|
|
|
$display("%t %m Instruction = %s",$realtime, inst_string);
|
$display("%t %m Instruction = %s",$realtime, inst_string);
|
end
|
end
|
|
|
`endif
|
`endif
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|