// (C) 2001-2017 Intel Corporation. All rights reserved.
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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// File name: acv_hard_memphy.v
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// File name: acv_hard_memphy.v
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// This file instantiates all the main components of the PHY.
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// This file instantiates all the main components of the PHY.
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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`timescale 1 ps / 1 ps
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`timescale 1 ps / 1 ps
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module hps_sdram_p0_acv_hard_memphy (
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module hps_sdram_p0_acv_hard_memphy (
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global_reset_n,
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global_reset_n,
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soft_reset_n,
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soft_reset_n,
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ctl_reset_n,
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ctl_reset_n,
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ctl_reset_export_n,
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ctl_reset_export_n,
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afi_reset_n,
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afi_reset_n,
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pll_locked,
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pll_locked,
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oct_ctl_rs_value,
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oct_ctl_rs_value,
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oct_ctl_rt_value,
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oct_ctl_rt_value,
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afi_addr,
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afi_addr,
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afi_ba,
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afi_ba,
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afi_cke,
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afi_cke,
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afi_cs_n,
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afi_cs_n,
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afi_ras_n,
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afi_ras_n,
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afi_we_n,
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afi_we_n,
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afi_cas_n,
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afi_cas_n,
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afi_rst_n,
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afi_rst_n,
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afi_odt,
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afi_odt,
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afi_mem_clk_disable,
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afi_mem_clk_disable,
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afi_dqs_burst,
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afi_dqs_burst,
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afi_wdata_valid,
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afi_wdata_valid,
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afi_wdata,
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afi_wdata,
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afi_dm,
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afi_dm,
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afi_rdata,
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afi_rdata,
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afi_rdata_en,
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afi_rdata_en,
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afi_rdata_en_full,
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afi_rdata_en_full,
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afi_rdata_valid,
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afi_rdata_valid,
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afi_wlat,
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afi_wlat,
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afi_rlat,
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afi_rlat,
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afi_cal_success,
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afi_cal_success,
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afi_cal_fail,
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afi_cal_fail,
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avl_read,
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avl_read,
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avl_write,
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avl_write,
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avl_address,
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avl_address,
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avl_writedata,
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avl_writedata,
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avl_waitrequest,
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avl_waitrequest,
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avl_readdata,
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avl_readdata,
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cfg_addlat,
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cfg_addlat,
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cfg_bankaddrwidth,
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cfg_bankaddrwidth,
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cfg_caswrlat,
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cfg_caswrlat,
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cfg_coladdrwidth,
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cfg_coladdrwidth,
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cfg_csaddrwidth,
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cfg_csaddrwidth,
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cfg_devicewidth,
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cfg_devicewidth,
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cfg_dramconfig,
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cfg_dramconfig,
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cfg_interfacewidth,
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cfg_interfacewidth,
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cfg_rowaddrwidth,
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cfg_rowaddrwidth,
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cfg_tcl,
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cfg_tcl,
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cfg_tmrd,
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cfg_tmrd,
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cfg_trefi,
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cfg_trefi,
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cfg_trfc,
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cfg_trfc,
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cfg_twr,
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cfg_twr,
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io_intaddrdout,
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io_intaddrdout,
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io_intbadout,
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io_intbadout,
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io_intcasndout,
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io_intcasndout,
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io_intckdout,
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io_intckdout,
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io_intckedout,
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io_intckedout,
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io_intckndout,
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io_intckndout,
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io_intcsndout,
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io_intcsndout,
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io_intdmdout,
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io_intdmdout,
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io_intdqdin,
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io_intdqdin,
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io_intdqdout,
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io_intdqdout,
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io_intdqoe,
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io_intdqoe,
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io_intdqsbdout,
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io_intdqsbdout,
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io_intdqsboe,
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io_intdqsboe,
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io_intdqsdout,
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io_intdqsdout,
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io_intdqslogicdqsena,
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io_intdqslogicdqsena,
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io_intdqslogicfiforeset,
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io_intdqslogicfiforeset,
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io_intdqslogicincrdataen,
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io_intdqslogicincrdataen,
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io_intdqslogicincwrptr,
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io_intdqslogicincwrptr,
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io_intdqslogicoct,
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io_intdqslogicoct,
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io_intdqslogicrdatavalid,
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io_intdqslogicrdatavalid,
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io_intdqslogicreadlatency,
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io_intdqslogicreadlatency,
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io_intdqsoe,
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io_intdqsoe,
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io_intodtdout,
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io_intodtdout,
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io_intrasndout,
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io_intrasndout,
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io_intresetndout,
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io_intresetndout,
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io_intwendout,
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io_intwendout,
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io_intafirlat,
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io_intafirlat,
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io_intafiwlat,
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io_intafiwlat,
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io_intaficalfail,
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io_intaficalfail,
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io_intaficalsuccess,
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io_intaficalsuccess,
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mem_a,
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mem_a,
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mem_ba,
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mem_ba,
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mem_cs_n,
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mem_cs_n,
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mem_cke,
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mem_cke,
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mem_odt,
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mem_odt,
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mem_we_n,
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mem_we_n,
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mem_ras_n,
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mem_ras_n,
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mem_cas_n,
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mem_cas_n,
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mem_reset_n,
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mem_reset_n,
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mem_dq,
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mem_dq,
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mem_dm,
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mem_dm,
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mem_ck,
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mem_ck,
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mem_ck_n,
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mem_ck_n,
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mem_dqs,
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mem_dqs,
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mem_dqs_n,
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mem_dqs_n,
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reset_n_scc_clk,
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reset_n_scc_clk,
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reset_n_avl_clk,
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reset_n_avl_clk,
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scc_data,
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scc_data,
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scc_dqs_ena,
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scc_dqs_ena,
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scc_dqs_io_ena,
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scc_dqs_io_ena,
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scc_dq_ena,
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scc_dq_ena,
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scc_dm_ena,
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scc_dm_ena,
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scc_upd,
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scc_upd,
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capture_strobe_tracking,
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capture_strobe_tracking,
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phy_clk,
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phy_clk,
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ctl_clk,
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ctl_clk,
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phy_reset_n,
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phy_reset_n,
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pll_afi_clk,
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pll_afi_clk,
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pll_afi_half_clk,
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pll_afi_half_clk,
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pll_addr_cmd_clk,
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pll_addr_cmd_clk,
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pll_mem_clk,
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pll_mem_clk,
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pll_mem_phy_clk,
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pll_mem_phy_clk,
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pll_afi_phy_clk,
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pll_afi_phy_clk,
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pll_avl_phy_clk,
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pll_avl_phy_clk,
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pll_write_clk,
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pll_write_clk,
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pll_write_clk_pre_phy_clk,
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pll_write_clk_pre_phy_clk,
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pll_dqs_ena_clk,
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pll_dqs_ena_clk,
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seq_clk,
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seq_clk,
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pll_avl_clk,
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pll_avl_clk,
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pll_config_clk,
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pll_config_clk,
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dll_clk,
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dll_clk,
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dll_pll_locked,
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dll_pll_locked,
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dll_phy_delayctrl
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dll_phy_delayctrl
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);
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);
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// BEGIN PARAMETER SECTION
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// BEGIN PARAMETER SECTION
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// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
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// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
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parameter DEVICE_FAMILY = "";
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parameter DEVICE_FAMILY = "";
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parameter IS_HHP_HPS = "false";
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parameter IS_HHP_HPS = "false";
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// On-chip termination
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// On-chip termination
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parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
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parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
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parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
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parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
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// PHY-Memory Interface
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// PHY-Memory Interface
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// Memory device specific parameters, they are set according to the memory spec
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// Memory device specific parameters, they are set according to the memory spec
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parameter MEM_ADDRESS_WIDTH = "";
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parameter MEM_ADDRESS_WIDTH = "";
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parameter MEM_BANK_WIDTH = "";
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parameter MEM_BANK_WIDTH = "";
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parameter MEM_IF_CS_WIDTH = "";
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parameter MEM_IF_CS_WIDTH = "";
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parameter MEM_CLK_EN_WIDTH = "";
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parameter MEM_CLK_EN_WIDTH = "";
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parameter MEM_CK_WIDTH = "";
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parameter MEM_CK_WIDTH = "";
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parameter MEM_ODT_WIDTH = "";
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parameter MEM_ODT_WIDTH = "";
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parameter MEM_DQS_WIDTH = "";
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parameter MEM_DQS_WIDTH = "";
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parameter MEM_DM_WIDTH = "";
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parameter MEM_DM_WIDTH = "";
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parameter MEM_CONTROL_WIDTH = "";
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parameter MEM_CONTROL_WIDTH = "";
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parameter MEM_DQ_WIDTH = "";
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parameter MEM_DQ_WIDTH = "";
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parameter MEM_READ_DQS_WIDTH = "";
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parameter MEM_READ_DQS_WIDTH = "";
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parameter MEM_WRITE_DQS_WIDTH = "";
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parameter MEM_WRITE_DQS_WIDTH = "";
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// PHY-Controller (AFI) Interface
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// PHY-Controller (AFI) Interface
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// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
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// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
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// The calculations are done on higher level wrapper
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// The calculations are done on higher level wrapper
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// DLL Interface
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// DLL Interface
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// The DLL delay output control is always 6 bits for current existing devices
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// The DLL delay output control is always 6 bits for current existing devices
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parameter DLL_DELAY_CTRL_WIDTH = "";
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parameter DLL_DELAY_CTRL_WIDTH = "";
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parameter MR1_ODS = "";
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parameter MR1_ODS = "";
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parameter MR1_RTT = "";
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parameter MR1_RTT = "";
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parameter MR2_RTT_WR = "";
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parameter MR2_RTT_WR = "";
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parameter TB_PROTOCOL = "";
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parameter TB_PROTOCOL = "";
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parameter TB_MEM_CLK_FREQ = "";
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parameter TB_MEM_CLK_FREQ = "";
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parameter TB_RATE = "";
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parameter TB_RATE = "";
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parameter TB_MEM_DQ_WIDTH = "";
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parameter TB_MEM_DQ_WIDTH = "";
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parameter TB_MEM_DQS_WIDTH = "";
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parameter TB_MEM_DQS_WIDTH = "";
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parameter TB_PLL_DLL_MASTER = "";
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parameter TB_PLL_DLL_MASTER = "";
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parameter FAST_SIM_MODEL = "";
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parameter FAST_SIM_MODEL = "";
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parameter FAST_SIM_CALIBRATION = "";
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parameter FAST_SIM_CALIBRATION = "";
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// Width of the calibration status register used to control calibration skipping.
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// Width of the calibration status register used to control calibration skipping.
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parameter CALIB_REG_WIDTH = "";
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parameter CALIB_REG_WIDTH = "";
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parameter AC_ROM_INIT_FILE_NAME = "";
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parameter AC_ROM_INIT_FILE_NAME = "";
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parameter INST_ROM_INIT_FILE_NAME = "";
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parameter INST_ROM_INIT_FILE_NAME = "";
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// The number of AFI Resets to generate
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// The number of AFI Resets to generate
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localparam NUM_AFI_RESET = 4;
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localparam NUM_AFI_RESET = 4;
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// Addr/cmd clock phase
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// Addr/cmd clock phase
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localparam ADC_PHASE_SETTING = 0;
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localparam ADC_PHASE_SETTING = 0;
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localparam ADC_INVERT_PHASE = "true";
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localparam ADC_INVERT_PHASE = "true";
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// END PARAMETER SECTION
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// END PARAMETER SECTION
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// BEGIN PORT SECTION
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// BEGIN PORT SECTION
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// Reset Interface
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// Reset Interface
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input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
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input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
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input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
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input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
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input pll_locked; // Indicates that PLL is locked
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input pll_locked; // Indicates that PLL is locked
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output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
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output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
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output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
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output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
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output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
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output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
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input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
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input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
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input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
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input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
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// PHY-Controller Interface, AFI 2.0
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// PHY-Controller Interface, AFI 2.0
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// Control Interface
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// Control Interface
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input [19:0] afi_addr;
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input [19:0] afi_addr;
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input [2:0] afi_ba;
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input [2:0] afi_ba;
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input [1:0] afi_cke;
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input [1:0] afi_cke;
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input [1:0] afi_cs_n;
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input [1:0] afi_cs_n;
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input [0:0] afi_cas_n;
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input [0:0] afi_cas_n;
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input [1:0] afi_odt;
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input [1:0] afi_odt;
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input [0:0] afi_ras_n;
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input [0:0] afi_ras_n;
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input [0:0] afi_we_n;
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input [0:0] afi_we_n;
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input [0:0] afi_rst_n;
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input [0:0] afi_rst_n;
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input [0:0] afi_mem_clk_disable;
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input [0:0] afi_mem_clk_disable;
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input [4:0] afi_dqs_burst;
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input [4:0] afi_dqs_burst;
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output [3:0] afi_wlat;
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output [3:0] afi_wlat;
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output [4:0] afi_rlat;
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output [4:0] afi_rlat;
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// Write data interface
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// Write data interface
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input [79:0] afi_wdata; // write data
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input [79:0] afi_wdata; // write data
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input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
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input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
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input [9:0] afi_dm; // write data mask
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input [9:0] afi_dm; // write data mask
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// Read data interface
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// Read data interface
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output [79:0] afi_rdata; // read data
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output [79:0] afi_rdata; // read data
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input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
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input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
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input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
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input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
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output [0:0] afi_rdata_valid; // read data valid
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output [0:0] afi_rdata_valid; // read data valid
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// Status interface
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// Status interface
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output afi_cal_success; // calibration success
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output afi_cal_success; // calibration success
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output afi_cal_fail; // calibration failure
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output afi_cal_fail; // calibration failure
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// Avalon interface to the sequencer
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// Avalon interface to the sequencer
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input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
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input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
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input avl_read;
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input avl_read;
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output [31:0] avl_readdata;
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output [31:0] avl_readdata;
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output avl_waitrequest;
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output avl_waitrequest;
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input avl_write;
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input avl_write;
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input [31:0] avl_writedata;
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input [31:0] avl_writedata;
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// Configuration interface to the memory controller
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// Configuration interface to the memory controller
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input [7:0] cfg_addlat;
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input [7:0] cfg_addlat;
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input [7:0] cfg_bankaddrwidth;
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input [7:0] cfg_bankaddrwidth;
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input [7:0] cfg_caswrlat;
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input [7:0] cfg_caswrlat;
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input [7:0] cfg_coladdrwidth;
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input [7:0] cfg_coladdrwidth;
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input [7:0] cfg_csaddrwidth;
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input [7:0] cfg_csaddrwidth;
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input [7:0] cfg_devicewidth;
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input [7:0] cfg_devicewidth;
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input [23:0] cfg_dramconfig;
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input [23:0] cfg_dramconfig;
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input [7:0] cfg_interfacewidth;
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input [7:0] cfg_interfacewidth;
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input [7:0] cfg_rowaddrwidth;
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input [7:0] cfg_rowaddrwidth;
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input [7:0] cfg_tcl;
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input [7:0] cfg_tcl;
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input [7:0] cfg_tmrd;
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input [7:0] cfg_tmrd;
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input [15:0] cfg_trefi;
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input [15:0] cfg_trefi;
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input [7:0] cfg_trfc;
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input [7:0] cfg_trfc;
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input [7:0] cfg_twr;
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input [7:0] cfg_twr;
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// IO/bypass interface to the core (or soft controller)
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// IO/bypass interface to the core (or soft controller)
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input [63:0] io_intaddrdout;
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input [63:0] io_intaddrdout;
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input [11:0] io_intbadout;
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input [11:0] io_intbadout;
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input [3:0] io_intcasndout;
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input [3:0] io_intcasndout;
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input [3:0] io_intckdout;
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input [3:0] io_intckdout;
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input [7:0] io_intckedout;
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input [7:0] io_intckedout;
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input [3:0] io_intckndout;
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input [3:0] io_intckndout;
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input [7:0] io_intcsndout;
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input [7:0] io_intcsndout;
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input [19:0] io_intdmdout;
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input [19:0] io_intdmdout;
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output [179:0] io_intdqdin;
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output [179:0] io_intdqdin;
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input [179:0] io_intdqdout;
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input [179:0] io_intdqdout;
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input [89:0] io_intdqoe;
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input [89:0] io_intdqoe;
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input [19:0] io_intdqsbdout;
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input [19:0] io_intdqsbdout;
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input [9:0] io_intdqsboe;
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input [9:0] io_intdqsboe;
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input [19:0] io_intdqsdout;
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input [19:0] io_intdqsdout;
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input [9:0] io_intdqslogicdqsena;
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input [9:0] io_intdqslogicdqsena;
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input [4:0] io_intdqslogicfiforeset;
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input [4:0] io_intdqslogicfiforeset;
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input [9:0] io_intdqslogicincrdataen;
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input [9:0] io_intdqslogicincrdataen;
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input [9:0] io_intdqslogicincwrptr;
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input [9:0] io_intdqslogicincwrptr;
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input [9:0] io_intdqslogicoct;
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input [9:0] io_intdqslogicoct;
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output [4:0] io_intdqslogicrdatavalid;
|
output [4:0] io_intdqslogicrdatavalid;
|
input [24:0] io_intdqslogicreadlatency;
|
input [24:0] io_intdqslogicreadlatency;
|
input [9:0] io_intdqsoe;
|
input [9:0] io_intdqsoe;
|
input [7:0] io_intodtdout;
|
input [7:0] io_intodtdout;
|
input [3:0] io_intrasndout;
|
input [3:0] io_intrasndout;
|
input [3:0] io_intresetndout;
|
input [3:0] io_intresetndout;
|
input [3:0] io_intwendout;
|
input [3:0] io_intwendout;
|
output [4:0] io_intafirlat;
|
output [4:0] io_intafirlat;
|
output [3:0] io_intafiwlat;
|
output [3:0] io_intafiwlat;
|
output io_intaficalfail;
|
output io_intaficalfail;
|
output io_intaficalsuccess;
|
output io_intaficalsuccess;
|
|
|
|
|
// PHY-Memory Interface
|
// PHY-Memory Interface
|
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
|
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
|
output [MEM_BANK_WIDTH-1:0] mem_ba;
|
output [MEM_BANK_WIDTH-1:0] mem_ba;
|
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
|
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
|
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
|
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
|
output [MEM_ODT_WIDTH-1:0] mem_odt;
|
output [MEM_ODT_WIDTH-1:0] mem_odt;
|
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
|
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
|
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
|
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
|
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
|
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
|
output mem_reset_n;
|
output mem_reset_n;
|
inout [MEM_DQ_WIDTH-1:0] mem_dq;
|
inout [MEM_DQ_WIDTH-1:0] mem_dq;
|
output [MEM_DM_WIDTH-1:0] mem_dm;
|
output [MEM_DM_WIDTH-1:0] mem_dm;
|
output [MEM_CK_WIDTH-1:0] mem_ck;
|
output [MEM_CK_WIDTH-1:0] mem_ck;
|
output [MEM_CK_WIDTH-1:0] mem_ck_n;
|
output [MEM_CK_WIDTH-1:0] mem_ck_n;
|
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
|
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
|
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
|
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
|
|
|
|
|
|
|
output reset_n_scc_clk;
|
output reset_n_scc_clk;
|
output reset_n_avl_clk;
|
output reset_n_avl_clk;
|
|
|
|
|
// Scan chain configuration manager interface
|
// Scan chain configuration manager interface
|
input scc_data;
|
input scc_data;
|
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
|
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
|
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
|
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
|
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
|
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
|
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
|
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
|
input [0:0] scc_upd;
|
input [0:0] scc_upd;
|
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
|
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
|
|
|
|
|
output phy_clk;
|
output phy_clk;
|
output ctl_clk;
|
output ctl_clk;
|
output phy_reset_n;
|
output phy_reset_n;
|
|
|
|
|
// PLL Interface
|
// PLL Interface
|
input pll_afi_clk; // clocks AFI interface logic
|
input pll_afi_clk; // clocks AFI interface logic
|
input pll_afi_half_clk; //
|
input pll_afi_half_clk; //
|
input pll_addr_cmd_clk; // clocks address/command DDIO
|
input pll_addr_cmd_clk; // clocks address/command DDIO
|
input pll_mem_clk; // output clock to memory
|
input pll_mem_clk; // output clock to memory
|
input pll_write_clk; // clocks write data DDIO
|
input pll_write_clk; // clocks write data DDIO
|
input pll_write_clk_pre_phy_clk;
|
input pll_write_clk_pre_phy_clk;
|
input pll_dqs_ena_clk;
|
input pll_dqs_ena_clk;
|
input seq_clk;
|
input seq_clk;
|
input pll_avl_clk;
|
input pll_avl_clk;
|
input pll_config_clk;
|
input pll_config_clk;
|
input pll_mem_phy_clk;
|
input pll_mem_phy_clk;
|
input pll_afi_phy_clk;
|
input pll_afi_phy_clk;
|
input pll_avl_phy_clk;
|
input pll_avl_phy_clk;
|
|
|
|
|
// DLL Interface
|
// DLL Interface
|
output dll_clk;
|
output dll_clk;
|
output dll_pll_locked;
|
output dll_pll_locked;
|
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
|
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
|
|
|
|
|
|
|
// END PARAMETER SECTION
|
// END PARAMETER SECTION
|
// ********************************************************************************************************************************
|
// ********************************************************************************************************************************
|
|
|
|
|
wire [179:0] ddio_phy_dqdin;
|
wire [179:0] ddio_phy_dqdin;
|
wire [4:0] ddio_phy_dqslogic_rdatavalid;
|
wire [4:0] ddio_phy_dqslogic_rdatavalid;
|
|
|
wire [63:0] phy_ddio_address;
|
wire [63:0] phy_ddio_address;
|
wire [11:0] phy_ddio_bank;
|
wire [11:0] phy_ddio_bank;
|
wire [3:0] phy_ddio_cas_n;
|
wire [3:0] phy_ddio_cas_n;
|
wire [3:0] phy_ddio_ck;
|
wire [3:0] phy_ddio_ck;
|
wire [7:0] phy_ddio_cke;
|
wire [7:0] phy_ddio_cke;
|
wire [3:0] phy_ddio_ck_n;
|
wire [3:0] phy_ddio_ck_n;
|
wire [7:0] phy_ddio_cs_n;
|
wire [7:0] phy_ddio_cs_n;
|
wire [19:0] phy_ddio_dmdout;
|
wire [19:0] phy_ddio_dmdout;
|
wire [179:0] phy_ddio_dqdout;
|
wire [179:0] phy_ddio_dqdout;
|
wire [89:0] phy_ddio_dqoe;
|
wire [89:0] phy_ddio_dqoe;
|
wire [9:0] phy_ddio_dqsb_oe;
|
wire [9:0] phy_ddio_dqsb_oe;
|
wire [9:0] phy_ddio_dqslogic_dqsena;
|
wire [9:0] phy_ddio_dqslogic_dqsena;
|
wire [4:0] phy_ddio_dqslogic_fiforeset;
|
wire [4:0] phy_ddio_dqslogic_fiforeset;
|
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
|
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
|
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
|
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
|
wire [9:0] phy_ddio_dqslogic_incrdataen;
|
wire [9:0] phy_ddio_dqslogic_incrdataen;
|
wire [9:0] phy_ddio_dqslogic_incwrptr;
|
wire [9:0] phy_ddio_dqslogic_incwrptr;
|
wire [9:0] phy_ddio_dqslogic_oct;
|
wire [9:0] phy_ddio_dqslogic_oct;
|
wire [24:0] phy_ddio_dqslogic_readlatency;
|
wire [24:0] phy_ddio_dqslogic_readlatency;
|
wire [9:0] phy_ddio_dqs_oe;
|
wire [9:0] phy_ddio_dqs_oe;
|
wire [19:0] phy_ddio_dqs_dout;
|
wire [19:0] phy_ddio_dqs_dout;
|
wire [7:0] phy_ddio_odt;
|
wire [7:0] phy_ddio_odt;
|
wire [3:0] phy_ddio_ras_n;
|
wire [3:0] phy_ddio_ras_n;
|
wire [3:0] phy_ddio_reset_n;
|
wire [3:0] phy_ddio_reset_n;
|
wire [3:0] phy_ddio_we_n;
|
wire [3:0] phy_ddio_we_n;
|
|
|
wire read_capture_clk;
|
wire read_capture_clk;
|
|
|
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
|
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
|
wire reset_n_addr_cmd_clk;
|
wire reset_n_addr_cmd_clk;
|
wire reset_n_seq_clk;
|
wire reset_n_seq_clk;
|
|
|
wire reset_n_scc_clk;
|
wire reset_n_scc_clk;
|
wire reset_n_avl_clk;
|
wire reset_n_avl_clk;
|
wire reset_n_resync_clk;
|
wire reset_n_resync_clk;
|
|
|
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
|
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
|
|
|
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
|
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
|
|
|
localparam SKIP_MEM_INIT = 1'b1;
|
localparam SKIP_MEM_INIT = 1'b1;
|
|
|
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
|
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
|
|
|
generate
|
generate
|
if (IS_HHP_HPS != "true") begin
|
if (IS_HHP_HPS != "true") begin
|
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
|
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
|
|
|
// Initialization of the sequencer status register. This register
|
// Initialization of the sequencer status register. This register
|
// is preserved in the netlist so that it can be forced during simulation
|
// is preserved in the netlist so that it can be forced during simulation
|
always @(posedge pll_afi_clk)
|
always @(posedge pll_afi_clk)
|
`ifdef SYNTH_FOR_SIM
|
`ifdef SYNTH_FOR_SIM
|
`else
|
`else
|
//synthesis translate_off
|
//synthesis translate_off
|
`endif
|
`endif
|
seq_calib_init_reg <= SEQ_CALIB_INIT;
|
seq_calib_init_reg <= SEQ_CALIB_INIT;
|
`ifdef SYNTH_FOR_SIM
|
`ifdef SYNTH_FOR_SIM
|
`else
|
`else
|
//synthesis translate_on
|
//synthesis translate_on
|
//synthesis read_comments_as_HDL on
|
//synthesis read_comments_as_HDL on
|
`endif
|
`endif
|
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
|
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
|
`ifdef SYNTH_FOR_SIM
|
`ifdef SYNTH_FOR_SIM
|
`else
|
`else
|
// synthesis read_comments_as_HDL off
|
// synthesis read_comments_as_HDL off
|
`endif
|
`endif
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
// ********************************************************************************************************************************
|
// ********************************************************************************************************************************
|
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
|
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
|
// The reset block has 2 main functionalities:
|
// The reset block has 2 main functionalities:
|
// 1. Keep all the PHY logic in reset state until after the PLL is locked
|
// 1. Keep all the PHY logic in reset state until after the PLL is locked
|
// 2. Synchronize the reset to each clock domain
|
// 2. Synchronize the reset to each clock domain
|
// ********************************************************************************************************************************
|
// ********************************************************************************************************************************
|
|
|
|
|
generate
|
generate
|
if (IS_HHP_HPS != "true") begin
|
if (IS_HHP_HPS != "true") begin
|
hps_sdram_p0_reset ureset(
|
hps_sdram_p0_reset ureset(
|
.pll_afi_clk (pll_afi_clk),
|
.pll_afi_clk (pll_afi_clk),
|
.pll_addr_cmd_clk (pll_addr_cmd_clk),
|
.pll_addr_cmd_clk (pll_addr_cmd_clk),
|
.pll_dqs_ena_clk (pll_dqs_ena_clk),
|
.pll_dqs_ena_clk (pll_dqs_ena_clk),
|
.seq_clk (seq_clk),
|
.seq_clk (seq_clk),
|
.pll_avl_clk (pll_avl_clk),
|
.pll_avl_clk (pll_avl_clk),
|
.scc_clk (pll_config_clk),
|
.scc_clk (pll_config_clk),
|
.reset_n_scc_clk (reset_n_scc_clk),
|
.reset_n_scc_clk (reset_n_scc_clk),
|
.reset_n_avl_clk (reset_n_avl_clk),
|
.reset_n_avl_clk (reset_n_avl_clk),
|
.read_capture_clk (read_capture_clk),
|
.read_capture_clk (read_capture_clk),
|
.pll_locked (pll_locked),
|
.pll_locked (pll_locked),
|
.global_reset_n (global_reset_n),
|
.global_reset_n (global_reset_n),
|
.soft_reset_n (soft_reset_n),
|
.soft_reset_n (soft_reset_n),
|
.ctl_reset_export_n (ctl_reset_export_n),
|
.ctl_reset_export_n (ctl_reset_export_n),
|
.reset_n_afi_clk (reset_n_afi_clk),
|
.reset_n_afi_clk (reset_n_afi_clk),
|
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
|
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
|
.reset_n_seq_clk (reset_n_seq_clk),
|
.reset_n_seq_clk (reset_n_seq_clk),
|
.reset_n_resync_clk (reset_n_resync_clk)
|
.reset_n_resync_clk (reset_n_resync_clk)
|
);
|
);
|
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
|
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
|
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
|
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
|
end else begin
|
end else begin
|
// synthesis translate_off
|
// synthesis translate_off
|
hps_sdram_p0_reset ureset(
|
hps_sdram_p0_reset ureset(
|
.pll_afi_clk (pll_afi_clk),
|
.pll_afi_clk (pll_afi_clk),
|
.pll_addr_cmd_clk (pll_addr_cmd_clk),
|
.pll_addr_cmd_clk (pll_addr_cmd_clk),
|
.pll_dqs_ena_clk (pll_dqs_ena_clk),
|
.pll_dqs_ena_clk (pll_dqs_ena_clk),
|
.seq_clk (seq_clk),
|
.seq_clk (seq_clk),
|
.pll_avl_clk (pll_avl_clk),
|
.pll_avl_clk (pll_avl_clk),
|
.scc_clk (pll_config_clk),
|
.scc_clk (pll_config_clk),
|
.reset_n_scc_clk (reset_n_scc_clk),
|
.reset_n_scc_clk (reset_n_scc_clk),
|
.reset_n_avl_clk (reset_n_avl_clk),
|
.reset_n_avl_clk (reset_n_avl_clk),
|
.read_capture_clk (read_capture_clk),
|
.read_capture_clk (read_capture_clk),
|
.pll_locked (pll_locked),
|
.pll_locked (pll_locked),
|
.global_reset_n (global_reset_n),
|
.global_reset_n (global_reset_n),
|
.soft_reset_n (soft_reset_n),
|
.soft_reset_n (soft_reset_n),
|
.ctl_reset_export_n (ctl_reset_export_n),
|
.ctl_reset_export_n (ctl_reset_export_n),
|
.reset_n_afi_clk (reset_n_afi_clk),
|
.reset_n_afi_clk (reset_n_afi_clk),
|
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
|
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
|
.reset_n_seq_clk (reset_n_seq_clk),
|
.reset_n_seq_clk (reset_n_seq_clk),
|
.reset_n_resync_clk (reset_n_resync_clk)
|
.reset_n_resync_clk (reset_n_resync_clk)
|
);
|
);
|
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
|
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
|
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
|
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
|
// synthesis translate_on
|
// synthesis translate_on
|
// synthesis read_comments_as_HDL on
|
// synthesis read_comments_as_HDL on
|
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
|
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
|
// assign reset_n_addr_cmd_clk = global_reset_n;
|
// assign reset_n_addr_cmd_clk = global_reset_n;
|
// assign reset_n_avl_clk = global_reset_n;
|
// assign reset_n_avl_clk = global_reset_n;
|
// assign reset_n_scc_clk = global_reset_n;
|
// assign reset_n_scc_clk = global_reset_n;
|
// synthesis read_comments_as_HDL off
|
// synthesis read_comments_as_HDL off
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
|
|
|
|
assign phy_clk = seq_clk;
|
assign phy_clk = seq_clk;
|
assign phy_reset_n = reset_n_seq_clk;
|
assign phy_reset_n = reset_n_seq_clk;
|
|
|
assign dll_clk = pll_write_clk_pre_phy_clk;
|
assign dll_clk = pll_write_clk_pre_phy_clk;
|
|
|
assign dll_pll_locked = pll_locked;
|
assign dll_pll_locked = pll_locked;
|
|
|
// PHY clock and LDC
|
// PHY clock and LDC
|
wire afi_clk;
|
wire afi_clk;
|
wire avl_clk;
|
wire avl_clk;
|
wire adc_clk;
|
wire adc_clk;
|
wire adc_clk_cps;
|
wire adc_clk_cps;
|
|
|
hps_sdram_p0_acv_ldc # (
|
hps_sdram_p0_acv_ldc # (
|
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
|
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
|
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
|
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
|
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
|
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
|
.IS_HHP_HPS (IS_HHP_HPS)
|
.IS_HHP_HPS (IS_HHP_HPS)
|
) memphy_ldc (
|
) memphy_ldc (
|
.pll_hr_clk (pll_avl_phy_clk),
|
.pll_hr_clk (pll_avl_phy_clk),
|
.pll_dq_clk (pll_write_clk),
|
.pll_dq_clk (pll_write_clk),
|
.pll_dqs_clk (pll_mem_phy_clk),
|
.pll_dqs_clk (pll_mem_phy_clk),
|
.dll_phy_delayctrl (dll_phy_delayctrl),
|
.dll_phy_delayctrl (dll_phy_delayctrl),
|
.afi_clk (afi_clk),
|
.afi_clk (afi_clk),
|
.avl_clk (avl_clk),
|
.avl_clk (avl_clk),
|
.adc_clk (adc_clk),
|
.adc_clk (adc_clk),
|
.adc_clk_cps (adc_clk_cps)
|
.adc_clk_cps (adc_clk_cps)
|
);
|
);
|
|
|
assign ctl_clk = afi_clk;
|
assign ctl_clk = afi_clk;
|
assign afi_reset_n = reset_n_afi_clk;
|
assign afi_reset_n = reset_n_afi_clk;
|
|
|
// ********************************************************************************************************************************
|
// ********************************************************************************************************************************
|
// This is the hard PHY instance
|
// This is the hard PHY instance
|
// ********************************************************************************************************************************
|
// ********************************************************************************************************************************
|
|
|
|
|
cyclonev_mem_phy hphy_inst (
|
cyclonev_mem_phy hphy_inst (
|
.pllaficlk (afi_clk),
|
.pllaficlk (afi_clk),
|
.pllavlclk (avl_clk),
|
.pllavlclk (avl_clk),
|
.plllocked (pll_locked),
|
.plllocked (pll_locked),
|
.plladdrcmdclk (adc_clk),
|
.plladdrcmdclk (adc_clk),
|
.globalresetn (global_reset_n),
|
.globalresetn (global_reset_n),
|
.softresetn (soft_reset_n),
|
.softresetn (soft_reset_n),
|
.phyresetn (phy_reset_n),
|
.phyresetn (phy_reset_n),
|
.ctlresetn (ctl_reset_n),
|
.ctlresetn (ctl_reset_n),
|
.iointaddrdout (io_intaddrdout),
|
.iointaddrdout (io_intaddrdout),
|
.iointbadout (io_intbadout),
|
.iointbadout (io_intbadout),
|
.iointcasndout (io_intcasndout),
|
.iointcasndout (io_intcasndout),
|
.iointckdout (io_intckdout),
|
.iointckdout (io_intckdout),
|
.iointckedout (io_intckedout),
|
.iointckedout (io_intckedout),
|
.iointckndout (io_intckndout),
|
.iointckndout (io_intckndout),
|
.iointcsndout (io_intcsndout),
|
.iointcsndout (io_intcsndout),
|
.iointdmdout (io_intdmdout),
|
.iointdmdout (io_intdmdout),
|
.iointdqdin (io_intdqdin),
|
.iointdqdin (io_intdqdin),
|
.iointdqdout (io_intdqdout),
|
.iointdqdout (io_intdqdout),
|
.iointdqoe (io_intdqoe),
|
.iointdqoe (io_intdqoe),
|
.iointdqsbdout (io_intdqsbdout),
|
.iointdqsbdout (io_intdqsbdout),
|
.iointdqsboe (io_intdqsboe),
|
.iointdqsboe (io_intdqsboe),
|
.iointdqsdout (io_intdqsdout),
|
.iointdqsdout (io_intdqsdout),
|
.iointdqslogicdqsena (io_intdqslogicdqsena),
|
.iointdqslogicdqsena (io_intdqslogicdqsena),
|
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
|
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
|
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
|
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
|
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
|
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
|
.iointdqslogicoct (io_intdqslogicoct),
|
.iointdqslogicoct (io_intdqslogicoct),
|
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
|
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
|
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
|
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
|
.iointdqsoe (io_intdqsoe),
|
.iointdqsoe (io_intdqsoe),
|
.iointodtdout (io_intodtdout),
|
.iointodtdout (io_intodtdout),
|
.iointrasndout (io_intrasndout),
|
.iointrasndout (io_intrasndout),
|
.iointresetndout (io_intresetndout),
|
.iointresetndout (io_intresetndout),
|
.iointwendout (io_intwendout),
|
.iointwendout (io_intwendout),
|
.iointafirlat (io_intafirlat),
|
.iointafirlat (io_intafirlat),
|
.iointafiwlat (io_intafiwlat),
|
.iointafiwlat (io_intafiwlat),
|
.iointaficalfail (io_intaficalfail),
|
.iointaficalfail (io_intaficalfail),
|
.iointaficalsuccess (io_intaficalsuccess),
|
.iointaficalsuccess (io_intaficalsuccess),
|
.ddiophydqdin (ddio_phy_dqdin),
|
.ddiophydqdin (ddio_phy_dqdin),
|
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
|
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
|
.phyddioaddrdout (phy_ddio_address),
|
.phyddioaddrdout (phy_ddio_address),
|
.phyddiobadout (phy_ddio_bank),
|
.phyddiobadout (phy_ddio_bank),
|
.phyddiocasndout (phy_ddio_cas_n),
|
.phyddiocasndout (phy_ddio_cas_n),
|
.phyddiockdout (phy_ddio_ck),
|
.phyddiockdout (phy_ddio_ck),
|
.phyddiockedout (phy_ddio_cke),
|
.phyddiockedout (phy_ddio_cke),
|
.phyddiockndout (),
|
.phyddiockndout (),
|
.phyddiocsndout (phy_ddio_cs_n),
|
.phyddiocsndout (phy_ddio_cs_n),
|
.phyddiodmdout (phy_ddio_dmdout),
|
.phyddiodmdout (phy_ddio_dmdout),
|
.phyddiodqdout (phy_ddio_dqdout),
|
.phyddiodqdout (phy_ddio_dqdout),
|
.phyddiodqoe (phy_ddio_dqoe),
|
.phyddiodqoe (phy_ddio_dqoe),
|
.phyddiodqsbdout (),
|
.phyddiodqsbdout (),
|
.phyddiodqsboe (phy_ddio_dqsb_oe),
|
.phyddiodqsboe (phy_ddio_dqsb_oe),
|
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
|
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
|
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
|
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
|
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
|
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
|
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
|
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
|
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
|
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
|
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
|
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
|
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
|
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
|
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
|
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
|
.phyddiodqsoe (phy_ddio_dqs_oe),
|
.phyddiodqsoe (phy_ddio_dqs_oe),
|
.phyddiodqsdout (phy_ddio_dqs_dout),
|
.phyddiodqsdout (phy_ddio_dqs_dout),
|
.phyddioodtdout (phy_ddio_odt),
|
.phyddioodtdout (phy_ddio_odt),
|
.phyddiorasndout (phy_ddio_ras_n),
|
.phyddiorasndout (phy_ddio_ras_n),
|
.phyddioresetndout (phy_ddio_reset_n),
|
.phyddioresetndout (phy_ddio_reset_n),
|
.phyddiowendout (phy_ddio_we_n),
|
.phyddiowendout (phy_ddio_we_n),
|
.afiaddr (afi_addr),
|
.afiaddr (afi_addr),
|
.afiba (afi_ba),
|
.afiba (afi_ba),
|
.aficalfail (afi_cal_fail),
|
.aficalfail (afi_cal_fail),
|
.aficalsuccess (afi_cal_success),
|
.aficalsuccess (afi_cal_success),
|
.aficasn (afi_cas_n),
|
.aficasn (afi_cas_n),
|
.aficke (afi_cke),
|
.aficke (afi_cke),
|
.aficsn (afi_cs_n),
|
.aficsn (afi_cs_n),
|
.afidm (afi_dm),
|
.afidm (afi_dm),
|
.afidqsburst (afi_dqs_burst),
|
.afidqsburst (afi_dqs_burst),
|
.afimemclkdisable (afi_mem_clk_disable),
|
.afimemclkdisable (afi_mem_clk_disable),
|
.afiodt (afi_odt),
|
.afiodt (afi_odt),
|
.afirasn (afi_ras_n),
|
.afirasn (afi_ras_n),
|
.afirdata (afi_rdata),
|
.afirdata (afi_rdata),
|
.afirdataen (afi_rdata_en),
|
.afirdataen (afi_rdata_en),
|
.afirdataenfull (afi_rdata_en_full),
|
.afirdataenfull (afi_rdata_en_full),
|
.afirdatavalid (afi_rdata_valid),
|
.afirdatavalid (afi_rdata_valid),
|
.afirlat (afi_rlat),
|
.afirlat (afi_rlat),
|
.afirstn (afi_rst_n),
|
.afirstn (afi_rst_n),
|
.afiwdata (afi_wdata),
|
.afiwdata (afi_wdata),
|
.afiwdatavalid (afi_wdata_valid),
|
.afiwdatavalid (afi_wdata_valid),
|
.afiwen (afi_we_n),
|
.afiwen (afi_we_n),
|
.afiwlat (afi_wlat),
|
.afiwlat (afi_wlat),
|
.avladdress (avl_address),
|
.avladdress (avl_address),
|
.avlread (avl_read),
|
.avlread (avl_read),
|
.avlreaddata (avl_readdata),
|
.avlreaddata (avl_readdata),
|
.avlresetn (reset_n_avl_clk),
|
.avlresetn (reset_n_avl_clk),
|
.avlwaitrequest (avl_waitrequest),
|
.avlwaitrequest (avl_waitrequest),
|
.avlwrite (avl_write),
|
.avlwrite (avl_write),
|
.avlwritedata (avl_writedata),
|
.avlwritedata (avl_writedata),
|
.cfgaddlat (cfg_addlat),
|
.cfgaddlat (cfg_addlat),
|
.cfgbankaddrwidth (cfg_bankaddrwidth),
|
.cfgbankaddrwidth (cfg_bankaddrwidth),
|
.cfgcaswrlat (cfg_caswrlat),
|
.cfgcaswrlat (cfg_caswrlat),
|
.cfgcoladdrwidth (cfg_coladdrwidth),
|
.cfgcoladdrwidth (cfg_coladdrwidth),
|
.cfgcsaddrwidth (cfg_csaddrwidth),
|
.cfgcsaddrwidth (cfg_csaddrwidth),
|
.cfgdevicewidth (cfg_devicewidth),
|
.cfgdevicewidth (cfg_devicewidth),
|
.cfgdramconfig (cfg_dramconfig),
|
.cfgdramconfig (cfg_dramconfig),
|
.cfginterfacewidth (cfg_interfacewidth),
|
.cfginterfacewidth (cfg_interfacewidth),
|
.cfgrowaddrwidth (cfg_rowaddrwidth),
|
.cfgrowaddrwidth (cfg_rowaddrwidth),
|
.cfgtcl (cfg_tcl),
|
.cfgtcl (cfg_tcl),
|
.cfgtmrd (cfg_tmrd),
|
.cfgtmrd (cfg_tmrd),
|
.cfgtrefi (cfg_trefi),
|
.cfgtrefi (cfg_trefi),
|
.cfgtrfc (cfg_trfc),
|
.cfgtrfc (cfg_trfc),
|
.cfgtwr (cfg_twr),
|
.cfgtwr (cfg_twr),
|
.scanen ()
|
.scanen ()
|
);
|
);
|
defparam hphy_inst.hphy_ac_ddr_disable = "true";
|
defparam hphy_inst.hphy_ac_ddr_disable = "true";
|
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
|
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
|
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
|
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
|
defparam hphy_inst.hphy_reset_delay_en = "false";
|
defparam hphy_inst.hphy_reset_delay_en = "false";
|
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
|
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
|
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
|
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
|
defparam hphy_inst.hphy_wrap_back_en = "false";
|
defparam hphy_inst.hphy_wrap_back_en = "false";
|
defparam hphy_inst.hphy_atpg_en = "false";
|
defparam hphy_inst.hphy_atpg_en = "false";
|
defparam hphy_inst.hphy_use_hphy = "true";
|
defparam hphy_inst.hphy_use_hphy = "true";
|
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
|
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
|
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
|
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
|
|
|
|
|
// ********************************************************************************************************************************
|
// ********************************************************************************************************************************
|
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
|
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
|
// ********************************************************************************************************************************
|
// ********************************************************************************************************************************
|
|
|
|
|
hps_sdram_p0_acv_hard_io_pads #(
|
hps_sdram_p0_acv_hard_io_pads #(
|
.DEVICE_FAMILY(DEVICE_FAMILY),
|
.DEVICE_FAMILY(DEVICE_FAMILY),
|
.FAST_SIM_MODEL(FAST_SIM_MODEL),
|
.FAST_SIM_MODEL(FAST_SIM_MODEL),
|
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
|
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
|
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
|
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
|
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
|
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
|
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
|
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
|
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
|
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
|
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
|
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
|
.MEM_CK_WIDTH(MEM_CK_WIDTH),
|
.MEM_CK_WIDTH(MEM_CK_WIDTH),
|
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
|
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
|
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
|
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
|
.MEM_DM_WIDTH(MEM_DM_WIDTH),
|
.MEM_DM_WIDTH(MEM_DM_WIDTH),
|
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
|
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
|
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
|
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
|
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
|
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
|
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
|
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
|
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
|
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
|
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
|
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
|
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
|
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
|
.IS_HHP_HPS(IS_HHP_HPS)
|
.IS_HHP_HPS(IS_HHP_HPS)
|
) uio_pads (
|
) uio_pads (
|
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
|
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
|
.reset_n_afi_clk (reset_n_afi_clk[1]),
|
.reset_n_afi_clk (reset_n_afi_clk[1]),
|
.oct_ctl_rs_value (oct_ctl_rs_value),
|
.oct_ctl_rs_value (oct_ctl_rs_value),
|
.oct_ctl_rt_value (oct_ctl_rt_value),
|
.oct_ctl_rt_value (oct_ctl_rt_value),
|
.phy_ddio_address (phy_ddio_address),
|
.phy_ddio_address (phy_ddio_address),
|
.phy_ddio_bank (phy_ddio_bank),
|
.phy_ddio_bank (phy_ddio_bank),
|
.phy_ddio_cs_n (phy_ddio_cs_n),
|
.phy_ddio_cs_n (phy_ddio_cs_n),
|
.phy_ddio_cke (phy_ddio_cke),
|
.phy_ddio_cke (phy_ddio_cke),
|
.phy_ddio_odt (phy_ddio_odt),
|
.phy_ddio_odt (phy_ddio_odt),
|
.phy_ddio_we_n (phy_ddio_we_n),
|
.phy_ddio_we_n (phy_ddio_we_n),
|
.phy_ddio_ras_n (phy_ddio_ras_n),
|
.phy_ddio_ras_n (phy_ddio_ras_n),
|
.phy_ddio_cas_n (phy_ddio_cas_n),
|
.phy_ddio_cas_n (phy_ddio_cas_n),
|
.phy_ddio_ck (phy_ddio_ck),
|
.phy_ddio_ck (phy_ddio_ck),
|
.phy_ddio_reset_n (phy_ddio_reset_n),
|
.phy_ddio_reset_n (phy_ddio_reset_n),
|
.phy_mem_address (mem_a),
|
.phy_mem_address (mem_a),
|
.phy_mem_bank (mem_ba),
|
.phy_mem_bank (mem_ba),
|
.phy_mem_cs_n (mem_cs_n),
|
.phy_mem_cs_n (mem_cs_n),
|
.phy_mem_cke (mem_cke),
|
.phy_mem_cke (mem_cke),
|
.phy_mem_odt (mem_odt),
|
.phy_mem_odt (mem_odt),
|
.phy_mem_we_n (mem_we_n),
|
.phy_mem_we_n (mem_we_n),
|
.phy_mem_ras_n (mem_ras_n),
|
.phy_mem_ras_n (mem_ras_n),
|
.phy_mem_cas_n (mem_cas_n),
|
.phy_mem_cas_n (mem_cas_n),
|
.phy_mem_reset_n (mem_reset_n),
|
.phy_mem_reset_n (mem_reset_n),
|
.pll_afi_clk (pll_afi_clk),
|
.pll_afi_clk (pll_afi_clk),
|
.pll_mem_clk (pll_mem_clk),
|
.pll_mem_clk (pll_mem_clk),
|
.pll_afi_phy_clk (pll_afi_phy_clk),
|
.pll_afi_phy_clk (pll_afi_phy_clk),
|
.pll_avl_phy_clk (pll_avl_phy_clk),
|
.pll_avl_phy_clk (pll_avl_phy_clk),
|
.pll_avl_clk (pll_avl_clk),
|
.pll_avl_clk (pll_avl_clk),
|
.avl_clk (avl_clk),
|
.avl_clk (avl_clk),
|
.pll_mem_phy_clk (pll_mem_phy_clk),
|
.pll_mem_phy_clk (pll_mem_phy_clk),
|
.pll_write_clk (pll_write_clk),
|
.pll_write_clk (pll_write_clk),
|
.pll_dqs_ena_clk (pll_dqs_ena_clk),
|
.pll_dqs_ena_clk (pll_dqs_ena_clk),
|
.pll_addr_cmd_clk (adc_clk_cps),
|
.pll_addr_cmd_clk (adc_clk_cps),
|
.phy_mem_dq (mem_dq),
|
.phy_mem_dq (mem_dq),
|
.phy_mem_dm (mem_dm),
|
.phy_mem_dm (mem_dm),
|
.phy_mem_ck (mem_ck),
|
.phy_mem_ck (mem_ck),
|
.phy_mem_ck_n (mem_ck_n),
|
.phy_mem_ck_n (mem_ck_n),
|
.mem_dqs (mem_dqs),
|
.mem_dqs (mem_dqs),
|
.mem_dqs_n (mem_dqs_n),
|
.mem_dqs_n (mem_dqs_n),
|
.dll_phy_delayctrl (dll_phy_delayctrl),
|
.dll_phy_delayctrl (dll_phy_delayctrl),
|
.scc_clk (pll_config_clk),
|
.scc_clk (pll_config_clk),
|
.scc_data (scc_data),
|
.scc_data (scc_data),
|
.scc_dqs_ena (scc_dqs_ena),
|
.scc_dqs_ena (scc_dqs_ena),
|
.scc_dqs_io_ena (scc_dqs_io_ena),
|
.scc_dqs_io_ena (scc_dqs_io_ena),
|
.scc_dq_ena (scc_dq_ena),
|
.scc_dq_ena (scc_dq_ena),
|
.scc_dm_ena (scc_dm_ena),
|
.scc_dm_ena (scc_dm_ena),
|
.scc_upd (scc_upd[0]),
|
.scc_upd (scc_upd[0]),
|
.phy_ddio_dmdout (phy_ddio_dmdout),
|
.phy_ddio_dmdout (phy_ddio_dmdout),
|
.phy_ddio_dqdout (phy_ddio_dqdout),
|
.phy_ddio_dqdout (phy_ddio_dqdout),
|
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
|
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
|
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
|
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
|
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
|
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
|
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
|
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
|
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
|
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
|
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
|
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
|
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
|
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
|
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
|
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
|
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
|
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
|
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
|
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
|
.ddio_phy_dqdin (ddio_phy_dqdin),
|
.ddio_phy_dqdin (ddio_phy_dqdin),
|
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
|
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
|
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
|
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
|
.phy_ddio_dqoe (phy_ddio_dqoe),
|
.phy_ddio_dqoe (phy_ddio_dqoe),
|
.capture_strobe_tracking (capture_strobe_tracking)
|
.capture_strobe_tracking (capture_strobe_tracking)
|
);
|
);
|
|
|
|
|
|
|
generate
|
generate
|
if (IS_HHP_HPS != "true") begin
|
if (IS_HHP_HPS != "true") begin
|
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
|
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
|
always @(posedge pll_afi_clk)
|
always @(posedge pll_afi_clk)
|
afi_clk_reg <= ~afi_clk_reg;
|
afi_clk_reg <= ~afi_clk_reg;
|
|
|
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
|
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
|
always @(posedge pll_afi_half_clk)
|
always @(posedge pll_afi_half_clk)
|
afi_half_clk_reg <= ~afi_half_clk_reg;
|
afi_half_clk_reg <= ~afi_half_clk_reg;
|
|
|
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
|
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
|
always @(posedge pll_avl_clk)
|
always @(posedge pll_avl_clk)
|
avl_clk_reg <= ~avl_clk_reg;
|
avl_clk_reg <= ~avl_clk_reg;
|
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
|
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
|
always @(posedge pll_config_clk)
|
always @(posedge pll_config_clk)
|
config_clk_reg <= ~config_clk_reg;
|
config_clk_reg <= ~config_clk_reg;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
|
|
|
|
// Calculate the ceiling of log_2 of the input value
|
// Calculate the ceiling of log_2 of the input value
|
function integer ceil_log2;
|
function integer ceil_log2;
|
input integer value;
|
input integer value;
|
begin
|
begin
|
value = value - 1;
|
value = value - 1;
|
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
|
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
|
value = value >> 1;
|
value = value >> 1;
|
end
|
end
|
endfunction
|
endfunction
|
|
|
endmodule
|
endmodule
|
|
|
