// (C) 2001-2017 Intel Corporation. All rights reserved.
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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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// (C) 2001-2013 Altera Corporation. All rights reserved.
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// (C) 2001-2013 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
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// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
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// $Revision: #1 $
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// $Revision: #1 $
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// $Date: 2013/09/09 $
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// $Date: 2013/09/09 $
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// $Author: dmunday $
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// $Author: dmunday $
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// --------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------
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//| Avalon Streaming Error Adapter
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//| Avalon Streaming Error Adapter
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// --------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------
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`timescale 1ns / 100ps
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`timescale 1ns / 100ps
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// ------------------------------------------
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// ------------------------------------------
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// Generation parameters:
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// Generation parameters:
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// output_name: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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// output_name: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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// use_ready: true
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// use_ready: true
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// use_packets: false
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// use_packets: false
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// use_empty: 0
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// use_empty: 0
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// empty_width: 0
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// empty_width: 0
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// data_width: 34
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// data_width: 34
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// channel_width: 0
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// channel_width: 0
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// in_error_width: 0
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// in_error_width: 0
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// out_error_width: 1
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// out_error_width: 1
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// in_errors_list
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// in_errors_list
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// in_errors_indices 0
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// in_errors_indices 0
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// out_errors_list
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// out_errors_list
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// has_in_error_desc: FALSE
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// has_in_error_desc: FALSE
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// has_out_error_desc: FALSE
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// has_out_error_desc: FALSE
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// out_has_other: FALSE
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// out_has_other: FALSE
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// out_other_index: -1
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// out_other_index: -1
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// dumpVar:
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// dumpVar:
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// inString: in_error[
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// inString: in_error[
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// closeString: ] |
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// closeString: ] |
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// ------------------------------------------
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// ------------------------------------------
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module ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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module ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0
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(
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(
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// Interface: in
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// Interface: in
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output reg in_ready,
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output reg in_ready,
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input in_valid,
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input in_valid,
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input [34-1: 0] in_data,
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input [34-1: 0] in_data,
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// Interface: out
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// Interface: out
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input out_ready,
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input out_ready,
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output reg out_valid,
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output reg out_valid,
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output reg [34-1: 0] out_data,
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output reg [34-1: 0] out_data,
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output reg [0:0] out_error,
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output reg [0:0] out_error,
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// Interface: clk
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// Interface: clk
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input clk,
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input clk,
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// Interface: reset
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// Interface: reset
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input reset_n
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input reset_n
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/*AUTOARG*/);
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/*AUTOARG*/);
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reg in_error = 0;
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reg in_error = 0;
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initial in_error = 0;
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initial in_error = 0;
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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//| Pass-through Mapping
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//| Pass-through Mapping
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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always_comb begin
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always_comb begin
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in_ready = out_ready;
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in_ready = out_ready;
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out_valid = in_valid;
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out_valid = in_valid;
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out_data = in_data;
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out_data = in_data;
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end
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end
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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//| Error Mapping
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//| Error Mapping
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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always_comb begin
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always_comb begin
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out_error = 0;
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out_error = 0;
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out_error = in_error;
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out_error = in_error;
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end //always @*
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end //always @*
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endmodule
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endmodule
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