// (C) 2001-2017 Intel Corporation. All rights reserved.
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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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// (C) 2001-2014 Altera Corporation. All rights reserved.
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// (C) 2001-2014 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// Your use of Altera Corporation's design tools, logic functions and other
|
// software and tools, and its AMPP partner logic functions, and any output
|
// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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// $Id: //acds/rel/17.0std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
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// $Id: //acds/rel/17.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
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// $Revision: #1 $
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// $Revision: #1 $
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// $Date: 2017/01/22 $
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// $Date: 2017/07/30 $
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// $Author: swbranch $
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// $Author: swbranch $
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// ------------------------------------------
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// ------------------------------------------
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// Merlin Multiplexer
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// Merlin Multiplexer
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// ------------------------------------------
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// ------------------------------------------
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`timescale 1 ns / 1 ns
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`timescale 1 ns / 1 ns
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// ------------------------------------------
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// ------------------------------------------
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// Generation parameters:
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// Generation parameters:
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// output_name: ulight_fifo_mm_interconnect_0_cmd_mux
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// output_name: ulight_fifo_mm_interconnect_0_cmd_mux
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// NUM_INPUTS: 2
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// NUM_INPUTS: 2
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// ARBITRATION_SHARES: 1 1
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// ARBITRATION_SHARES: 1 1
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// ARBITRATION_SCHEME "round-robin"
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// ARBITRATION_SCHEME "round-robin"
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// PIPELINE_ARB: 1
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// PIPELINE_ARB: 1
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// PKT_TRANS_LOCK: 70 (arbitration locking enabled)
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// PKT_TRANS_LOCK: 70 (arbitration locking enabled)
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// ST_DATA_W: 129
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// ST_DATA_W: 129
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// ST_CHANNEL_W: 22
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// ST_CHANNEL_W: 22
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// ------------------------------------------
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// ------------------------------------------
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module ulight_fifo_mm_interconnect_0_cmd_mux
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module ulight_fifo_mm_interconnect_0_cmd_mux
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(
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(
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// ----------------------
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// ----------------------
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// Sinks
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// Sinks
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// ----------------------
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// ----------------------
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input sink0_valid,
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input sink0_valid,
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input [129-1 : 0] sink0_data,
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input [129-1 : 0] sink0_data,
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input [22-1: 0] sink0_channel,
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input [22-1: 0] sink0_channel,
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input sink0_startofpacket,
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input sink0_startofpacket,
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input sink0_endofpacket,
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input sink0_endofpacket,
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output sink0_ready,
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output sink0_ready,
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input sink1_valid,
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input sink1_valid,
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input [129-1 : 0] sink1_data,
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input [129-1 : 0] sink1_data,
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input [22-1: 0] sink1_channel,
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input [22-1: 0] sink1_channel,
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input sink1_startofpacket,
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input sink1_startofpacket,
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input sink1_endofpacket,
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input sink1_endofpacket,
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output sink1_ready,
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output sink1_ready,
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// ----------------------
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// ----------------------
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// Source
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// Source
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// ----------------------
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// ----------------------
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output src_valid,
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output src_valid,
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output [129-1 : 0] src_data,
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output [129-1 : 0] src_data,
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output [22-1 : 0] src_channel,
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output [22-1 : 0] src_channel,
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output src_startofpacket,
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output src_startofpacket,
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output src_endofpacket,
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output src_endofpacket,
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input src_ready,
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input src_ready,
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// ----------------------
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// ----------------------
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// Clock & Reset
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// Clock & Reset
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// ----------------------
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// ----------------------
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input clk,
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input clk,
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input reset
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input reset
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);
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);
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localparam PAYLOAD_W = 129 + 22 + 2;
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localparam PAYLOAD_W = 129 + 22 + 2;
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localparam NUM_INPUTS = 2;
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localparam NUM_INPUTS = 2;
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localparam SHARE_COUNTER_W = 1;
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localparam SHARE_COUNTER_W = 1;
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localparam PIPELINE_ARB = 1;
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localparam PIPELINE_ARB = 1;
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localparam ST_DATA_W = 129;
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localparam ST_DATA_W = 129;
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localparam ST_CHANNEL_W = 22;
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localparam ST_CHANNEL_W = 22;
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localparam PKT_TRANS_LOCK = 70;
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localparam PKT_TRANS_LOCK = 70;
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// ------------------------------------------
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// ------------------------------------------
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// Signals
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// Signals
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// ------------------------------------------
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// ------------------------------------------
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wire [NUM_INPUTS - 1 : 0] request;
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wire [NUM_INPUTS - 1 : 0] request;
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wire [NUM_INPUTS - 1 : 0] valid;
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wire [NUM_INPUTS - 1 : 0] valid;
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wire [NUM_INPUTS - 1 : 0] grant;
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wire [NUM_INPUTS - 1 : 0] grant;
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wire [NUM_INPUTS - 1 : 0] next_grant;
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wire [NUM_INPUTS - 1 : 0] next_grant;
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reg [NUM_INPUTS - 1 : 0] saved_grant;
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reg [NUM_INPUTS - 1 : 0] saved_grant;
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reg [PAYLOAD_W - 1 : 0] src_payload;
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reg [PAYLOAD_W - 1 : 0] src_payload;
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wire last_cycle;
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wire last_cycle;
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reg packet_in_progress;
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reg packet_in_progress;
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reg update_grant;
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reg update_grant;
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wire [PAYLOAD_W - 1 : 0] sink0_payload;
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wire [PAYLOAD_W - 1 : 0] sink0_payload;
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wire [PAYLOAD_W - 1 : 0] sink1_payload;
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wire [PAYLOAD_W - 1 : 0] sink1_payload;
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assign valid[0] = sink0_valid;
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assign valid[0] = sink0_valid;
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assign valid[1] = sink1_valid;
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assign valid[1] = sink1_valid;
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wire [NUM_INPUTS - 1 : 0] eop;
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wire [NUM_INPUTS - 1 : 0] eop;
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assign eop[0] = sink0_endofpacket;
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assign eop[0] = sink0_endofpacket;
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assign eop[1] = sink1_endofpacket;
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assign eop[1] = sink1_endofpacket;
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// ------------------------------------------
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// ------------------------------------------
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// ------------------------------------------
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// ------------------------------------------
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// Grant Logic & Updates
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// Grant Logic & Updates
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// ------------------------------------------
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// ------------------------------------------
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// ------------------------------------------
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// ------------------------------------------
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reg [NUM_INPUTS - 1 : 0] lock;
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reg [NUM_INPUTS - 1 : 0] lock;
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always @* begin
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always @* begin
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lock[0] = sink0_data[70];
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lock[0] = sink0_data[70];
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lock[1] = sink1_data[70];
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lock[1] = sink1_data[70];
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end
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end
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reg [NUM_INPUTS - 1 : 0] locked = '0;
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reg [NUM_INPUTS - 1 : 0] locked = '0;
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always @(posedge clk or posedge reset) begin
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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if (reset) begin
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locked <= '0;
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locked <= '0;
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end
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end
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else begin
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else begin
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locked <= next_grant & lock;
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locked <= next_grant & lock;
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end
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end
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end
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end
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assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
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assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
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// ------------------------------------------
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// ------------------------------------------
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// We're working on a packet at any time valid is high, except
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// We're working on a packet at any time valid is high, except
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// when this is the endofpacket.
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// when this is the endofpacket.
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// ------------------------------------------
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// ------------------------------------------
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always @(posedge clk or posedge reset) begin
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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if (reset) begin
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packet_in_progress <= 1'b0;
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packet_in_progress <= 1'b0;
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end
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end
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else begin
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else begin
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if (last_cycle)
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if (last_cycle)
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packet_in_progress <= 1'b0;
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packet_in_progress <= 1'b0;
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else if (src_valid)
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else if (src_valid)
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packet_in_progress <= 1'b1;
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packet_in_progress <= 1'b1;
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end
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end
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end
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end
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// ------------------------------------------
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// ------------------------------------------
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// Shares
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// Shares
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//
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//
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// Special case: all-equal shares _should_ be optimized into assigning a
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// Special case: all-equal shares _should_ be optimized into assigning a
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// constant to next_grant_share.
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// constant to next_grant_share.
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// Special case: all-1's shares _should_ result in the share counter
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// Special case: all-1's shares _should_ result in the share counter
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// being optimized away.
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// being optimized away.
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// ------------------------------------------
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// ------------------------------------------
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// Input | arb shares | counter load value
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// Input | arb shares | counter load value
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// 0 | 1 | 0
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// 0 | 1 | 0
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// 1 | 1 | 0
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// 1 | 1 | 0
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wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
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wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
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// ------------------------------------------
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// ------------------------------------------
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// Choose the share value corresponding to the grant.
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// Choose the share value corresponding to the grant.
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// ------------------------------------------
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// ------------------------------------------
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reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
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reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
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always @* begin
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always @* begin
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next_grant_share =
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next_grant_share =
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share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
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share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
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share_1 & { SHARE_COUNTER_W {next_grant[1]} };
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share_1 & { SHARE_COUNTER_W {next_grant[1]} };
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end
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end
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// ------------------------------------------
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// ------------------------------------------
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// Flag to indicate first packet of an arb sequence.
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// Flag to indicate first packet of an arb sequence.
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// ------------------------------------------
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// ------------------------------------------
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// ------------------------------------------
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// ------------------------------------------
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// Compute the next share-count value.
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// Compute the next share-count value.
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// ------------------------------------------
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// ------------------------------------------
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reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
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reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
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reg [SHARE_COUNTER_W - 1 : 0] share_count;
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reg [SHARE_COUNTER_W - 1 : 0] share_count;
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reg share_count_zero_flag;
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reg share_count_zero_flag;
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always @* begin
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always @* begin
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// Update the counter, but don't decrement below 0.
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// Update the counter, but don't decrement below 0.
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p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
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p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
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end
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end
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// ------------------------------------------
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// ------------------------------------------
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// Update the share counter and share-counter=zero flag.
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// Update the share counter and share-counter=zero flag.
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// ------------------------------------------
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// ------------------------------------------
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always @(posedge clk or posedge reset) begin
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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if (reset) begin
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share_count <= '0;
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share_count <= '0;
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share_count_zero_flag <= 1'b1;
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share_count_zero_flag <= 1'b1;
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end
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end
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else begin
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else begin
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if (update_grant) begin
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if (update_grant) begin
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share_count <= next_grant_share;
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share_count <= next_grant_share;
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share_count_zero_flag <= (next_grant_share == '0);
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share_count_zero_flag <= (next_grant_share == '0);
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end
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end
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else if (last_cycle) begin
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else if (last_cycle) begin
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share_count <= p1_share_count;
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share_count <= p1_share_count;
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share_count_zero_flag <= (p1_share_count == '0);
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share_count_zero_flag <= (p1_share_count == '0);
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end
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end
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end
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end
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end
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end
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always @* begin
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always @* begin
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update_grant = 0;
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update_grant = 0;
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// ------------------------------------------
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// ------------------------------------------
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// The pipeline delays grant by one cycle, so
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// The pipeline delays grant by one cycle, so
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// we have to calculate the update_grant signal
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// we have to calculate the update_grant signal
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// one cycle ahead of time.
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// one cycle ahead of time.
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//
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//
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// Possible optimization: omit the first clause
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// Possible optimization: omit the first clause
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// "if (!packet_in_progress & ~src_valid) ..."
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// "if (!packet_in_progress & ~src_valid) ..."
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// cost: one idle cycle at the the beginning of each
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// cost: one idle cycle at the the beginning of each
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// grant cycle.
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// grant cycle.
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// benefit: save a small amount of logic.
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// benefit: save a small amount of logic.
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// ------------------------------------------
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// ------------------------------------------
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if (!packet_in_progress & !src_valid)
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if (!packet_in_progress & !src_valid)
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update_grant = 1;
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update_grant = 1;
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if (last_cycle && share_count_zero_flag)
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if (last_cycle && share_count_zero_flag)
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update_grant = 1;
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update_grant = 1;
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end
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end
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wire save_grant;
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wire save_grant;
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assign save_grant = update_grant;
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assign save_grant = update_grant;
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assign grant = saved_grant;
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assign grant = saved_grant;
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always @(posedge clk, posedge reset) begin
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always @(posedge clk, posedge reset) begin
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if (reset)
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if (reset)
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saved_grant <= '0;
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saved_grant <= '0;
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else if (save_grant)
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else if (save_grant)
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saved_grant <= next_grant;
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saved_grant <= next_grant;
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end
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end
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// ------------------------------------------
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// ------------------------------------------
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// ------------------------------------------
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// ------------------------------------------
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// Arbitrator
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// Arbitrator
|
// ------------------------------------------
|
// ------------------------------------------
|
// ------------------------------------------
|
// ------------------------------------------
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|
|
// ------------------------------------------
|
// ------------------------------------------
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// Create a request vector that stays high during
|
// Create a request vector that stays high during
|
// the packet for unpipelined arbitration.
|
// the packet for unpipelined arbitration.
|
//
|
//
|
// The pipelined arbitration scheme does not require
|
// The pipelined arbitration scheme does not require
|
// request to be held high during the packet.
|
// request to be held high during the packet.
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// ------------------------------------------
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// ------------------------------------------
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reg [NUM_INPUTS - 1 : 0] prev_request;
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reg [NUM_INPUTS - 1 : 0] prev_request;
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always @(posedge clk, posedge reset) begin
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always @(posedge clk, posedge reset) begin
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if (reset)
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if (reset)
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prev_request <= '0;
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prev_request <= '0;
|
else
|
else
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prev_request <= request & ~(valid & eop);
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prev_request <= request & ~(valid & eop);
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end
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end
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assign request = (PIPELINE_ARB == 1) ? valid | locked :
|
assign request = (PIPELINE_ARB == 1) ? valid | locked :
|
prev_request | valid | locked;
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prev_request | valid | locked;
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wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
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wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
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altera_merlin_arbitrator
|
altera_merlin_arbitrator
|
#(
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#(
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.NUM_REQUESTERS(NUM_INPUTS),
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.NUM_REQUESTERS(NUM_INPUTS),
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.SCHEME ("round-robin"),
|
.SCHEME ("round-robin"),
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.PIPELINE (1)
|
.PIPELINE (1)
|
) arb (
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) arb (
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.request (request),
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.request (request),
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.grant (next_grant_from_arb),
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.grant (next_grant_from_arb),
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.save_top_priority (src_valid),
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.save_top_priority (src_valid),
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.increment_top_priority (update_grant)
|
.increment_top_priority (update_grant)
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);
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);
|
|
|
assign next_grant = next_grant_from_arb;
|
assign next_grant = next_grant_from_arb;
|
|
|
// ------------------------------------------
|
// ------------------------------------------
|
// ------------------------------------------
|
// ------------------------------------------
|
// Mux
|
// Mux
|
//
|
//
|
// Implemented as a sum of products.
|
// Implemented as a sum of products.
|
// ------------------------------------------
|
// ------------------------------------------
|
// ------------------------------------------
|
// ------------------------------------------
|
|
|
assign sink0_ready = src_ready && grant[0];
|
assign sink0_ready = src_ready && grant[0];
|
assign sink1_ready = src_ready && grant[1];
|
assign sink1_ready = src_ready && grant[1];
|
|
|
assign src_valid = |(grant & valid);
|
assign src_valid = |(grant & valid);
|
|
|
always @* begin
|
always @* begin
|
src_payload =
|
src_payload =
|
sink0_payload & {PAYLOAD_W {grant[0]} } |
|
sink0_payload & {PAYLOAD_W {grant[0]} } |
|
sink1_payload & {PAYLOAD_W {grant[1]} };
|
sink1_payload & {PAYLOAD_W {grant[1]} };
|
end
|
end
|
|
|
// ------------------------------------------
|
// ------------------------------------------
|
// Mux Payload Mapping
|
// Mux Payload Mapping
|
// ------------------------------------------
|
// ------------------------------------------
|
|
|
assign sink0_payload = {sink0_channel,sink0_data,
|
assign sink0_payload = {sink0_channel,sink0_data,
|
sink0_startofpacket,sink0_endofpacket};
|
sink0_startofpacket,sink0_endofpacket};
|
assign sink1_payload = {sink1_channel,sink1_data,
|
assign sink1_payload = {sink1_channel,sink1_data,
|
sink1_startofpacket,sink1_endofpacket};
|
sink1_startofpacket,sink1_endofpacket};
|
|
|
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
|
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
|
endmodule
|
endmodule
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|
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|
|
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|
