//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME :
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//DEPARTMENT : IC Design / Verification
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH [32,16] : width of the DATA : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy :
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//Clock Domains :
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//Critical Timing :
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//Test Features :
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//Asynchronous I/F :
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//Scan Methodology :
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//Instantiations :
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//Synthesizable (y/n) :
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//Other :
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//-FHDR------------------------------------------------------------------------
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#ifndef CONTROL_SC_H
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#ifndef CONTROL_SC_H
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#define CONTROL_SC_H
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#define CONTROL_SC_H
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class Control_SC
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class Control_SC
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{
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{
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public:
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public:
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/*Constructor*/
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/*Constructor*/
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Control_SC();
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Control_SC();
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/*initialize systemC model*/
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/*initialize systemC model*/
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virtual void init();
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virtual void init();
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/*Reset the model*/
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/*Reset the model*/
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virtual bool reset_set();
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virtual bool reset_set();
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/*Run the Env for ammount off time*/
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/*Run the Env for ammount off time*/
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virtual void run_sim();
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virtual void run_sim();
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/*Tell to SystemC to finish*/
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/*Tell to SystemC to finish*/
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virtual void stop_sim();
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virtual void stop_sim();
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/*get dout */
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/*get dout */
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virtual unsigned int get_value_dout();
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virtual unsigned int get_value_dout();
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/*get sout*/
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/*get sout*/
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virtual unsigned int get_value_sout();
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virtual unsigned int get_value_sout();
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/*set sin*/
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/*set sin*/
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virtual void set_rx_sin(unsigned int strobe);
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virtual void set_rx_sin(unsigned int strobe);
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/*set din*/
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/*set din*/
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virtual void set_rx_din(unsigned int data);
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virtual void set_rx_din(unsigned int data);
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virtual unsigned int get_spw_fsm();
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virtual unsigned int get_spw_fsm();
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virtual unsigned int finish_simulation();
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virtual unsigned int finish_simulation();
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//verilog variables
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//verilog variables
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virtual bool verilog_linkenable();
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virtual bool verilog_linkenable();
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virtual bool verilog_autostart();
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virtual bool verilog_autostart();
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virtual bool verilog_linkdisable();
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virtual bool verilog_linkdisable();
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virtual float verilog_frequency();
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virtual float verilog_frequency();
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//tests
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//tests
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virtual bool start_tx_test();
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virtual bool start_tx_test();
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virtual bool enable_time_code_tx_test();
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virtual bool enable_time_code_tx_test();
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virtual void end_tx_test();
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virtual void end_tx_test();
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virtual unsigned int take_data(unsigned int a);
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virtual unsigned int take_data(unsigned int a);
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virtual int size_data_test();
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virtual int size_data_test_vlog();
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virtual int size_data_test_sc();
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virtual void data_o(unsigned int data, unsigned int pos);
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virtual void data_o(unsigned int data, unsigned int pos);
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virtual void data_rx_vlog_loopback_o(unsigned int data, unsigned int pos);
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virtual unsigned int clock_tx();
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virtual unsigned int clock_tx();
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};
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};
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#endif
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#endif
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