`include "aDefinitions.v"
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`include "aDefinitions.v"
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module ReservationStation
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module ReservationStation
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
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input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
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input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
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input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
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input wire [3:0] iMyId,
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input wire [3:0] iMyId,
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input wire iExecutionDone,
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input wire iExecutionDone,
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input wire iCommitGranted,
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input wire iCommitGranted,
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input wire [`DATA_ROW_WIDTH-1:0] iResult,
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input wire [`DATA_ROW_WIDTH-1:0] iResult,
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output wire [`DATA_ROW_WIDTH-1:0] oSource1,
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output wire [`DATA_ROW_WIDTH-1:0] oSource1,
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output wire [`DATA_ROW_WIDTH-1:0] oSource0,
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output wire [`DATA_ROW_WIDTH-1:0] oSource0,
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output wire [2:0] oScale,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
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output wire [`DATA_ROW_WIDTH-1:0] oResult,
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output wire [`DATA_ROW_WIDTH-1:0] oResult,
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output wire [2:0] oWE,
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output wire [2:0] oWE,
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output wire [3:0] oId,
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output wire [3:0] oId,
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output wire oBusy,
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output wire oBusy,
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output wire oTrigger,
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output wire oTrigger,
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output wire oCommitRequest,
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output wire oCommitRequest,
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output wire [`DATA_ROW_WIDTH-1:0] oSrc0Latched,oSrc1Latched
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output wire [`DATA_ROW_WIDTH-1:0] oSrc0Latched,oSrc1Latched
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);
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);
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wire wStall;
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wire wStall;
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wire wLatchRequest;
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wire wLatchRequest;
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wire [3:0] wSource1_RS;
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wire [3:0] wSource1_RS;
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wire [3:0] wSource0_RS;
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wire [3:0] wSource0_RS;
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//wire [3:0] wMyId;
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//wire [3:0] wMyId;
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wire wTrigger;
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wire wTrigger;
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//wire wFIFO_Pop;
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//wire wFIFO_Pop;
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wire [`MOD_ISSUE_PACKET_SIZE-1:0] wIssue_Latched;
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wire [`MOD_ISSUE_PACKET_SIZE-1:0] wIssue_Latched;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
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wire [3:0] wID;
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wire [3:0] wID;
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wire [2:0] wWE;
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wire [2:0] wWE;
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wire wCommitFifoFull;
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wire wCommitFifoFull;
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wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
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wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
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assign oScale = wScale;
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//assign wFIFO_Pop = iExecutionDone;
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//assign wFIFO_Pop = iExecutionDone;
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assign oCommitRequest = iExecutionDone;
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assign oCommitRequest = iExecutionDone;
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assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
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assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
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//If there are no dependencies then just trigger execution
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//If there are no dependencies then just trigger execution
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//assign oTrigger = (wTrigger /*&& (iIssueBus[`ISSUE_SRC0RS_RNG] == 0) && (iIssueBus[`ISSUE_SRC1RS_RNG] == 0)*/ ) ? 1'b1 : 0;
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//assign oTrigger = (wTrigger /*&& (iIssueBus[`ISSUE_SRC0RS_RNG] == 0) && (iIssueBus[`ISSUE_SRC1RS_RNG] == 0)*/ ) ? 1'b1 : 0;
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assign oTrigger = ( (wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus) & ~wStall);
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assign oTrigger = ( (wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus) & ~wStall);
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assign wStall = (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ? 1'b1 : 1'b0;
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assign wStall = (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ? 1'b1 : 1'b0;
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//assign wStall = (wSource1_RS == 0 & wSource0_RS == 0) ? 1'b0 : 1'b1;
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//assign wStall = (wSource1_RS == 0 & wSource0_RS == 0) ? 1'b0 : 1'b1;
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wire wLatchData0FromCommitBus;
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wire wLatchData0FromCommitBus;
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wire wLatchData1FromCommitBus;
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wire wLatchData1FromCommitBus;
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assign wLatchData0FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS)) ? 1'b1 : 1'b0;
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assign wLatchData0FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS)) ? 1'b1 : 1'b0;
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assign wLatchData1FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS)) ? 1'b1 : 1'b0;
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assign wLatchData1FromCommitBus = ((wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS)) ? 1'b1 : 1'b0;
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wire wBusy;
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wire wBusy;
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assign oBusy = wBusy | wCommitFifoFull & ~iCommitGranted;
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assign oBusy = wBusy | wCommitFifoFull & ~iCommitGranted;
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wire wCommitGrantedDelay;
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wire wCommitGrantedDelay;
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UPCOUNTER_POSEDGE # ( 1 ) BUSY
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UPCOUNTER_POSEDGE # ( 1 ) BUSY
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( wLatchRequest | iCommitGranted ),
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.Enable( wLatchRequest | iCommitGranted ),
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.Initial( 1'b0 ),
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.Initial( 1'b0 ),
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.Q( wBusy )
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.Q( wBusy )
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);
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);
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assign oSource1 = (wLatchData0FromCommitBus) ? iCommitBus[`MOD_COMMIT_DATA_RNG] : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
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assign oSource1 = (wLatchData0FromCommitBus) ? iCommitBus[`MOD_COMMIT_DATA_RNG] : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
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assign oSource0 = (wLatchData1FromCommitBus) ? (/*(wDstZero)?`DATA_ROW_WIDTH'b0:*/iCommitBus[`MOD_COMMIT_DATA_RNG]) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
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assign oSource0 = (wLatchData1FromCommitBus) ? (/*(wDstZero)?`DATA_ROW_WIDTH'b0:*/iCommitBus[`MOD_COMMIT_DATA_RNG]) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
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assign wTrigger = ( wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus);
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assign wTrigger = ( wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus);
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wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0;
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wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0;
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//FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
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//FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
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//( Clock, Reset, wLatchRequest , iIssueBus, {wDstZero,wID,wWE,wDestination,wSource1_RS,wSource0_RS,wSrc1,wSrc0} );
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//( Clock, Reset, wLatchRequest , iIssueBus, {wDstZero,wID,wWE,wDestination,wSource1_RS,wSource0_RS,wSrc1,wSrc0} );
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wire [3:0] wScale;
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wire [3:0] wScale;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
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( Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
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( Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
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assign oSrc0Latched = wSrc0;
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assign oSrc0Latched = wSrc0;
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assign oSrc1Latched = wSrc1;
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assign oSrc1Latched = wSrc1;
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assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
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assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
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sync_fifo # (`COMMIT_PACKET_SIZE ) COMMIT_OUT_FIFO
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(
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.clk( Clock ),
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.reset( Reset ),
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.din( {wID,wWE,wDestination,iResult} ),
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.wr_en( iExecutionDone ),
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.rd_en( iCommitGranted ),
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.dout( {oId,oWE,oDestination,oResult} ),
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.full( wCommitFifoFull )
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);
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/*
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_Trigger
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( Clock, Reset, 1'b1 , wLatchRequest, wTrigger );
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*/
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endmodule
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module ReservationStation_EX
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(
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input wire Clock,
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input wire Reset,
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input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
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input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
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input wire [3:0] iMyId,
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input wire iExecutionDone,
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input wire iCommitGranted,
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input wire [`DATA_ROW_WIDTH-1:0] iResult,
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output wire [`DATA_ROW_WIDTH-1:0] oSource1,
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output wire [`DATA_ROW_WIDTH-1:0] oSource0,
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output wire [2:0] oScale,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
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output wire [`DATA_ROW_WIDTH-1:0] oResult,
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output wire [2:0] oWE,
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output wire [3:0] oId,
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output wire oBusy,
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output wire oTrigger,
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output wire oCommitRequest,
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output wire [`DATA_ROW_WIDTH-1:0] oSrc0Latched,oSrc1Latched
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);
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wire wStall;
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wire wLatchRequest;
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wire [3:0] wSource1_RS;
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wire [3:0] wSource0_RS;
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//wire [3:0] wMyId;
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wire wTrigger;
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//wire wFIFO_Pop;
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wire [`MOD_ISSUE_PACKET_SIZE-1:0] wIssue_Latched;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
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wire [3:0] wID;
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wire [2:0] wWE;
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wire wCommitFifoFull;
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wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
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assign oScale = wScale;
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//assign wFIFO_Pop = iExecutionDone;
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assign oCommitRequest = iExecutionDone;
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assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
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//If there are no dependencies then just trigger execution
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//assign oTrigger = (wTrigger /*&& (iIssueBus[`ISSUE_SRC0RS_RNG] == 0) && (iIssueBus[`ISSUE_SRC1RS_RNG] == 0)*/ ) ? 1'b1 : 0;
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wire wTrigger_Pre,wTrigger_Delay,DependencyResolved_Delay;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) ISSUE_FFDXXX
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( Clock, Reset, 1'b1 , wTrigger_Pre, wTrigger_Delay );
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) ISSUE_FFDYYY
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( Clock, Reset, 1'b1 , DependencyResolved, DependencyResolved_Delay );
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assign wTrigger_Pre = ((wLatchRequest & ~wStall) | DependencyResolved);//( (wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus) & ~wStall);
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//////////////HERE!!!!!!!!!!!!!!!!!!!!!
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//assign oTrigger = wTrigger_Pre;//(DependencyResolved) ? wTrigger_Pre : wTrigger_Delay;
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assign oTrigger = (DependencyResolved) ? wTrigger_Pre : (wTrigger_Delay & ~DependencyResolved_Delay);
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//////////////HERE!!!!!!!!!!!!!!!!!!!!!
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//assign wStall = (/*wLatchRequest*/(wBusy||wLatchRequest) && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ? 1'b1 : 1'b0;
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///assign wStall = ( (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ||
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//((wBusy ) && (wSource1_RS != 0 || wSource0_RS != 0) ) ) ? 1'b1 : 1'b0;
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wire DependencyDetected,DependencyResolved, wStall_Pre;
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assign DependencyDetected = (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0));
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assign DependencyResolved = ( wLatchData0FromCommitBus || wLatchData1FromCommitBus );
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UPCOUNTER_POSEDGE # ( 1 ) STALL
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.Enable( DependencyDetected | DependencyResolved ),
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.Initial( 1'b0 ),
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.Q( wStall_Pre )
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);
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assign wStall = ( (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) || wStall_Pre);
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//assign wStall = (wSource1_RS == 0 & wSource0_RS == 0) ? 1'b0 : 1'b1;
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wire wLatchData0FromCommitBus;
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wire wLatchData1FromCommitBus;
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assign wLatchData0FromCommitBus = ((wSource0_RS != 0) && (wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS)) ? 1'b1 : 1'b0;
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assign wLatchData1FromCommitBus = ((wSource1_RS != 0) && (wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS)) ? 1'b1 : 1'b0;
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wire wBusy;
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assign oBusy = wBusy | wCommitFifoFull & ~iCommitGranted;
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wire wCommitGrantedDelay;
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UPCOUNTER_POSEDGE # ( 1 ) BUSY
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.Enable( wLatchRequest | iCommitGranted ),
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.Initial( 1'b0 ),
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.Q( wBusy )
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);
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assign oSource0 = (wLatchData0FromCommitBus) ? iCommitBus[`MOD_COMMIT_DATA_RNG] : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
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assign oSource1 = (wLatchData1FromCommitBus) ? (iCommitBus[`MOD_COMMIT_DATA_RNG]) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
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assign wTrigger = ( wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus);
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wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0;
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//FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
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//( Clock, Reset, wLatchRequest , iIssueBus, {wDstZero,wID,wWE,wDestination,wSource1_RS,wSource0_RS,wSrc1,wSrc0} );
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wire [3:0] wScale;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
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( Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
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assign oSrc0Latched = (wLatchData0FromCommitBus)? oSource0 : wSrc0;
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assign oSrc1Latched = (wLatchData1FromCommitBus)? oSource1 : wSrc1;
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assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
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assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
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assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
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assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
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sync_fifo # (`COMMIT_PACKET_SIZE ) COMMIT_OUT_FIFO
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sync_fifo # (`COMMIT_PACKET_SIZE ) COMMIT_OUT_FIFO
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(
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(
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.clk( Clock ),
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.clk( Clock ),
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.reset( Reset ),
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.reset( Reset ),
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.din( {wID,wWE,wDestination,iResult} ),
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.din( {wID,wWE,wDestination,iResult} ),
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.wr_en( iExecutionDone ),
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.wr_en( iExecutionDone ),
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.rd_en( iCommitGranted ),
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.rd_en( iCommitGranted ),
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.dout( {oId,oWE,oDestination,oResult} ),
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.dout( {oId,oWE,oDestination,oResult} ),
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.full( wCommitFifoFull )
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.full( wCommitFifoFull )
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);
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);
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/*
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/*
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_Trigger
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_Trigger
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( Clock, Reset, 1'b1 , wLatchRequest, wTrigger );
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( Clock, Reset, 1'b1 , wLatchRequest, wTrigger );
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*/
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*/
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endmodule
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endmodule
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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module ReservationStation_1Cycle
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module ReservationStation_1Cycle
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
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input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
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input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
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input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
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input wire [3:0] iMyId,
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input wire [3:0] iMyId,
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input wire iExecutionDone,
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input wire iExecutionDone,
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input wire iCommitGranted,
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input wire iCommitGranted,
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input wire [`DATA_ROW_WIDTH-1:0] iResult,
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input wire [`DATA_ROW_WIDTH-1:0] iResult,
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output wire [`DATA_ROW_WIDTH-1:0] oSource1,
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output wire [`DATA_ROW_WIDTH-1:0] oSource1,
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output wire [`DATA_ROW_WIDTH-1:0] oSource0,
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output wire [`DATA_ROW_WIDTH-1:0] oSource0,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
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output wire [`DATA_ROW_WIDTH-1:0] oResult,
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output wire [`DATA_ROW_WIDTH-1:0] oResult,
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output wire [`SCALE_SIZE-1:0] oScale,
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output wire [`SCALE_SIZE-1:0] oScale,
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output wire [2:0] oWE,
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output wire [2:0] oWE,
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output wire [3:0] oId,
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output wire [3:0] oId,
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output wire oBusy,
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output wire oBusy,
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output wire oTrigger,
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output wire oTrigger,
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output wire oCommitRequest
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output wire oCommitRequest
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);
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);
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wire [3:0] wSource1_RS;
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wire [3:0] wSource1_RS;
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wire [3:0] wSource0_RS;
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wire [3:0] wSource0_RS;
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wire [3:0] wMyId;
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wire [3:0] wMyId;
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wire wTrigger;
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wire wTrigger;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
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wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
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wire [3:0] wID;
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wire [3:0] wID;
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wire [2:0] wWE;
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wire [2:0] wWE;
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wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0,wResult;
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wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0,wResult;
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//wire wDstZero;
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//wire wDstZero;
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wire [`DATA_ROW_WIDTH-1:0] wSrc1_Fwd;
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wire [`DATA_ROW_WIDTH-1:0] wSrc1_Fwd;
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wire [`DATA_ROW_WIDTH-1:0] wSrc0_Fwd;
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wire [`DATA_ROW_WIDTH-1:0] wSrc0_Fwd;
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wire wSrc0_Dependency_Initial, wSrc0_Dependency;
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wire wSrc0_Dependency_Initial, wSrc0_Dependency;
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wire wSrc1_Dependency_Initial, wSrc1_Dependency;
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wire wSrc1_Dependency_Initial, wSrc1_Dependency;
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wire wSrc0_DependencyResolved, wSrc0_DependencyLatch;
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wire wSrc0_DependencyResolved, wSrc0_DependencyLatch;
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wire wSrc1_DependencyResolved, wSrc1_DependencyLatch;
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wire wSrc1_DependencyResolved, wSrc1_DependencyLatch;
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wire wWaitingDependency;
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wire wWaitingDependency;
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wire wHandleCurrentIssue;
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wire wHandleCurrentIssue;
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wire wDependencyResolved;
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wire wDependencyResolved;
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wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
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wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
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wire wSrc0_DependencyLatch_Pre,wSrc1_DependencyLatch_Pre;
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wire wSrc0_DependencyLatch_Pre,wSrc1_DependencyLatch_Pre;
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assign wHandleCurrentIssue = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
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assign wHandleCurrentIssue = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
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assign wSrc0_Dependency_Initial = wHandleCurrentIssue & (iIssueBus[96] | iIssueBus[97] | iIssueBus[98] | iIssueBus[99]);
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assign wSrc0_Dependency_Initial = wHandleCurrentIssue & (iIssueBus[96] | iIssueBus[97] | iIssueBus[98] | iIssueBus[99]);
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assign wSrc1_Dependency_Initial = wHandleCurrentIssue & (iIssueBus[196] | iIssueBus[197] | iIssueBus[198] | iIssueBus[199]);
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assign wSrc1_Dependency_Initial = wHandleCurrentIssue & (iIssueBus[196] | iIssueBus[197] | iIssueBus[198] | iIssueBus[199]);
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assign oTrigger =
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assign oTrigger =
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(~wWaitingDependency & wHandleCurrentIssue & ~wSrc0_Dependency_Initial & ~wSrc1_Dependency_Initial)
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(~wWaitingDependency & wHandleCurrentIssue & ~wSrc0_Dependency_Initial & ~wSrc1_Dependency_Initial)
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|(wWaitingDependency & ~wSrc1_Dependency & wSrc0_Dependency & wSrc0_DependencyResolved )
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|(wWaitingDependency & ~wSrc1_Dependency & wSrc0_Dependency & wSrc0_DependencyResolved )
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|(wWaitingDependency & wSrc1_Dependency & ~wSrc0_Dependency & wSrc1_DependencyResolved )
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|(wWaitingDependency & wSrc1_Dependency & ~wSrc0_Dependency & wSrc1_DependencyResolved )
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|(wWaitingDependency & wSrc1_Dependency & wSrc0_Dependency & wSrc1_DependencyResolved & wSrc0_DependencyResolved );
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|(wWaitingDependency & wSrc1_Dependency & wSrc0_Dependency & wSrc1_DependencyResolved & wSrc0_DependencyResolved );
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assign wDependencyResolved = wWaitingDependency & ~wSrc1_Dependency & ~wSrc0_Dependency;
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assign wDependencyResolved = wWaitingDependency & ~wSrc1_Dependency & ~wSrc0_Dependency;
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assign wSrc0_DependencyLatch_Pre = ( wSrc0_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag0) ) ? 1'b1 : 1'b0;
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assign wSrc0_DependencyLatch_Pre = ( wSrc0_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag0) ) ? 1'b1 : 1'b0;
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assign wSrc1_DependencyLatch_Pre = ( wSrc1_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag1) ) ? 1'b1 : 1'b0;
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assign wSrc1_DependencyLatch_Pre = ( wSrc1_Dependency && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS && iCommitBus[`MOD_COMMIT_TAG_RNG] == wTag1) ) ? 1'b1 : 1'b0;
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PULSE P1 ( Clock,Reset, 1'b1, wSrc0_DependencyLatch_Pre, wSrc0_DependencyLatch);
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PULSE P1 ( Clock,Reset, 1'b1, wSrc0_DependencyLatch_Pre, wSrc0_DependencyLatch);
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PULSE P2 ( Clock,Reset, 1'b1, wSrc1_DependencyLatch_Pre, wSrc1_DependencyLatch);
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PULSE P2 ( Clock,Reset, 1'b1, wSrc1_DependencyLatch_Pre, wSrc1_DependencyLatch);
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wire wWaitingForCommitGranted;
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wire wWaitingForCommitGranted;
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UPCOUNTER_POSEDGE # ( 1 ) FFD_101
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UPCOUNTER_POSEDGE # ( 1 ) FFD_101
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( Clock, Reset, 1'b0, (oBusy & (iCommitGranted ^ wDependencyResolved) ), wWaitingForCommitGranted );
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( Clock, Reset, 1'b0, (oBusy & (iCommitGranted ^ wDependencyResolved) ), wWaitingForCommitGranted );
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UPCOUNTER_POSEDGE # ( 1 ) FFD_10
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UPCOUNTER_POSEDGE # ( 1 ) FFD_10
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( Clock, Reset, 1'b0, wSrc0_DependencyLatch | wDependencyResolved, wSrc0_DependencyResolved );
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( Clock, Reset, 1'b0, wSrc0_DependencyLatch | wDependencyResolved, wSrc0_DependencyResolved );
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UPCOUNTER_POSEDGE # ( 1 ) FFD_11
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UPCOUNTER_POSEDGE # ( 1 ) FFD_11
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( Clock, Reset, 1'b0, wSrc1_DependencyLatch | wDependencyResolved, wSrc1_DependencyResolved );
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( Clock, Reset, 1'b0, wSrc1_DependencyLatch | wDependencyResolved, wSrc1_DependencyResolved );
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP0
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP0
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( Clock, Reset, wSrc1_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc1_Fwd );
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( Clock, Reset, wSrc1_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc1_Fwd );
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP1
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD_DEP1
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( Clock, Reset, wSrc0_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc0_Fwd );
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( Clock, Reset, wSrc0_DependencyLatch, iCommitBus[`MOD_COMMIT_DATA_RNG],wSrc0_Fwd );
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//assign oBusy = wWaitingDependency;
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//assign oBusy = wWaitingDependency;
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UPCOUNTER_POSEDGE # ( 1 ) BUSY
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UPCOUNTER_POSEDGE # ( 1 ) BUSY
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( wSrc0_Dependency_Initial | wSrc1_Dependency_Initial | ((wWaitingForCommitGranted|wDependencyResolved)/*WaitingDependency*/ & iCommitGranted) ),//***
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.Enable( wSrc0_Dependency_Initial | wSrc1_Dependency_Initial | ((wWaitingForCommitGranted|wDependencyResolved)/*WaitingDependency*/ & iCommitGranted) ),//***
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.Initial( 1'b0 ),
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.Initial( 1'b0 ),
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.Q( oBusy )
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.Q( oBusy )
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);
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);
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wire wCommitRequest;
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wire wCommitRequest;
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UPCOUNTER_POSEDGE # ( 1 ) CRQ
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UPCOUNTER_POSEDGE # ( 1 ) CRQ
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( oTrigger | iCommitGranted ),
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.Enable( oTrigger | iCommitGranted ),
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.Initial( 1'b0 ),
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.Initial( 1'b0 ),
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.Q( wCommitRequest )
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.Q( wCommitRequest )
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);
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);
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assign oCommitRequest = oTrigger | (wCommitRequest & ~iCommitGranted);
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assign oCommitRequest = oTrigger | (wCommitRequest & ~iCommitGranted);
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assign oResult = iResult;
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assign oResult = iResult;
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assign oSource1 = (wWaitingDependency) ? ((wSrc1_Dependency)? (wSrc1_Fwd):wSrc1) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
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assign oSource1 = (wWaitingDependency) ? ((wSrc1_Dependency)? (wSrc1_Fwd):wSrc1) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
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assign oSource0 = (wWaitingDependency) ? ((wSrc0_Dependency)? (wSrc0_Fwd):wSrc0) : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
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assign oSource0 = (wWaitingDependency) ? ((wSrc0_Dependency)? (wSrc0_Fwd):wSrc0) : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
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UPCOUNTER_POSEDGE # ( 1 ) DEP
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UPCOUNTER_POSEDGE # ( 1 ) DEP
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( wSrc0_Dependency_Initial | wSrc1_Dependency_Initial | wDependencyResolved ),//***
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.Enable( wSrc0_Dependency_Initial | wSrc1_Dependency_Initial | wDependencyResolved ),//***
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.Initial( 1'b0 ),
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.Initial( 1'b0 ),
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.Q( wWaitingDependency )
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.Q( wWaitingDependency )
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);
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);
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UPCOUNTER_POSEDGE # ( 1 ) DEPA
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UPCOUNTER_POSEDGE # ( 1 ) DEPA
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( wSrc0_Dependency_Initial | wSrc0_DependencyResolved ),
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.Enable( wSrc0_Dependency_Initial | wSrc0_DependencyResolved ),
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.Initial( 1'b0 ),
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.Initial( 1'b0 ),
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.Q( wSrc0_Dependency )
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.Q( wSrc0_Dependency )
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);
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);
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UPCOUNTER_POSEDGE # ( 1 ) DEPB
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UPCOUNTER_POSEDGE # ( 1 ) DEPB
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( wSrc1_Dependency_Initial | wSrc1_DependencyResolved ),
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.Enable( wSrc1_Dependency_Initial | wSrc1_DependencyResolved ),
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.Initial( 1'b0 ),
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.Initial( 1'b0 ),
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.Q( wSrc1_Dependency )
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.Q( wSrc1_Dependency )
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
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( Clock, Reset, wHandleCurrentIssue , iIssueBus, {oId,oDestination,oWE,oScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
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( Clock, Reset, wHandleCurrentIssue , iIssueBus, {oId,oDestination,oWE,oScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
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assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
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assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
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assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
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assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
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endmodule
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endmodule
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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