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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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module Unit_Execution
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module Unit_Execution
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iEnable,
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input wire iEnable,
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input wire [`INSTRUCTION_ADDR_WIDTH-1:0] iInstructionMem_WriteAddress,
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input wire [`INSTRUCTION_ADDR_WIDTH-1:0] iInstructionMem_WriteAddress,
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input wire iInstructionMem_WriteEnable,
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input wire iInstructionMem_WriteEnable,
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input wire [`INSTRUCTION_WIDTH-1:0] iInstructionMem_WriteData,
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input wire [`INSTRUCTION_WIDTH-1:0] iInstructionMem_WriteData,
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//OMEM
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output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
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output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
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output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
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output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
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output wire oOMEMWriteEnable
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output wire oOMEMWriteEnable,
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//TMEM
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output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress,
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input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData,
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input wire iTMEMDataAvailable,
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output wire oTMEMDataRequest
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);
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);
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wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP0;
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wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP0;
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wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP1;
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wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP1;
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wire [`INSTRUCTION_WIDTH-1:0] wIM_2_II_Instruction0;
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wire [`INSTRUCTION_WIDTH-1:0] wIM_2_II_Instruction0;
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wire [`INSTRUCTION_WIDTH-1:0] wIM_2_II_Instruction1;
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wire [`INSTRUCTION_WIDTH-1:0] wIM_2_II_Instruction1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr0;
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wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr0;
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wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr1;
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wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data0;
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wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data0;
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wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data1;
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wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data1;
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wire [`NUMBER_OF_RSVR_STATIONS-1:0] wRS_2_II_Busy;
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wire [`NUMBER_OF_RSVR_STATIONS-1:0] wRS_2_II_Busy;
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wire [`ISSUE_PACKET_SIZE-1:0] wIssueBus,wModIssue;
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wire [`ISSUE_PACKET_SIZE-1:0] wIssueBus;
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wire [`MOD_ISSUE_PACKET_SIZE-1:0] wModIssue;
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wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitRequest;
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wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitRequest;
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wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitGrant;
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wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitGrant;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitBus;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitBus;
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wire [`MOD_COMMIT_PACKET_SIZE-1:0] wModCommitBus;
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wire [`MOD_COMMIT_PACKET_SIZE-1:0] wModCommitBus;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Adder0;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Adder0;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Adder1;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Adder1;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Div;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Div;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Mul;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Mul;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Sqrt;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Sqrt;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Logic;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Logic;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_IO;
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wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_IO;
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wire wZeroFlag;
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wire wZeroFlag;
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wire wSignFlag;
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wire wSignFlag;
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wire [`DATA_ADDRESS_WIDTH-1:0] wFrameOffset,wIndexRegister;
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wire [`DATA_ADDRESS_WIDTH-1:0] wFrameOffset,wIndexRegister;
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wire [`WIDTH-1:0] wThreadControl;
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wire [`WIDTH-1:0] wThreadControl;
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// The Register File
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// The Register File
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RegisterFile # ( `DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH ) RF
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RegisterFile # ( `DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH ) RF
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iWriteEnable( wCommitBus[`COMMIT_WE_RNG] ),
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.iWriteEnable( wCommitBus[`COMMIT_WE_RNG] ),
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.iReadAddress0( wII_2_RF_Addr0 ),
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.iReadAddress0( wII_2_RF_Addr0 ),
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.iReadAddress1( wII_2_RF_Addr1 ),
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.iReadAddress1( wII_2_RF_Addr1 ),
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.iWriteAddress( wCommitBus[`COMMIT_DST_RNG] ),
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.iWriteAddress( wCommitBus[`COMMIT_DST_RNG] ),
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.oFrameOffset( wFrameOffset ),
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.oFrameOffset( wFrameOffset ),
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.oIndexRegister( wIndexRegister ),
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.oIndexRegister( wIndexRegister ),
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.oThreadControlRegister( wThreadControl ),
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.oThreadControlRegister( wThreadControl ),
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.iData( wCommitBus[`COMMIT_DATA_RNG] ),
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.iData( wCommitBus[`COMMIT_DATA_RNG] ),
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.oData0( wRF_2_II_Data0 ),
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.oData0( wRF_2_II_Data0 ),
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.oData1( wRF_2_II_Data1 )
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.oData1( wRF_2_II_Data1 )
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);
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);
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//Code bank 0
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//Code bank 0
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RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH, `INSTRUCTION_ADDR_WIDTH) IM
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RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH, `INSTRUCTION_ADDR_WIDTH) IM
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.iWriteEnable( iInstructionMem_WriteEnable ),
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.iWriteEnable( iInstructionMem_WriteEnable ),
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.iReadAddress0( wII0_IP0 ),
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.iReadAddress0( wII0_IP0 ),
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.iReadAddress1( wII1_IP0 ),
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.iReadAddress1( wII1_IP0 ),
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.iWriteAddress( iInstructionMem_WriteAddress ),
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.iWriteAddress( iInstructionMem_WriteAddress ),
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.iDataIn( iInstructionMem_WriteData ),
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.iDataIn( iInstructionMem_WriteData ),
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.oDataOut0( wInstrThread0 ),
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.oDataOut0( wInstrThread0 ),
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.oDataOut1( wInstrThread1 )
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.oDataOut1( wInstrThread1 )
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);
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);
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//**********************************************
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//**********************************************
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parameter MaxThreads = 3;
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parameter MaxThreads = 3;
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wire [MaxThreads-1:0] wDelay;
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wire [MaxThreads-1:0] wDelay;
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UPCOUNTER_POSEDGE # (MaxThreads) UP111
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UPCOUNTER_POSEDGE # (MaxThreads) UP111
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(
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(
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.Clock( Clock), .Reset( Reset),
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.Clock( Clock), .Reset( Reset),
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.Initial(0),
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.Initial(0),
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.Enable(1'b1),
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.Enable(1'b1),
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.Q(wDelay)
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.Q(wDelay)
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);
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);
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wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII0_IP0,wII0_IP1;
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wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII0_IP0,wII0_IP1;
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wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII1_IP0,wII1_IP1;
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wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII1_IP0,wII1_IP1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wII0_RF_Addr0,wII0_RF_Addr1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wII0_RF_Addr0,wII0_RF_Addr1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wII1_RF_Addr0,wII1_RF_Addr1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wII1_RF_Addr0,wII1_RF_Addr1;
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wire [`ISSUE_PACKET_SIZE-1:0] wII0_IBus,wII1_IBus;
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wire [`ISSUE_PACKET_SIZE-1:0] wII0_IBus,wII1_IBus;
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assign wII_2_RF_Addr0 = (wCurrentActiveThread[0]) ? wII0_RF_Addr0 : wII1_RF_Addr0;
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assign wII_2_RF_Addr0 = (wCurrentActiveThread[0]) ? wII0_RF_Addr0 : wII1_RF_Addr0;
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assign wII_2_RF_Addr1 = (wCurrentActiveThread[0]) ? wII0_RF_Addr1 : wII1_RF_Addr1;
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assign wII_2_RF_Addr1 = (wCurrentActiveThread[0]) ? wII0_RF_Addr1 : wII1_RF_Addr1;
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assign wIssueBus = (wCurrentActiveThread[0]) ? wII0_IBus: wII1_IBus;
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assign wIssueBus = (wCurrentActiveThread[0]) ? wII0_IBus: wII1_IBus;
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wire [`MAX_THREADS-1:0] wCurrentActiveThread,wCurrentActiveThread_Pre,wCurrentActiveThread_Pre2;
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wire [`MAX_THREADS-1:0] wCurrentActiveThread,wCurrentActiveThread_Pre,wCurrentActiveThread_Pre2;
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CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( `MAX_THREADS ) THREAD_SELECT
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CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( `MAX_THREADS ) THREAD_SELECT
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Initial(`MAX_THREADS'b1),
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.Initial(`MAX_THREADS'b1),
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.Enable( wDelay[0] /*& wDelay[1]*/ & wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
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.Enable( wDelay[0] /*& wDelay[1]*/ & wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
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.O( wCurrentActiveThread_Pre )
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.O( wCurrentActiveThread_Pre )
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_THREADS ) FFD12
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_THREADS ) FFD12
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( Clock, Reset, 1'b1 , wCurrentActiveThread_Pre , wCurrentActiveThread_Pre2 );
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( Clock, Reset, 1'b1 , wCurrentActiveThread_Pre , wCurrentActiveThread_Pre2 );
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assign wCurrentActiveThread = (wThreadControl[`SPR_TCONTROL0_MT_ENABLED]) ? wCurrentActiveThread_Pre2 : `MAX_THREADS'b1;
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assign wCurrentActiveThread = (wThreadControl[`SPR_TCONTROL0_MT_ENABLED]) ? wCurrentActiveThread_Pre2 : `MAX_THREADS'b1;
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//**********************************************
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//**********************************************
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wire [`INSTRUCTION_WIDTH-1:0] wInstrThread0;
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wire [`INSTRUCTION_WIDTH-1:0] wInstrThread0;
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//When the thread is inactive I want to keep this input just the way it was,
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//When the thread is inactive I want to keep this input just the way it was,
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//sort of "time freezing"...
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//sort of "time freezing"...
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InstructionIssue II0
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InstructionIssue II0
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iEnable( wCurrentActiveThread[0] & iEnable),
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.iEnable( wCurrentActiveThread[0] & iEnable),
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.iFrameOffset( wFrameOffset ),
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.iFrameOffset( wFrameOffset ),
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/* New Apr 06*/.iCodeOffset( `INSTRUCTION_ADDR_WIDTH'b0 ),
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/* New Apr 06*/.iCodeOffset( `INSTRUCTION_ADDR_WIDTH'b0 ),
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.iMtEnabled(wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
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.iMtEnabled(wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
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.iIndexRegister( wIndexRegister ),
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.iIndexRegister( wIndexRegister ),
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.iInstruction0( wInstrThread0 ),
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.iInstruction0( wInstrThread0 ),
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// .iInstruction1( wIM_2_II_Instruction1 ),
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// .iInstruction1( wIM_2_II_Instruction1 ),
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.iSourceData0( wRF_2_II_Data0 ),
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.iSourceData0( wRF_2_II_Data0 ),
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.iSourceData1( wRF_2_II_Data1 ),
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.iSourceData1( wRF_2_II_Data1 ),
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.iRStationBusy( wRS_2_II_Busy ),
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.iRStationBusy( wRS_2_II_Busy ),
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.iResultBcast( wCommitBus ),
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.iResultBcast( wCommitBus ),
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.iSignFlag( wSignFlag ),
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.iSignFlag( wSignFlag ),
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.iZeroFlag( wZeroFlag ),
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.iZeroFlag( wZeroFlag ),
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.iIgnoreResultBcast( wResultBCastDst[7] & wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
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.iIgnoreResultBcast( wResultBCastDst[7] & wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
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.oSourceAddress0( wII0_RF_Addr0 ),//wII_2_RF_Addr0 ),
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.oSourceAddress0( wII0_RF_Addr0 ),//wII_2_RF_Addr0 ),
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.oSourceAddress1( wII0_RF_Addr1 ),//wII_2_RF_Addr1 ),
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.oSourceAddress1( wII0_RF_Addr1 ),//wII_2_RF_Addr1 ),
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.oIssueBcast( wII0_IBus ),//wIssueBus ),
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.oIssueBcast( wII0_IBus ),//wIssueBus ),
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.oIP0( wII0_IP0 )//wII_2_IM_IP0 ),
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.oIP0( wII0_IP0 )//wII_2_IM_IP0 ),
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//.oIP1( wII0_IP1 )//wII_2_IM_IP1 )
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//.oIP1( wII0_IP1 )//wII_2_IM_IP1 )
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);
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);
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wire [`INSTRUCTION_WIDTH-1:0] wInstrThread1;
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wire [`INSTRUCTION_WIDTH-1:0] wInstrThread1;
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//When the thread is inactive I want to keep this input just the way it was,
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//When the thread is inactive I want to keep this input just the way it was,
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//sort of "time freezing"...
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//sort of "time freezing"...
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//Add the offset to the thread instructions... 1 16 bit adder wasted :(
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//Add the offset to the thread instructions... 1 16 bit adder wasted :(
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//assign wInstrThread1 = wInstrThread1_Pre;
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//assign wInstrThread1 = wInstrThread1_Pre;
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wire [`DATA_ADDRESS_WIDTH-1:0] wResultBCastDst;
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wire [`DATA_ADDRESS_WIDTH-1:0] wResultBCastDst;
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assign wResultBCastDst = wCommitBus[`COMMIT_DST_RNG];
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assign wResultBCastDst = wCommitBus[`COMMIT_DST_RNG];
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InstructionIssue II1
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InstructionIssue II1
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset || ~wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
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.Reset( Reset || ~wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
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.iEnable( wCurrentActiveThread[1] & iEnable ),
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.iEnable( wCurrentActiveThread[1] & iEnable ),
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.iFrameOffset( wFrameOffset ),
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.iFrameOffset( wFrameOffset ),
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.iCodeOffset( wThreadControl[`SPR_TCONTROL0_T0_INST_OFFSET_RNG] ),
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.iCodeOffset( wThreadControl[`SPR_TCONTROL0_T0_INST_OFFSET_RNG] ),
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.iMtEnabled( wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
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.iMtEnabled( wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
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.iIndexRegister( wIndexRegister ),
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.iIndexRegister( wIndexRegister ),
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.iInstruction0( wInstrThread1 ),
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.iInstruction0( wInstrThread1 ),
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.iSourceData0( wRF_2_II_Data0 ),
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.iSourceData0( wRF_2_II_Data0 ),
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.iSourceData1( wRF_2_II_Data1 ),
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.iSourceData1( wRF_2_II_Data1 ),
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.iRStationBusy( wRS_2_II_Busy ),
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.iRStationBusy( wRS_2_II_Busy ),
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.iResultBcast( wCommitBus ),
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.iResultBcast( wCommitBus ),
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.iSignFlag( wSignFlag ),
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.iSignFlag( wSignFlag ),
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.iZeroFlag( wZeroFlag ),
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.iZeroFlag( wZeroFlag ),
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|
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.iIgnoreResultBcast( ~wResultBCastDst[7] ),
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.iIgnoreResultBcast( ~wResultBCastDst[7] ),
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.oSourceAddress0( wII1_RF_Addr0 ),
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.oSourceAddress0( wII1_RF_Addr0 ),
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.oSourceAddress1( wII1_RF_Addr1 ),
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.oSourceAddress1( wII1_RF_Addr1 ),
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.oIssueBcast( wII1_IBus ),
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.oIssueBcast( wII1_IBus ),
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.oIP0( wII1_IP0 )
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.oIP0( wII1_IP0 )
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//.oIP1( wII1_IP1 )
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//.oIP1( wII1_IP1 )
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|
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);
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);
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OperandModifiers SMU
|
OperandModifiers SMU
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iIssueBus( wIssueBus ),
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.iIssueBus( wIssueBus ),
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.iCommitBus( wCommitBus ),
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.iCommitBus( wCommitBus ),
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.oModIssue( wModIssue ),
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.oModIssue( wModIssue ),
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.oCommitBus( wModCommitBus )
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.oCommitBus( wModCommitBus )
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|
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);
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);
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assign wSignFlag = wCommitBus[`COMMIT_SIGN_X] & wCommitBus[`COMMIT_SIGN_Y] & wCommitBus[`COMMIT_SIGN_Z];
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assign wSignFlag = wCommitBus[`COMMIT_SIGN_X] & wCommitBus[`COMMIT_SIGN_Y] & wCommitBus[`COMMIT_SIGN_Z];
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assign wZeroFlag = (wCommitBus[`COMMIT_DATA_RNG] == `DATA_ROW_WIDTH'b0) ? 1'b1 : 1'b0;
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assign wZeroFlag = (wCommitBus[`COMMIT_DATA_RNG] == `DATA_ROW_WIDTH'b0) ? 1'b1 : 1'b0;
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|
|
|
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ADDER_STATION ADD_STA0
|
ADDER_STATION ADD_STA0
|
(
|
(
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.Clock( Clock ),
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.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.iId( `RS_ADD0 ),
|
.iId( `RS_ADD0 ),
|
.iIssueBus( wModIssue ),
|
.iIssueBus( wModIssue ),
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.iCommitBus( wModCommitBus ),
|
.iCommitBus( wModCommitBus ),
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.oCommitData( wCommitData_Adder0 ),
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.oCommitData( wCommitData_Adder0 ),
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.oCommitResquest( wStationCommitRequest[0] ),
|
.oCommitResquest( wStationCommitRequest[0] ),
|
.iCommitGranted( wStationCommitGrant[0] ),
|
.iCommitGranted( wStationCommitGrant[0] ),
|
.oBusy( wRS_2_II_Busy[ 0 ] )
|
.oBusy( wRS_2_II_Busy[ 0 ] )
|
|
|
);
|
);
|
|
|
ADDER_STATION ADD_STA1
|
ADDER_STATION ADD_STA1
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.iId( `RS_ADD1 ),
|
.iId( `RS_ADD1 ),
|
.iIssueBus( wModIssue ),
|
.iIssueBus( wModIssue ),
|
.iCommitBus( wModCommitBus ),
|
.iCommitBus( wModCommitBus ),
|
.oCommitData( wCommitData_Adder1 ),
|
.oCommitData( wCommitData_Adder1 ),
|
.oCommitResquest( wStationCommitRequest[1] ),
|
.oCommitResquest( wStationCommitRequest[1] ),
|
.iCommitGranted( wStationCommitGrant[1] ),
|
.iCommitGranted( wStationCommitGrant[1] ),
|
.oBusy( wRS_2_II_Busy[ 1 ] )
|
.oBusy( wRS_2_II_Busy[ 1 ] )
|
|
|
);
|
);
|
|
|
|
|
DIVISION_STATION DIV_STA
|
DIVISION_STATION DIV_STA
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.iId( `RS_DIV ),
|
.iId( `RS_DIV ),
|
.iIssueBus( wModIssue ),
|
.iIssueBus( wModIssue ),
|
.iCommitBus( wModCommitBus ),
|
.iCommitBus( wModCommitBus ),
|
.oCommitData( wCommitData_Div ),
|
.oCommitData( wCommitData_Div ),
|
.oCommitResquest( wStationCommitRequest[2] ),
|
.oCommitResquest( wStationCommitRequest[2] ),
|
.iCommitGranted( wStationCommitGrant[2] ),
|
.iCommitGranted( wStationCommitGrant[2] ),
|
.oBusy( wRS_2_II_Busy[2] )
|
.oBusy( wRS_2_II_Busy[2] )
|
|
|
);
|
);
|
|
|
|
|
MUL_STATION MUL_STA
|
MUL_STATION MUL_STA
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.iId( `RS_MUL ),
|
.iId( `RS_MUL ),
|
.iIssueBus( wModIssue ),
|
.iIssueBus( wModIssue ),
|
.iCommitBus( wModCommitBus ),
|
.iCommitBus( wModCommitBus ),
|
.oCommitData( wCommitData_Mul ),
|
.oCommitData( wCommitData_Mul ),
|
.oCommitResquest( wStationCommitRequest[3] ),
|
.oCommitResquest( wStationCommitRequest[3] ),
|
.iCommitGranted( wStationCommitGrant[3] ),
|
.iCommitGranted( wStationCommitGrant[3] ),
|
.oBusy( wRS_2_II_Busy[3] )
|
.oBusy( wRS_2_II_Busy[3] )
|
|
|
);
|
);
|
|
|
|
|
SQRT_STATION SQRT_STA
|
SQRT_STATION SQRT_STA
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.iId( `RS_SQRT ),
|
.iId( `RS_SQRT ),
|
.iIssueBus( wModIssue ),
|
.iIssueBus( wModIssue ),
|
.iCommitBus( wModCommitBus ),
|
.iCommitBus( wModCommitBus ),
|
.oCommitData( wCommitData_Sqrt ),
|
.oCommitData( wCommitData_Sqrt ),
|
.oCommitResquest( wStationCommitRequest[4] ),
|
.oCommitResquest( wStationCommitRequest[4] ),
|
.iCommitGranted( wStationCommitGrant[4] ),
|
.iCommitGranted( wStationCommitGrant[4] ),
|
.oBusy( wRS_2_II_Busy[4] )
|
.oBusy( wRS_2_II_Busy[4] )
|
|
|
);
|
);
|
|
|
|
|
|
|
LOGIC_STATION LOGIC_STA
|
LOGIC_STATION LOGIC_STA
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.iId( `RS_LOGIC ),
|
.iId( `RS_LOGIC ),
|
.iIssueBus( wModIssue ),
|
.iIssueBus( wModIssue ),
|
.iCommitBus( wModCommitBus ),
|
.iCommitBus( wModCommitBus ),
|
.oCommitData( wCommitData_Logic ),
|
.oCommitData( wCommitData_Logic ),
|
.oCommitResquest( wStationCommitRequest[5] ),
|
.oCommitResquest( wStationCommitRequest[5] ),
|
.iCommitGranted( wStationCommitGrant[5] ),
|
.iCommitGranted( wStationCommitGrant[5] ),
|
.oBusy( wRS_2_II_Busy[5] )
|
.oBusy( wRS_2_II_Busy[5] )
|
|
|
);
|
);
|
|
|
IO_STATION IO_STA
|
IO_STATION IO_STA
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.iId( `RS_IO ),
|
.iId( `RS_IO ),
|
.iIssueBus( wModIssue ),
|
.iIssueBus( wModIssue ),
|
.iCommitBus( wModCommitBus ),
|
.iCommitBus( wModCommitBus ),
|
.oCommitData( wCommitData_IO ),
|
.oCommitData( wCommitData_IO ),
|
.oCommitResquest( wStationCommitRequest[6] ),
|
.oCommitResquest( wStationCommitRequest[6] ),
|
.iCommitGranted( wStationCommitGrant[6] ),
|
.iCommitGranted( wStationCommitGrant[6] ),
|
.oBusy( wRS_2_II_Busy[6] ),
|
.oBusy( wRS_2_II_Busy[6] ),
|
|
//OMEM
|
.oOMEMWriteAddress( oOMEMWriteAddress ),
|
.oOMEMWriteAddress( oOMEMWriteAddress ),
|
.oOMEMWriteData( oOMEMWriteData ),
|
.oOMEMWriteData( oOMEMWriteData ),
|
.oOMEMWriteEnable( oOMEMWriteEnable )
|
.oOMEMWriteEnable( oOMEMWriteEnable ),
|
|
//TMEM
|
|
.oTMEMReadAddress( oTMEMReadAddress ),
|
|
.iTMEMReadData( iTMEMReadData ),
|
|
.iTMEMDataAvailable( iTMEMDataAvailable ),
|
|
.oTMEMDataRequest( oTMEMDataRequest )
|
|
|
);
|
);
|
|
|
ROUND_ROBIN_7_ENTRIES ARB
|
ROUND_ROBIN_7_ENTRIES ARB
|
//ROUND_ROBIN_6_ENTRIES ARB
|
//ROUND_ROBIN_6_ENTRIES ARB
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.iRequest0( wStationCommitRequest[0] ),
|
.iRequest0( wStationCommitRequest[0] ),
|
.iRequest1( wStationCommitRequest[1] ),
|
.iRequest1( wStationCommitRequest[1] ),
|
.iRequest2( wStationCommitRequest[2] ),
|
.iRequest2( wStationCommitRequest[2] ),
|
.iRequest3( wStationCommitRequest[3] ),
|
.iRequest3( wStationCommitRequest[3] ),
|
.iRequest4( wStationCommitRequest[4] ),
|
.iRequest4( wStationCommitRequest[4] ),
|
.iRequest5( wStationCommitRequest[5] ),
|
.iRequest5( wStationCommitRequest[5] ),
|
.iRequest6( wStationCommitRequest[6] ),
|
.iRequest6( wStationCommitRequest[6] ),
|
.oGrant0( wStationCommitGrant[0] ),
|
.oGrant0( wStationCommitGrant[0] ),
|
.oGrant1( wStationCommitGrant[1] ),
|
.oGrant1( wStationCommitGrant[1] ),
|
.oGrant2( wStationCommitGrant[2] ),
|
.oGrant2( wStationCommitGrant[2] ),
|
.oGrant3( wStationCommitGrant[3] ),
|
.oGrant3( wStationCommitGrant[3] ),
|
.oGrant4( wStationCommitGrant[4] ),
|
.oGrant4( wStationCommitGrant[4] ),
|
.oGrant5( wStationCommitGrant[5] ),
|
.oGrant5( wStationCommitGrant[5] ),
|
.oGrant6( wStationCommitGrant[6] )
|
.oGrant6( wStationCommitGrant[6] )
|
|
|
);
|
);
|
|
|
|
wire [5:0] wBusSelector_Tmp;
|
wire[3:0] wBusSelector;
|
wire[2:0] wBusSelector;
|
DECODER_ONEHOT_2_BINARY DECODER
|
DECODER_ONEHOT_2_BINARY DECODER
|
(
|
(
|
.iIn( wStationCommitGrant ),
|
.iIn( wStationCommitGrant ),
|
.oOut( wBusSelector )
|
.oOut( wBusSelector_Tmp )
|
);
|
);
|
|
assign wBusSelector = wBusSelector_Tmp[3:0];
|
|
|
|
MUXFULLPARALELL_3SEL_GENERIC # (`COMMIT_PACKET_SIZE ) MUX //TODO I need one more entry for the IO
|
MUXFULLPARALELL_3SEL_GENERIC # (`COMMIT_PACKET_SIZE ) MUX
|
|
(
|
(
|
.Sel(wBusSelector),
|
.Sel(wBusSelector),
|
.I1(`COMMIT_PACKET_SIZE'b0),
|
.I1(`COMMIT_PACKET_SIZE'b0),
|
.I2(wCommitData_Adder0),
|
.I2(wCommitData_Adder0),
|
.I3(wCommitData_Adder1),
|
.I3(wCommitData_Adder1),
|
.I4(wCommitData_Div),
|
.I4(wCommitData_Div),
|
.I5(wCommitData_Mul),
|
.I5(wCommitData_Mul),
|
.I6(wCommitData_Sqrt),
|
.I6(wCommitData_Sqrt),
|
.I7(wCommitData_Logic),
|
.I7(wCommitData_Logic),
|
|
.I8(wCommitData_IO ),
|
.O1(wCommitBus)
|
.O1(wCommitBus)
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
