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/*
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* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`define P 20 // clock period
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`define P 20 // clock period
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module test_tiny;
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module test_tiny;
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// Inputs
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// Inputs
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reg clk;
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reg clk;
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reg reset;
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reg reset;
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reg sel;
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reg sel;
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reg [5:0] addr;
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reg [5:0] addr;
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reg w;
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reg w;
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reg [197:0] data;
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reg [197:0] data;
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// Outputs
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// Outputs
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wire [197:0] out;
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wire [197:0] out;
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wire done;
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wire done;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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tiny uut (
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tiny uut (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.sel(sel),
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.sel(sel),
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.addr(addr),
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.addr(addr),
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.w(w),
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.w(w),
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.data(data),
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.data(data),
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.out(out),
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.out(out),
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.done(done)
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.done(done)
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);
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);
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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clk = 0;
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clk = 0;
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reset = 0;
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reset = 0;
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sel = 0;
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sel = 0;
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addr = 0;
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addr = 0;
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w = 0;
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w = 0;
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data = 0;
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data = 0;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#100;
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#100;
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// Add stimulus here
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// Add stimulus here
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reset = 1; // keep FSM silent
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reset = 1; // keep FSM silent
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// init x, y
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// init x, y
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write(3, 194'h21181940120548aa020568aa65a5989609251595a89a44598);
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write(3, 194'h21181940120548aa020568aa65a5989609251595a89a44598);
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write(5, 194'h0a905590506a8a845592a09644a2095291422910a968a5048);
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write(5, 194'h0a905590506a8a845592a09644a2095291422910a968a5048);
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write(6, 194'h21181940120548aa020568aa65a5989609251595a89a44598);
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write(6, 194'h21181940120548aa020568aa65a5989609251595a89a44598);
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write(7, 194'h0a905590506a8a845592a09644a2095291422910a968a5048);
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write(7, 194'h0a905590506a8a845592a09644a2095291422910a968a5048);
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/* read back. uncomment me if error happens */
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/* read back. uncomment me if error happens */
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/* read(3);
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/* read(3);
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$display("xp = %h", out);
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$display("xp = %h", out);
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read(5);
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read(5);
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$display("yp = %h", out);
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$display("yp = %h", out);
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read(6);
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read(6);
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$display("xq = %h", out);
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$display("xq = %h", out);
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read(7);
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read(7);
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$display("yq = %h", out);*/
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$display("yq = %h", out);*/
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reset = 0;
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reset = 0;
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sel = 0; w = 0;
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sel = 0; w = 0;
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@(posedge done);
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@(posedge done);
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@(negedge clk);
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@(negedge clk);
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read(3);
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read(3);
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check(194'h21181940120548aa020568aa65a5989609251595a89a44599);
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check(194'h21181940120548aa020568aa65a5989609251595a89a44599);
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read(5);
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read(5);
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check(194'h0560aa60a0954548aa615069885106a16281162056945a084);
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check(194'h0560aa60a0954548aa615069885106a16281162056945a084);
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read(6);
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read(6);
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check(194'h21181940120548aa020568aa65a5989609251595a89a44598);
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check(194'h21181940120548aa020568aa65a5989609251595a89a44598);
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read(7);
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read(7);
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check(194'h0a905590506a8a845592a09644a2095291422910a968a5048);
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check(194'h0a905590506a8a845592a09644a2095291422910a968a5048);
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read(9);
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read(9);
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check(194'h09a49266428495042842965645266a2164a1268408a669866);
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check(194'h09a49266428495042842965645266a2164a1268408a669866);
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read(10);
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read(10);
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check(194'h204446152452400968480544296829199a169a2562a908520);
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check(194'h204446152452400968480544296829199a169a2562a908520);
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read(11);
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read(11);
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check(194'h1699142918666651a156954a80544689590a5094624610281);
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check(194'h1699142918666651a156954a80544689590a5094624610281);
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read(12);
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read(12);
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check(194'h2461998924145511611291626a4a295888569280285884661);
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check(194'h2461998924145511611291626a4a295888569280285884661);
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read(13);
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read(13);
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check(194'h1040525045a404150a1881aa91a99156660a1658a090a1091);
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check(194'h1040525045a404150a1881aa91a99156660a1658a090a1091);
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read(14);
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read(14);
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check(194'h2400a94249694808254880924a06494816081900811198925);
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check(194'h2400a94249694808254880924a06494816081900811198925);
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$display("Good");
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$display("Good");
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$finish;
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$finish;
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end
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end
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initial #100 forever #(`P/2) clk = ~clk;
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initial #100 forever #(`P/2) clk = ~clk;
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task write;
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task write;
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input [6:0] adr;
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input [6:0] adr;
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input [197:0] dat;
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input [197:0] dat;
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begin
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begin
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sel = 1;
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sel = 1;
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w = 1;
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w = 1;
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addr = adr;
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addr = adr;
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data = dat;
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data = dat;
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#(`P);
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#(`P);
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end
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end
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endtask
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endtask
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task read;
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task read;
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input [6:0] adr;
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input [6:0] adr;
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begin
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begin
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sel = 1;
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sel = 1;
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w = 0;
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w = 0;
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addr = adr;
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addr = adr;
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#(`P);
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#(`P);
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end
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end
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endtask
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endtask
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task check;
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task check;
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input [197:0] wish;
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input [197:0] wish;
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begin
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begin
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if (out !== wish)
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if (out !== wish)
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begin $display("Error!"); $finish; end
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begin $display("Error!"); $finish; end
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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