/*!
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/*!
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mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15b
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mmio -- Memory mapped I/O example for ZTEX USB-FPGA Module 1.15a
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Copyright (C) 2009-2011 ZTEX GmbH.
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Copyright (C) 2009-2014 ZTEX GmbH.
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http://www.ztex.de
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http://www.ztex.de
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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!*/
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#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros
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#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros
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#include[ztex-utils.h] // include basic functions
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#include[ztex-utils.h] // include basic functions
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// configure endpoints 2 and 4, both belong to interface 0 (in/out are from the point of view of the host)
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// configure endpoints 2 and 4, both belong to interface 0 (in/out are from the point of view of the host)
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EP_CONFIG(2,0,BULK,IN,512,2);
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EP_CONFIG(2,0,BULK,IN,512,2);
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EP_CONFIG(4,0,BULK,OUT,512,2);
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EP_CONFIG(4,0,BULK,OUT,512,2);
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// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration)
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// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration)
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IDENTITY_UFM_1_15(10.13.0.0,0);
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IDENTITY_UFM_1_15(10.13.0.0,0);
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// enables high speed FPGA configuration, (re)use EP 4
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// enables high speed FPGA configuration, (re)use EP 4
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ENABLE_HS_FPGA_CONF(4);
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ENABLE_HS_FPGA_CONF(4);
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// this product string is also used for identification by the host software
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// this product string is also used for identification by the host software
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#define[PRODUCT_STRING]["memeory mapping example for UFM 1.15"]
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#define[PRODUCT_STRING]["memeory mapping example for UFM 1.15"]
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__xdata BYTE run;
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__xdata BYTE run;
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#define[PRE_FPGA_RESET][PRE_FPGA_RESET
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#define[PRE_FPGA_RESET][PRE_FPGA_RESET
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run = 0;
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run = 0;
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]
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]
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#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG
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#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG
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IFCONFIG = bmBIT7; // internel 30MHz clock, drive IFCLK ouput, slave FIFO interface
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IFCONFIG = bmBIT7; // internel 30MHz clock, drive IFCLK ouput, slave FIFO interface
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SYNCDELAY;
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SYNCDELAY;
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EP2FIFOCFG = 0;
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EP2FIFOCFG = 0;
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SYNCDELAY;
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SYNCDELAY;
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EP4FIFOCFG = 0;
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EP4FIFOCFG = 0;
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SYNCDELAY;
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SYNCDELAY;
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REVCTL = 0x0; // reset
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REVCTL = 0x0; // reset
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SYNCDELAY;
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SYNCDELAY;
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EP2CS &= ~bmBIT0; // stall = 0
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EP2CS &= ~bmBIT0; // stall = 0
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SYNCDELAY;
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SYNCDELAY;
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EP4CS &= ~bmBIT0; // stall = 0
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EP4CS &= ~bmBIT0; // stall = 0
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SYNCDELAY; // first two packages are waste
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SYNCDELAY; // first two packages are waste
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EP4BCL = 0x80; // skip package, (re)arm EP4
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EP4BCL = 0x80; // skip package, (re)arm EP4
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SYNCDELAY;
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SYNCDELAY;
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EP4BCL = 0x80; // skip package, (re)arm EP4
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EP4BCL = 0x80; // skip package, (re)arm EP4
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FIFORESET = 0x80; // reset FIFO
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FIFORESET = 0x80; // reset FIFO
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = 0x82;
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FIFORESET = 0x82;
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = 0x00;
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FIFORESET = 0x00;
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SYNCDELAY;
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SYNCDELAY;
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run = 1;
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run = 1;
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]
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]
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// include the main part of the firmware kit, define the descriptors, ...
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// include the main part of the firmware kit, define the descriptors, ...
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#include[ztex.h]
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#include[ztex.h]
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__xdata __at 0x5001 volatile BYTE OUT_REG; // FPGA register where the data is written to
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__xdata __at 0x5001 volatile BYTE OUT_REG; // FPGA register where the data is written to
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__xdata __at 0x5002 volatile BYTE IN_REG; // FPGA register where the result is read from
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__xdata __at 0x5002 volatile BYTE IN_REG; // FPGA register where the result is read from
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void main(void)
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void main(void)
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{
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{
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WORD i,size;
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WORD i,size;
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// init everything
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// init everything
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init_USB();
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init_USB();
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while (1) {
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while (1) {
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if ( run & !(EP4CS & bmBIT2) ) { // EP4 is not empty
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if ( run & !(EP4CS & bmBIT2) ) { // EP4 is not empty
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size = (EP4BCH << 8) | EP4BCL;
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size = (EP4BCH << 8) | EP4BCL;
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if ( size>0 && size<=512 && !(EP2CS & bmBIT3)) { // EP2 is not full
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if ( size>0 && size<=512 && !(EP2CS & bmBIT3)) { // EP2 is not full
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for ( i=0; i<size; i++ ) {
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for ( i=0; i<size; i++ ) {
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OUT_REG = EP4FIFOBUF[i]; // data from EP4 is converted to uppercase by the FPGA ...
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OUT_REG = EP4FIFOBUF[i]; // data from EP4 is converted to uppercase by the FPGA ...
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EP2FIFOBUF[i] = IN_REG; // ... and written back to EP2 buffer
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EP2FIFOBUF[i] = IN_REG; // ... and written back to EP2 buffer
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}
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}
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EP2BCH = size >> 8;
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EP2BCH = size >> 8;
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SYNCDELAY;
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SYNCDELAY;
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EP2BCL = size & 255; // arm EP2
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EP2BCL = size & 255; // arm EP2
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SYNCDELAY;
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SYNCDELAY;
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INPKTEND = 0x2;
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INPKTEND = 0x2;
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}
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}
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SYNCDELAY;
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SYNCDELAY;
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EP4BCL = 0x80; // (re)arm EP4
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EP4BCL = 0x80; // (re)arm EP4
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}
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}
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}
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}
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}
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}
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