`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 13:33:36 01/02/2014
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// Create Date: 13:33:36 01/02/2014
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// Design Name:
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// Design Name:
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// Module Name: qmults
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// Module Name: qmults
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module qmults#(
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module qmults#(
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//Parameterized values
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//Parameterized values
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parameter Q = 15,
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parameter Q = 15,
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parameter N = 32
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parameter N = 32
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)
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)
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(
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(
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input [N-1:0] i_multiplicand,
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input [N-1:0] i_multiplicand,
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input [N-1:0] i_multiplier,
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input [N-1:0] i_multiplier,
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input i_start,
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input i_start,
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input i_clk,
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input i_clk,
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output [N-1:0] o_result_out,
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output [N-1:0] o_result_out,
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output o_complete,
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output o_complete,
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output o_overflow
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output o_overflow
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);
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);
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reg [2*N-2:0] reg_working_result; // a place to accumulate our result
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reg [2*N-2:0] reg_working_result; // a place to accumulate our result
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reg [2*N-2:0] reg_multiplier_temp; // a working copy of the multiplier
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reg [2*N-2:0] reg_multiplier_temp; // a working copy of the multiplier
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reg [N-1:0] reg_multiplicand_temp; // a working copy of the umultiplicand
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reg [N-1:0] reg_multiplicand_temp; // a working copy of the umultiplicand
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reg [N:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
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reg [N-1:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
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// count to N, but computing that number of bits requires a
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// count to N, but computing that number of bits requires a
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// logarithm (base 2), and I don't know how to do that in a
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// logarithm (base 2), and I don't know how to do that in a
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// way that will work for every possibility
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// way that will work for every possibility
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reg reg_done; // Computation completed flag
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reg reg_done; // Computation completed flag
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reg reg_sign; // The result's sign bit
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reg reg_sign; // The result's sign bit
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reg reg_overflow; // Overflow flag
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reg reg_overflow; // Overflow flag
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initial reg_done = 1'b1; // Initial state is to not be doing anything
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initial reg_done = 1'b1; // Initial state is to not be doing anything
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initial reg_overflow = 1'b0; // And there should be no woverflow present
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initial reg_overflow = 1'b0; // And there should be no woverflow present
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initial reg_sign = 1'b0; // And the sign should be positive
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initial reg_sign = 1'b0; // And the sign should be positive
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assign o_result_out[N-2:0] = reg_working_result[N-2+Q:Q]; // The multiplication results
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assign o_result_out[N-2:0] = reg_working_result[N-2+Q:Q]; // The multiplication results
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assign o_result_out[N-1] = reg_sign; // The sign of the result
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assign o_result_out[N-1] = reg_sign; // The sign of the result
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assign o_complete = reg_done; // "Done" flag
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assign o_complete = reg_done; // "Done" flag
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assign o_overflow = reg_overflow; // Overflow flag
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assign o_overflow = reg_overflow; // Overflow flag
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always @( posedge i_clk ) begin
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always @( posedge i_clk ) begin
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if( reg_done && i_start ) begin // This is our startup condition
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if( reg_done && i_start ) begin // This is our startup condition
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reg_done <= 1'b0; // We're not done
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reg_done <= 1'b0; // We're not done
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reg_count <= 0; // Reset the count
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reg_count <= 0; // Reset the count
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reg_working_result <= 0; // Clear out the result register
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reg_working_result <= 0; // Clear out the result register
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reg_multiplier_temp <= 0; // Clear out the multiplier register
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reg_multiplier_temp <= 0; // Clear out the multiplier register
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reg_multiplicand_temp <= 0; // Clear out the multiplicand register
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reg_multiplicand_temp <= 0; // Clear out the multiplicand register
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reg_overflow <= 1'b0; // Clear the overflow register
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reg_overflow <= 1'b0; // Clear the overflow register
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reg_multiplicand_temp <= i_multiplicand[N-2:0]; // Load the multiplicand in its working register and lose the sign bit
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reg_multiplicand_temp <= i_multiplicand[N-2:0]; // Load the multiplicand in its working register and lose the sign bit
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reg_multiplier_temp <= i_multiplier[N-2:0]; // Load the multiplier into its working register and lose the sign bit
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reg_multiplier_temp <= i_multiplier[N-2:0]; // Load the multiplier into its working register and lose the sign bit
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reg_sign <= i_multiplicand[N-1] ^ i_multiplier[N-1]; // Set the sign bit
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reg_sign <= i_multiplicand[N-1] ^ i_multiplier[N-1]; // Set the sign bit
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end
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end
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else if (!reg_done) begin
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else if (!reg_done) begin
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if (reg_multiplicand_temp[reg_count] == 1'b1) // if the appropriate multiplicand bit is 1
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if (reg_multiplicand_temp[reg_count] == 1'b1) // if the appropriate multiplicand bit is 1
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reg_working_result <= reg_working_result + reg_multiplier_temp; // then add the temp multiplier
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reg_working_result <= reg_working_result + reg_multiplier_temp; // then add the temp multiplier
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reg_multiplier_temp <= reg_multiplier_temp << 1; // Do a left-shift on the multiplier
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reg_multiplier_temp <= reg_multiplier_temp << 1; // Do a left-shift on the multiplier
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reg_count <= reg_count + 1; // Increment the count
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reg_count <= reg_count + 1; // Increment the count
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//stop condition
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//stop condition
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if(reg_count == N) begin
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if(reg_count == N) begin
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reg_done <= 1'b1; // If we're done, it's time to tell the calling process
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reg_done <= 1'b1; // If we're done, it's time to tell the calling process
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if (reg_working_result[2*N-2:N-1+Q] > 0) // Check for an overflow
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if (reg_working_result[2*N-2:N-1+Q] > 0) // Check for an overflow
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reg_overflow <= 1'b1;
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reg_overflow <= 1'b1;
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// else
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// else
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// reg_count <= reg_count + 1; // Increment the count
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// reg_count <= reg_count + 1; // Increment the count
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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