--!
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--!
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--! Copyright (C) 2011 - 2012 Creonic GmbH
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--! Copyright (C) 2011 - 2014 Creonic GmbH
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--!
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--! under the terms of the GNU General Public License version 2.
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--!
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--!
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--! @file
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--! @file
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--! @brief Viterbi decoder top entity, connecting all decoder units.
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--! @brief Viterbi decoder top entity, connecting all decoder units.
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--! @author Markus Fehrenz
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--! @author Markus Fehrenz
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--! @date 2011/12/05
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--! @date 2011/12/05
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--!
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--!
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--! @details
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--! @details
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--! The AXI std_logic_vector input is mapped to an internal information type.
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--! The AXI std_logic_vector input is mapped to an internal information type.
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--! Further the correct output order is handled.
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--! Further the correct output order is handled.
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--!
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--!
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library dec_viterbi;
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library dec_viterbi;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param_derived.all;
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use dec_viterbi.pkg_param_derived.all;
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use dec_viterbi.pkg_types.all;
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use dec_viterbi.pkg_types.all;
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use dec_viterbi.pkg_components.all;
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use dec_viterbi.pkg_components.all;
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use dec_viterbi.pkg_trellis.all;
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use dec_viterbi.pkg_trellis.all;
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entity dec_viterbi is
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entity dec_viterbi is
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port(
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port(
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--
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--
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-- The core only uses AXI4-Stream interfaces,
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-- The core only uses AXI4-Stream interfaces,
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-- based on AMBA4 AXI4-Stream Protocol with restrictions according to
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-- based on AMBA4 AXI4-Stream Protocol with restrictions according to
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-- Xilinx Migration, described in Xilinx AXI Reference UG761 (v13.3).
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-- Xilinx Migration, described in Xilinx AXI Reference UG761 (v13.3).
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--
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--
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aclk : in std_logic;
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aclk : in std_logic;
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-- Synchronous reset, active low.
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-- Synchronous reset, active low.
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aresetn : in std_logic;
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aresetn : in std_logic;
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--
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--
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-- Slave (input) data signals
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-- Slave (input) data signals
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-- Delivers the parity LLR values, one byte per LLR value.
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-- Delivers the parity LLR values, one byte per LLR value.
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--
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--
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s_axis_input_tvalid : in std_logic;
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s_axis_input_tvalid : in std_logic;
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s_axis_input_tdata : in std_logic_vector(31 downto 0);
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s_axis_input_tdata : in std_logic_vector(31 downto 0);
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s_axis_input_tlast : in std_logic;
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s_axis_input_tlast : in std_logic;
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s_axis_input_tready : out std_logic;
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s_axis_input_tready : out std_logic;
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--
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--
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-- Master (output) data signals
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-- Master (output) data signals
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-- Delivers the decoded systematic (payload) bits.
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-- Delivers the decoded systematic (payload) bits.
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--
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--
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m_axis_output_tvalid : out std_logic;
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m_axis_output_tvalid : out std_logic;
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m_axis_output_tdata : out std_logic;
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m_axis_output_tdata : out std_logic;
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m_axis_output_tlast : out std_logic;
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m_axis_output_tlast : out std_logic;
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m_axis_output_tready : in std_logic;
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m_axis_output_tready : in std_logic;
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--
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--
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-- Slave (input) configuration signals
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-- Slave (input) configuration signals
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-- Configures window length and acquisition length.
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-- Configures window length and acquisition length.
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--
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--
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s_axis_ctrl_tvalid : in std_logic;
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s_axis_ctrl_tvalid : in std_logic;
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s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
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s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
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s_axis_ctrl_tlast : in std_logic;
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s_axis_ctrl_tlast : in std_logic;
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s_axis_ctrl_tready : out std_logic
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s_axis_ctrl_tready : out std_logic
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);
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);
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end entity dec_viterbi;
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end entity dec_viterbi;
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architecture rtl of dec_viterbi is
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architecture rtl of dec_viterbi is
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alias clk is aclk;
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alias clk is aclk;
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signal rst : std_logic;
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signal rst : std_logic;
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-- split tdata into input array
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-- split tdata into input array
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signal input : t_input_block;
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signal input : t_input_block;
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-- buffer signals
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signal buffer_tdata : std_logic_vector(31 downto 0);
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signal buffer_tvalid : std_logic;
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signal buffer_tlast : std_logic;
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-- branch signals
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-- branch signals
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signal branch_tvalid : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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signal branch_tvalid : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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signal branch_tdata : t_branch;
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signal branch_tdata : t_branch;
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signal branch_tlast : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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signal branch_tlast : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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signal branch_tready : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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signal branch_tready : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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-- acs signals
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-- acs signals
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signal acs_tvalid : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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signal acs_tvalid : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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signal acs_tlast : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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signal acs_tlast : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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signal acs_tready : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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signal acs_tready : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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signal acs_dec_tdata : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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signal acs_dec_tdata : std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
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signal acs_prob_tdata : t_node;
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signal acs_prob_tdata : t_node;
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-- ram signals
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-- ram signals
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signal ram_tready : std_logic;
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signal ram_tready : std_logic;
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signal ram_tvalid, ram_tlast, ram_window_tuser, ram_last_tuser : std_logic_vector(1 downto 0);
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signal ram_tvalid, ram_tlast, ram_window_tuser, ram_last_tuser : std_logic_vector(1 downto 0);
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signal ram_tdata : t_ram_rd_data;
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signal ram_tdata : t_ram_rd_data;
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-- traceback signals
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-- traceback signals
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signal traceback_tvalid, traceback_tdata : std_logic_vector(1 downto 0);
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signal traceback_tvalid, traceback_tdata : std_logic_vector(1 downto 0);
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signal traceback_tready, traceback_tlast : std_logic_vector(1 downto 0);
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signal traceback_tready, traceback_tlast : std_logic_vector(1 downto 0);
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signal traceback_last_tuser : std_logic_vector(1 downto 0);
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signal traceback_last_tuser : std_logic_vector(1 downto 0);
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-- reorder signals
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-- reorder signals
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signal reorder_tready, reorder_tvalid : std_logic_vector(1 downto 0);
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signal reorder_tready, reorder_tvalid : std_logic_vector(1 downto 0);
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signal reorder_tdata, reorder_tlast : std_logic_vector(1 downto 0);
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signal reorder_tdata, reorder_tlast : std_logic_vector(1 downto 0);
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signal reorder_last_tuser : std_logic_vector(1 downto 0);
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signal reorder_last_tuser : std_logic_vector(1 downto 0);
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signal reorder_recursion_tvalid : std_logic;
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signal reorder_recursion_tdata : std_logic;
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signal reorder_recursion_tlast : std_logic;
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-- recursion signals
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signal recursion_tready : std_logic;
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-- output signals
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-- output signals
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signal output_tready : std_logic_vector(1 downto 0);
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signal output_tready : std_logic_vector(1 downto 0);
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signal current_active, semaphore_output : integer range 1 downto 0;
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signal current_active : integer range 1 downto 0;
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begin
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begin
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--
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--
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-- There is always one byte of data for each LLR value, even though each
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-- There is always one byte of data for each LLR value, even though each
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-- LLR value is represented with BW_LLR_INPUT bits. Hence, only
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-- LLR value is represented with BW_LLR_INPUT bits. Hence, only
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-- BW_LLR_INPUT bits are extracted from the byte.
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-- BW_LLR_INPUT bits are extracted from the byte.
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--
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--
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gen_input_assignment: for i in NUMBER_PARITY_BITS - 1 downto 0 generate
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gen_input_assignment: for i in NUMBER_PARITY_BITS - 1 downto 0 generate
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begin
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begin
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input(i) <= signed(s_axis_input_tdata(8 * i + BW_LLR_INPUT - 1 downto 8 * i));
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input(i) <= signed(buffer_tdata(8 * i + BW_LLR_INPUT - 1 downto 8 * i));
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end generate gen_input_assignment;
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end generate gen_input_assignment;
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rst <= not aresetn;
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rst <= not aresetn;
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------------------------------
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------------------------------
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--- Portmapping components ---
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--- Portmapping components ---
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------------------------------
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------------------------------
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-------------------------------------
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-------------------------------------
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-- AXI4S input buffer
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--------------------------------------
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inst_axi4s_buffer: axi4s_buffer
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generic map(
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DATA_WIDTH => 32
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)
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port map(
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clk => clk,
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rst => rst,
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input => s_axis_input_tdata,
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input_valid => s_axis_input_tvalid,
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input_last => s_axis_input_tlast,
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input_accept => s_axis_input_tready,
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output => buffer_tdata,
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output_valid => buffer_tvalid,
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output_last => buffer_tlast,
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output_accept => branch_tready(0)
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);
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-------------------------------------
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-- Branch metric unit
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-- Branch metric unit
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--------------------------------------
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--------------------------------------
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gen_branch_distance : for i in NUMBER_BRANCH_UNITS - 1 downto 0 generate
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gen_branch_distance : for i in NUMBER_BRANCH_UNITS - 1 downto 0 generate
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begin
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begin
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inst_branch_distance : branch_distance
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inst_branch_distance : branch_distance
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generic map(
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generic map(
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EDGE_WEIGHT => std_logic_vector(to_unsigned(i, NUMBER_PARITY_BITS))
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EDGE_WEIGHT => std_logic_vector(to_unsigned(i, NUMBER_PARITY_BITS))
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)
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)
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port map(
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port map(
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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s_axis_input_tvalid => s_axis_input_tvalid,
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s_axis_input_tvalid => buffer_tvalid,
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s_axis_input_tdata => input,
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s_axis_input_tdata => input,
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s_axis_input_tlast => s_axis_input_tlast,
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s_axis_input_tlast => buffer_tlast,
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s_axis_input_tready => branch_tready(i),
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s_axis_input_tready => branch_tready(i),
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m_axis_output_tvalid => branch_tvalid(i),
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m_axis_output_tvalid => branch_tvalid(i),
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m_axis_output_tdata => branch_tdata(i),
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m_axis_output_tdata => branch_tdata(i),
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m_axis_output_tlast => branch_tlast(i),
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m_axis_output_tlast => branch_tlast(i),
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m_axis_output_tready => acs_tready(0)
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m_axis_output_tready => acs_tready(0)
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);
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);
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end generate gen_branch_distance;
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end generate gen_branch_distance;
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-------------------------------------
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-------------------------------------
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-- ACS unit (path metric calculation)
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-- ACS unit (path metric calculation)
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--------------------------------------
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--------------------------------------
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gen_acs : for i in 0 to NUMBER_TRELLIS_STATES - 1 generate
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gen_acs : for i in 0 to NUMBER_TRELLIS_STATES - 1 generate
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signal inbranch_tdata_low : std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
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signal inbranch_tdata_low : std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
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signal inbranch_tdata_high : std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
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signal inbranch_tdata_high : std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
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signal inprev_tdata_low : std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
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signal inprev_tdata_low : std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
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signal inprev_tdata_high : std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
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signal inprev_tdata_high : std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0);
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begin
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begin
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inbranch_tdata_low <= branch_tdata(to_integer(unsigned(TRANSITIONS(i)(0))));
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inbranch_tdata_low <= branch_tdata(to_integer(unsigned(TRANSITIONS(i)(0))));
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inbranch_tdata_high <= branch_tdata(to_integer(unsigned(TRANSITIONS(i)(1))));
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inbranch_tdata_high <= branch_tdata(to_integer(unsigned(TRANSITIONS(i)(1))));
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inprev_tdata_low <= acs_prob_tdata(to_integer(unsigned(PREVIOUS_STATES(i)(0))));
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inprev_tdata_low <= acs_prob_tdata(to_integer(unsigned(PREVIOUS_STATES(i)(0))));
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inprev_tdata_high <= acs_prob_tdata(to_integer(unsigned(PREVIOUS_STATES(i)(1))));
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inprev_tdata_high <= acs_prob_tdata(to_integer(unsigned(PREVIOUS_STATES(i)(1))));
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inst_acs : acs
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inst_acs : acs
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generic map(
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generic map(
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initialize_value => INITIALIZE_TRELLIS(i)
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initialize_value => INITIALIZE_TRELLIS(i)
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)
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)
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port map(
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port map(
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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s_axis_inbranch_tvalid => branch_tvalid(0),
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s_axis_inbranch_tvalid => branch_tvalid(0),
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s_axis_inbranch_tdata_low => inbranch_tdata_low,
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s_axis_inbranch_tdata_low => inbranch_tdata_low,
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s_axis_inbranch_tdata_high => inbranch_tdata_high,
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s_axis_inbranch_tdata_high => inbranch_tdata_high,
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s_axis_inbranch_tlast => branch_tlast(0),
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s_axis_inbranch_tlast => branch_tlast(0),
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s_axis_inbranch_tready => acs_tready(i),
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s_axis_inbranch_tready => acs_tready(i),
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s_axis_inprev_tvalid => '1',
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s_axis_inprev_tvalid => '1',
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s_axis_inprev_tdata_low => inprev_tdata_low,
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s_axis_inprev_tdata_low => inprev_tdata_low,
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s_axis_inprev_tdata_high => inprev_tdata_high,
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s_axis_inprev_tdata_high => inprev_tdata_high,
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s_axis_inprev_tready => open,
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s_axis_inprev_tready => open,
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m_axis_outprob_tvalid => open,
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m_axis_outprob_tvalid => open,
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m_axis_outprob_tdata => acs_prob_tdata(i),
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m_axis_outprob_tdata => acs_prob_tdata(i),
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m_axis_outprob_tready => '1',
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m_axis_outprob_tready => '1',
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m_axis_outdec_tvalid => acs_tvalid(i),
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m_axis_outdec_tvalid => acs_tvalid(i),
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m_axis_outdec_tdata => acs_dec_tdata(i),
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m_axis_outdec_tdata => acs_dec_tdata(i),
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m_axis_outdec_tlast => acs_tlast(i),
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m_axis_outdec_tlast => acs_tlast(i),
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m_axis_outdec_tready => ram_tready
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m_axis_outdec_tready => ram_tready
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);
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);
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end generate gen_acs;
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end generate gen_acs;
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-------------------------------
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-------------------------------
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-- Traceback
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-- Traceback
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-------------------------------
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-------------------------------
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inst_ram_ctrl : ram_ctrl
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inst_ram_ctrl : ram_ctrl
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port map (
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port map (
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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s_axis_input_tvalid => acs_tvalid(0),
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s_axis_input_tvalid => acs_tvalid(0),
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s_axis_input_tdata => acs_dec_tdata,
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s_axis_input_tdata => acs_dec_tdata,
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s_axis_input_tlast => acs_tlast(0),
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s_axis_input_tlast => acs_tlast(0),
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s_axis_input_tready => ram_tready,
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s_axis_input_tready => ram_tready,
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m_axis_output_tvalid => ram_tvalid,
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m_axis_output_tvalid => ram_tvalid,
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m_axis_output_tdata => ram_tdata,
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m_axis_output_tdata => ram_tdata,
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m_axis_output_tlast => ram_tlast,
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m_axis_output_tlast => ram_tlast,
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m_axis_output_tready => traceback_tready,
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m_axis_output_tready => traceback_tready,
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m_axis_output_window_tuser => ram_window_tuser,
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m_axis_output_window_tuser => ram_window_tuser,
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m_axis_output_last_tuser => ram_last_tuser,
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m_axis_output_last_tuser => ram_last_tuser,
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|
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s_axis_ctrl_tvalid => s_axis_ctrl_tvalid,
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s_axis_ctrl_tvalid => s_axis_ctrl_tvalid,
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s_axis_ctrl_tdata => s_axis_ctrl_tdata,
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s_axis_ctrl_tdata => s_axis_ctrl_tdata,
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s_axis_ctrl_tready => s_axis_ctrl_tready
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s_axis_ctrl_tready => s_axis_ctrl_tready
|
);
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);
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|
|
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gen_inst_trellis_traceback : for i in 1 downto 0 generate
|
gen_inst_trellis_traceback : for i in 1 downto 0 generate
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begin
|
begin
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inst_trellis_traceback : trellis_traceback
|
inst_trellis_traceback : trellis_traceback
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port map(
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port map(
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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|
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s_axis_input_tvalid => ram_tvalid(i),
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s_axis_input_tvalid => ram_tvalid(i),
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s_axis_input_tdata => ram_tdata(i),
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s_axis_input_tdata => ram_tdata(i),
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s_axis_input_tlast => ram_tlast(i),
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s_axis_input_tlast => ram_tlast(i),
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s_axis_input_tready => traceback_tready(i),
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s_axis_input_tready => traceback_tready(i),
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s_axis_input_window_tuser => ram_window_tuser(i),
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s_axis_input_window_tuser => ram_window_tuser(i),
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s_axis_input_last_tuser => ram_last_tuser(i),
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s_axis_input_last_tuser => ram_last_tuser(i),
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|
|
m_axis_output_tvalid => traceback_tvalid(i),
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m_axis_output_tvalid => traceback_tvalid(i),
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m_axis_output_tdata => traceback_tdata(i),
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m_axis_output_tdata => traceback_tdata(i),
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m_axis_output_tlast => traceback_tlast(i),
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m_axis_output_tlast => traceback_tlast(i),
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m_axis_output_last_tuser => traceback_last_tuser(i),
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m_axis_output_last_tuser => traceback_last_tuser(i),
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m_axis_output_tready => reorder_tready(i)
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m_axis_output_tready => reorder_tready(i)
|
);
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);
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end generate gen_inst_trellis_traceback;
|
end generate gen_inst_trellis_traceback;
|
|
|
|
|
-------------------------------
|
-------------------------------
|
-- Reverse output order
|
-- Reverse output order
|
-------------------------------
|
-------------------------------
|
|
|
gen_inst_reorder : for i in 1 downto 0 generate
|
gen_inst_reorder : for i in 1 downto 0 generate
|
begin
|
begin
|
inst_reorder : reorder
|
inst_reorder : reorder
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
|
|
s_axis_input_tvalid => traceback_tvalid(i),
|
s_axis_input_tvalid => traceback_tvalid(i),
|
s_axis_input_tdata => traceback_tdata(i),
|
s_axis_input_tdata => traceback_tdata(i),
|
s_axis_input_tlast => traceback_tlast(i),
|
s_axis_input_tlast => traceback_tlast(i),
|
s_axis_input_last_tuser => traceback_last_tuser(i),
|
s_axis_input_last_tuser => traceback_last_tuser(i),
|
s_axis_input_tready => reorder_tready(i),
|
s_axis_input_tready => reorder_tready(i),
|
|
|
m_axis_output_tvalid => reorder_tvalid(i),
|
m_axis_output_tvalid => reorder_tvalid(i),
|
m_axis_output_tdata => reorder_tdata(i),
|
m_axis_output_tdata => reorder_tdata(i),
|
m_axis_output_tlast => reorder_tlast(i),
|
m_axis_output_tlast => reorder_tlast(i),
|
m_axis_output_last_tuser => reorder_last_tuser(i),
|
m_axis_output_last_tuser => reorder_last_tuser(i),
|
m_axis_output_tready => output_tready(i)
|
m_axis_output_tready => output_tready(i)
|
);
|
);
|
end generate gen_inst_reorder;
|
end generate gen_inst_reorder;
|
|
|
|
|
------------------------------
|
------------------------------
|
-- Recursive codes handling --
|
-- Recursive codes handling --
|
------------------------------
|
------------------------------
|
|
|
gen_inst_recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
|
gen_inst_recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
|
|
signal reorder_recursion_tvalid : std_logic;
|
|
signal reorder_recursion_tdata : std_logic;
|
|
signal reorder_recursion_tlast : std_logic;
|
|
signal recursion_tready : std_logic;
|
begin
|
begin
|
inst_recursion : recursion
|
inst_recursion : recursion
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
|
|
s_axis_input_tvalid => reorder_recursion_tvalid,
|
s_axis_input_tvalid => reorder_recursion_tvalid,
|
s_axis_input_tdata => reorder_recursion_tdata,
|
s_axis_input_tdata => reorder_recursion_tdata,
|
s_axis_input_tlast => reorder_recursion_tlast,
|
s_axis_input_tlast => reorder_recursion_tlast,
|
s_axis_input_tready => recursion_tready,
|
s_axis_input_tready => recursion_tready,
|
|
|
m_axis_output_tvalid => m_axis_output_tvalid,
|
m_axis_output_tvalid => m_axis_output_tvalid,
|
m_axis_output_tdata => m_axis_output_tdata,
|
m_axis_output_tdata => m_axis_output_tdata,
|
m_axis_output_tlast => m_axis_output_tlast,
|
m_axis_output_tlast => m_axis_output_tlast,
|
m_axis_output_tready => m_axis_output_tready
|
m_axis_output_tready => m_axis_output_tready
|
);
|
);
|
end generate gen_inst_recursion;
|
|
|
|
-------------------------------
|
-------------------------------
|
-- Input interface handling
|
-- Output interface handling
|
-------------------------------
|
-------------------------------
|
|
|
s_axis_input_tready <= branch_tready(0);
|
reorder_recursion_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
|
|
'0';
|
|
|
|
reorder_recursion_tdata <= reorder_tdata(0) when current_active = 0 else
|
|
reorder_tdata(1);
|
|
|
|
reorder_recursion_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
|
|
'0';
|
|
|
|
output_tready(0) <= '1' when (current_active = 0) and m_axis_output_tready = '1' else
|
|
'0';
|
|
output_tready(1) <= '1' when (current_active = 1) and m_axis_output_tready = '1' else
|
|
'0';
|
|
end generate gen_inst_recursion;
|
|
|
|
|
|
|
|
no_recursion: if FEEDBACK_POLYNOMIAL = 0 generate
|
|
|
-------------------------------
|
-------------------------------
|
-- Output interface handling
|
-- Output interface handling
|
-------------------------------
|
-------------------------------
|
|
|
no_recursion: if FEEDBACK_POLYNOMIAL = 0 generate
|
m_axis_output_tdata <= reorder_tdata(0) when current_active = 0 else
|
m_axis_output_tdata <= reorder_tdata(0) when reorder_tvalid(0) = '1' else
|
|
reorder_tdata(1);
|
reorder_tdata(1);
|
|
|
m_axis_output_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
|
m_axis_output_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
|
'0';
|
'0';
|
|
|
m_axis_output_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
|
m_axis_output_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
|
'0';
|
'0';
|
|
|
output_tready(0) <= '1' when (semaphore_output = 1 or current_active = 0) and m_axis_output_tready = '1' else
|
output_tready(0) <= '1' when (current_active = 0) and m_axis_output_tready = '1' else
|
'0';
|
'0';
|
output_tready(1) <= '1' when (semaphore_output = 1 or current_active = 1) and m_axis_output_tready = '1' else
|
output_tready(1) <= '1' when (current_active = 1) and m_axis_output_tready = '1' else
|
'0';
|
'0';
|
end generate no_recursion;
|
end generate no_recursion;
|
|
|
|
|
recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
|
recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
|
begin
|
begin
|
reorder_recursion_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
|
|
'0';
|
|
|
|
reorder_recursion_tdata <= reorder_tdata(0) when reorder_tvalid(0) = '1' else
|
|
reorder_tdata(1);
|
|
|
|
reorder_recursion_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
|
|
'0';
|
|
|
|
output_tready(0) <= '1' when (semaphore_output = 1 or current_active = 0) and recursion_tready = '1' else
|
|
'0';
|
|
output_tready(1) <= '1' when (semaphore_output = 1 or current_active = 1) and recursion_tready = '1' else
|
|
'0';
|
|
end generate recursion;
|
end generate recursion;
|
|
|
|
|
-- Check and merge reordering outputs and block if necessary.
|
-- Check and merge reordering outputs and block if necessary.
|
pr_reorder_tready : process(clk) is
|
pr_reorder_tready : process(clk) is
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if rst = '1' then
|
if rst = '1' then
|
current_active <= 0;
|
current_active <= 0;
|
semaphore_output <= 1;
|
|
else
|
else
|
if reorder_last_tuser(current_active) = '1' then
|
if reorder_tvalid(current_active) = '1' and m_axis_output_tready = '1' and reorder_last_tuser(current_active) = '1' then
|
semaphore_output <= 1;
|
current_active <= 1 - current_active;
|
end if;
|
|
if semaphore_output = 1 then
|
|
if reorder_tvalid(0) = '1' then
|
|
current_active <= 0;
|
|
semaphore_output <= 0;
|
|
end if;
|
|
if reorder_tvalid(1) = '1' then
|
|
current_active <= 1;
|
|
semaphore_output <= 0;
|
|
end if;
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process pr_reorder_tready;
|
end process pr_reorder_tready;
|
|
|
end architecture rtl;
|
end architecture rtl;
|
|
|
