--!
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--!
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--! Copyright (C) 2011 - 2012 Creonic GmbH
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--! Copyright (C) 2011 - 2014 Creonic GmbH
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--!
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--! under the terms of the GNU General Public License version 2.
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--!
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--!
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--! @file
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--! @file
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--! @brief Recursion unit for recursive code.
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--! @brief Recursion unit for recursive code.
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--! @author Markus Fehrenz
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--! @author Markus Fehrenz
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--! @date 2011/01/12
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--! @date 2011/01/12
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--!
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--!
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--! @details The recusion handling buffers the reorder ouput and
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--! @details The recusion handling buffers the reorder ouput and
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--! calculates the correct output depending on the feedback polynomial.
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--! calculates the correct output depending on the feedback polynomial.
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--!
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--!
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library dec_viterbi;
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library dec_viterbi;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param_derived.all;
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use dec_viterbi.pkg_param_derived.all;
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entity recursion is
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entity recursion is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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--
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--
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-- Decoded bits input from the reordering units in std_logic
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-- Decoded bits input from the reordering units in std_logic
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--
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--
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s_axis_input_tvalid : in std_logic;
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s_axis_input_tvalid : in std_logic;
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s_axis_input_tdata : in std_logic;
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s_axis_input_tdata : in std_logic;
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s_axis_input_tlast : in std_logic;
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s_axis_input_tlast : in std_logic;
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s_axis_input_tready : out std_logic;
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s_axis_input_tready : out std_logic;
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--
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--
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-- Output decoded bits convolved with the feedback polynomial
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-- Output decoded bits convolved with the feedback polynomial
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--
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--
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m_axis_output_tvalid : out std_logic;
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m_axis_output_tvalid : out std_logic;
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m_axis_output_tdata : out std_logic;
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m_axis_output_tdata : out std_logic;
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m_axis_output_tlast : out std_logic;
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m_axis_output_tlast : out std_logic;
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m_axis_output_tready : in std_logic
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m_axis_output_tready : in std_logic
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);
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);
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end entity recursion;
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end entity recursion;
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architecture rtl of recursion is
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architecture rtl of recursion is
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signal recursion_sreg : unsigned(ENCODER_MEMORY_DEPTH downto 0);
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signal recursion_sreg : unsigned(ENCODER_MEMORY_DEPTH downto 0);
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signal s_axis_input_tready_int : std_logic;
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signal s_axis_input_tready_int : std_logic;
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signal m_axis_output_tvalid_int : std_logic;
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signal m_axis_output_tvalid_int : std_logic;
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begin
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begin
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s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' or m_axis_output_tvalid_int = '0' else
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s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' or m_axis_output_tvalid_int = '0' else
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'0';
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'0';
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s_axis_input_tready <= s_axis_input_tready_int;
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s_axis_input_tready <= s_axis_input_tready_int;
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m_axis_output_tvalid <= m_axis_output_tvalid_int;
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m_axis_output_tvalid <= m_axis_output_tvalid_int;
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-- Use the feedback polynomial to convolve the global path.
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-- Use the feedback polynomial to convolve the global path.
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pr_recursion : process(clk) is
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pr_recursion : process(clk) is
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variable v_bit : std_logic := '0';
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variable v_bit : std_logic := '0';
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variable v_recursion_state : unsigned(ENCODER_MEMORY_DEPTH downto 0);
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variable v_recursion_state : unsigned(ENCODER_MEMORY_DEPTH downto 0);
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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recursion_sreg <= (others => '0');
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recursion_sreg <= (others => '0');
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m_axis_output_tdata <= '0';
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m_axis_output_tdata <= '0';
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m_axis_output_tlast <= '0';
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m_axis_output_tlast <= '0';
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else
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else
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m_axis_output_tvalid_int <= s_axis_input_tvalid;
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m_axis_output_tvalid_int <= s_axis_input_tvalid;
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if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
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if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
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-- move current decoded output bits into shift register and reset if last flag is valid
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-- move current decoded output bits into shift register and reset if last flag is valid
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if s_axis_input_tlast = '1' then
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if s_axis_input_tlast = '1' then
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recursion_sreg <= (others => '0');
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recursion_sreg <= (others => '0');
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else
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else
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recursion_sreg <= s_axis_input_tdata & recursion_sreg(ENCODER_MEMORY_DEPTH downto 1);
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recursion_sreg <= s_axis_input_tdata & recursion_sreg(ENCODER_MEMORY_DEPTH downto 1);
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end if;
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end if;
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-- convolve with feedback polynomial with the output register.
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-- convolve with feedback polynomial with the output register.
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v_bit := '0';
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v_bit := '0';
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v_recursion_state := (s_axis_input_tdata & recursion_sreg(ENCODER_MEMORY_DEPTH downto 1)) and
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v_recursion_state := (s_axis_input_tdata & recursion_sreg(ENCODER_MEMORY_DEPTH downto 1)) and
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('1' & to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH));
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('1' & to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH));
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for i in ENCODER_MEMORY_DEPTH downto 0 loop
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for i in ENCODER_MEMORY_DEPTH downto 0 loop
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v_bit := v_bit xor v_recursion_state(i);
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v_bit := v_bit xor v_recursion_state(i);
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end loop;
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end loop;
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m_axis_output_tdata <= v_bit;
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m_axis_output_tdata <= v_bit;
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m_axis_output_tlast <= s_axis_input_tlast;
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m_axis_output_tlast <= s_axis_input_tlast;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process pr_recursion;
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end process pr_recursion;
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end architecture rtl;
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end architecture rtl;
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