--!
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--!
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--! Copyright (C) 2011 - 2012 Creonic GmbH
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--! Copyright (C) 2011 - 2014 Creonic GmbH
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--!
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--! under the terms of the GNU General Public License version 2.
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--!
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--!
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--! @file
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--! @file
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--! @brief Generic Viterbi Decoder Testbench
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--! @brief Generic Viterbi Decoder Testbench
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--! @author Markus Fehrenz
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--! @author Markus Fehrenz
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--! @date 2011/12/05
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--! @date 2011/12/05
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--!
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--!
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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use std.textio.all;
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library dec_viterbi;
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library dec_viterbi;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param.all;
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use dec_viterbi.pkg_param_derived.all;
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use dec_viterbi.pkg_param_derived.all;
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use dec_viterbi.pkg_types.all;
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use dec_viterbi.pkg_types.all;
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use dec_viterbi.pkg_helper.all;
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use dec_viterbi.pkg_helper.all;
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use dec_viterbi.pkg_tb_fileio.all;
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use dec_viterbi.pkg_tb_fileio.all;
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use dec_viterbi.txt_util.all;
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use dec_viterbi.txt_util.all;
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entity tb_dec_viterbi is
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entity tb_dec_viterbi is
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generic(
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generic(
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CLK_PERIOD : time := 10 ns; -- Clock period within simulation.
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CLK_PERIOD : time := 10 ns; -- Clock period within simulation.
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BLOCK_LENGTH_START : natural := 200; -- First block length to simulate.
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BLOCK_LENGTH_START : natural := 200; -- First block length to simulate.
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BLOCK_LENGTH_END : natural := 300; -- Last block length to simulate.
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BLOCK_LENGTH_END : natural := 500; -- Last block length to simulate.
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BLOCK_LENGTH_INCR : integer := 100; -- Increment from one block length to another.
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BLOCK_LENGTH_INCR : integer := 20; -- Increment from one block length to another.
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SIM_ALL_BLOCKS : boolean := true; -- Set to true in order to simulate all blocks within a data file.
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SIM_ALL_BLOCKS : boolean := true; -- Set to true in order to simulate all blocks within a data file.
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SIM_BLOCK_START : natural := 396; -- If SIM_ALL_BLOCKS = false, gives block to start simulation with.
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SIM_BLOCK_START : natural := 0; -- If SIM_ALL_BLOCKS = false, gives block to start simulation with.
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SIM_BLOCK_END : natural := 398; -- If SIM_ALL_BLOCKS = false, gives last block of simulation.
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SIM_BLOCK_END : natural := 10; -- If SIM_ALL_BLOCKS = false, gives last block of simulation.
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WINDOW_LENGTH : natural := 55; -- Window length to use for simulation.
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WINDOW_LENGTH : natural := 55; -- Window length to use for simulation.
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ACQUISITION_LENGTH : natural := 50; -- Acquisition length to use for simulation.
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ACQUISITION_LENGTH : natural := 50; -- Acquisition length to use for simulation.
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DATA_DIRECTORY : string := "../testbench/WiFi_121_91/" -- Path to testbench data, relative to simulation directory.
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DATA_DIRECTORY : string := "../testbench/WiFi_121_91/" -- Path to testbench data, relative to simulation directory.
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);
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);
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end entity tb_dec_viterbi;
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end entity tb_dec_viterbi;
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architecture sim of tb_dec_viterbi is
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architecture sim of tb_dec_viterbi is
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component dec_viterbi is
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component dec_viterbi is
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port(
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port(
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aclk : in std_logic;
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aclk : in std_logic;
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aresetn : in std_logic;
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aresetn : in std_logic;
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s_axis_input_tvalid : in std_logic;
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s_axis_input_tvalid : in std_logic;
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s_axis_input_tdata : in std_logic_vector(31 downto 0);
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s_axis_input_tdata : in std_logic_vector(31 downto 0);
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s_axis_input_tlast : in std_logic;
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s_axis_input_tlast : in std_logic;
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s_axis_input_tready : out std_logic;
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s_axis_input_tready : out std_logic;
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m_axis_output_tvalid : out std_logic;
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m_axis_output_tvalid : out std_logic;
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m_axis_output_tdata : out std_logic;
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m_axis_output_tdata : out std_logic;
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m_axis_output_tlast : out std_logic;
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m_axis_output_tlast : out std_logic;
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m_axis_output_tready : in std_logic;
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m_axis_output_tready : in std_logic;
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s_axis_ctrl_tvalid : in std_logic;
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s_axis_ctrl_tvalid : in std_logic;
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s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
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s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
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s_axis_ctrl_tlast : in std_logic;
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s_axis_ctrl_tlast : in std_logic;
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s_axis_ctrl_tready : out std_logic
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s_axis_ctrl_tready : out std_logic
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);
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);
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end component dec_viterbi;
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end component dec_viterbi;
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal aresetn : std_logic;
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signal aresetn : std_logic;
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signal m_axis_input_tvalid : std_logic;
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signal m_axis_input_tvalid : std_logic;
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signal m_axis_input_tlast : std_logic;
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signal m_axis_input_tlast : std_logic;
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signal m_axis_input_tready : std_logic;
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signal m_axis_input_tready : std_logic;
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signal m_axis_input_tdata : std_logic_vector(31 downto 0);
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signal m_axis_input_tdata : std_logic_vector(31 downto 0);
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signal s_axis_output_tvalid : std_logic;
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signal s_axis_output_tvalid : std_logic;
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signal s_axis_output_tlast : std_logic;
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signal s_axis_output_tlast : std_logic;
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signal s_axis_output_tready : std_logic;
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signal s_axis_output_tready : std_logic;
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signal s_axis_output_tdata : std_logic;
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signal s_axis_output_tdata : std_logic;
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signal m_axis_ctrl_tvalid : std_logic;
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signal m_axis_ctrl_tvalid : std_logic;
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signal m_axis_ctrl_tlast : std_logic;
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signal m_axis_ctrl_tlast : std_logic;
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signal m_axis_ctrl_tready : std_logic;
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signal m_axis_ctrl_tready : std_logic;
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signal m_axis_ctrl_tdata : std_logic_vector(31 downto 0);
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signal m_axis_ctrl_tdata : std_logic_vector(31 downto 0);
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--
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--
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-- Input data send signals.
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-- Input data send signals.
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--
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--
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type t_send_data_fsm is (READ_FILE, CONFIGURE, SEND_DATA, SEND_DATA_FINISHED);
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type t_send_data_fsm is (READ_FILE, CONFIGURE, SEND_DATA, DEASSERT_VALID, SEND_DATA_FINISHED, SEND_FIRST_DATA);
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signal send_data_fsm : t_send_data_fsm;
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signal send_data_fsm : t_send_data_fsm;
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signal block_send_end : natural;
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signal block_send_end : natural;
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signal current_block : natural;
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signal current_block : natural;
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signal current_block_length : natural;
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signal current_block_length : natural;
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signal current_block_length_tail : natural;
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signal current_block_length_tail : natural;
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--
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--
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-- Output comparison signals.
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-- Output comparison signals.
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--
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--
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signal sys_bit_counter : natural;
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signal sys_bit_counter : natural;
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signal decoded_hardware : std_logic_vector(0 to max(BLOCK_LENGTH_START, BLOCK_LENGTH_END));
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signal decoded_hardware : std_logic_vector(0 to max(BLOCK_LENGTH_START, BLOCK_LENGTH_END));
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signal block_receive_complete : boolean;
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signal block_receive_complete : boolean;
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signal new_block_length : boolean;
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signal new_block_length : boolean;
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signal first_block_out : natural;
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signal first_block_out : natural;
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signal last_block_out : natural;
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signal last_block_out : natural;
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signal current_block_out : natural;
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signal current_block_out : natural;
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signal current_block_length_out : natural;
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signal current_block_length_out : natural;
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signal current_block_length_out_d : natural;
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signal sys_bit_counter_out : natural;
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signal sys_bit_counter_out : natural;
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-- Get filename that matches to our current configuration.
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-- Get filename that matches to our current configuration.
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function get_filename_part(v_block_length : natural;
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function get_filename_part(v_block_length : natural;
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v_window_length : natural;
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v_window_length : natural;
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v_acquisition_length : natural) return string is
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v_acquisition_length : natural) return string is
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begin
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begin
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return "BL_" & str(v_block_length) & "_WL_" & str(v_window_length) & "_AL_" & str(v_acquisition_length);
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return "BL_" & str(v_block_length) & "_WL_" & str(v_window_length) & "_AL_" & str(v_acquisition_length);
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end function get_filename_part;
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end function get_filename_part;
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shared variable v_decoded_software : t_nat_array_ptr;
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shared variable v_decoded_software : t_nat_array_ptr;
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signal valid_cnt : natural :=0;
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signal ready_cnt : natural :=0;
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begin
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begin
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clk <= not clk after CLK_PERIOD / 2;
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clk <= not clk after CLK_PERIOD / 2;
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-- initial reset
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-- initial reset
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pr_reset : process is
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pr_reset : process is
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begin
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begin
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aresetn <= '0';
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aresetn <= '0';
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wait for 2 * CLK_PERIOD;
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wait for 2 * CLK_PERIOD;
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aresetn <= '1';
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aresetn <= '1';
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wait;
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wait;
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end process;
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end process;
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-- Configuration and sending data to the core.
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-- Configuration and sending data to the core.
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pr_send : process(clk) is
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pr_send : process(clk) is
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variable v_llr : t_int_array_ptr;
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variable v_llr : t_int_array_ptr;
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variable v_filepart_ptr : t_string_ptr;
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variable v_filepart_ptr : t_string_ptr;
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variable v_filename_ptr : t_string_ptr;
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variable v_filename_ptr : t_string_ptr;
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variable v_num_lines : natural := 0;
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variable v_num_lines : natural := 0;
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variable v_num_blocks : natural := 0;
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variable v_num_blocks : natural := 0;
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variable v_current_block_length : natural := 0;
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variable v_sys_bit_counter : integer := 0;
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if aresetn = '0' then
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if aresetn = '0' then
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-- ctrl_tlast is present but unused in the decoder
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-- ctrl_tlast is present but unused in the decoder
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m_axis_ctrl_tlast <= '0';
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m_axis_ctrl_tlast <= '0';
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m_axis_ctrl_tvalid <= '0';
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m_axis_ctrl_tvalid <= '0';
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m_axis_ctrl_tdata <= (others => '0');
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m_axis_ctrl_tdata <= (others => '0');
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m_axis_input_tlast <= '0';
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m_axis_input_tlast <= '0';
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m_axis_input_tvalid <= '0';
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m_axis_input_tvalid <= '0';
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m_axis_input_tdata <= (others => '0');
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m_axis_input_tdata <= (others => '0');
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current_block_length <= BLOCK_LENGTH_START;
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current_block_length <= BLOCK_LENGTH_START;
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current_block_length_tail <= BLOCK_LENGTH_START + ENCODER_MEMORY_DEPTH;
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current_block_length_tail <= BLOCK_LENGTH_START + ENCODER_MEMORY_DEPTH;
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current_block <= 0;
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current_block <= 0;
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block_send_end <= 0;
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block_send_end <= 0;
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sys_bit_counter <= 0;
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sys_bit_counter <= 0;
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send_data_fsm <= READ_FILE;
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send_data_fsm <= READ_FILE;
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valid_cnt <= 0;
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else
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else
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case send_data_fsm is
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case send_data_fsm is
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--
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--
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-- For each block length we have a different file as reference data.
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-- For each block length we have a different file as reference data.
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-- Read it when all requested blocks of a file were simulated,
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-- Read it when all requested blocks of a file were simulated,
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-- or when we start the simulation.
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-- or when we start the simulation.
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--
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--
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when READ_FILE =>
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when READ_FILE =>
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-- Read the appropriate file
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-- Read the appropriate file
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v_filepart_ptr := new string'(get_filename_part(current_block_length, WINDOW_LENGTH, ACQUISITION_LENGTH));
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v_filepart_ptr := new string'(get_filename_part(current_block_length, WINDOW_LENGTH, ACQUISITION_LENGTH));
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v_filename_ptr := new string'(DATA_DIRECTORY & "llr_" & v_filepart_ptr.all & "_in.txt");
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v_filename_ptr := new string'(DATA_DIRECTORY & "llr_" & v_filepart_ptr.all & "_in.txt");
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v_num_lines := get_num_lines(v_filename_ptr.all);
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v_num_lines := get_num_lines(v_filename_ptr.all);
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read_file(v_llr, v_num_lines, BW_LLR_INPUT, v_filename_ptr.all);
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read_file(v_llr, v_num_lines, BW_LLR_INPUT, v_filename_ptr.all);
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-- NUMBER_PARITY_BITS lines are stored in the file per payload bit!
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-- NUMBER_PARITY_BITS lines are stored in the file per payload bit!
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v_num_blocks := v_num_lines / ((current_block_length_tail) * NUMBER_PARITY_BITS);
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v_num_blocks := v_num_lines / ((current_block_length_tail) * NUMBER_PARITY_BITS);
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-- Determine the blocks to simulate.
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-- Determine the blocks to simulate.
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if SIM_ALL_BLOCKS then
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if SIM_ALL_BLOCKS then
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current_block <= 0;
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current_block <= 0;
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block_send_end <= v_num_blocks - 1;
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block_send_end <= v_num_blocks - 1;
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else
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else
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current_block <= SIM_BLOCK_START;
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current_block <= SIM_BLOCK_START;
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block_send_end <= SIM_BLOCK_END;
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block_send_end <= SIM_BLOCK_END;
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end if;
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end if;
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send_data_fsm <= CONFIGURE;
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send_data_fsm <= CONFIGURE;
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--
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--
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-- Configure the Viterbi decoder for every single block it has to process.
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-- Configure the Viterbi decoder for every single block it has to process.
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--
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--
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when CONFIGURE =>
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when CONFIGURE =>
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-- Set control data.
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-- Set control data.
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m_axis_ctrl_tdata(16 + BW_MAX_WINDOW_LENGTH - 1 downto 16) <=
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m_axis_ctrl_tdata(16 + BW_MAX_WINDOW_LENGTH - 1 downto 16) <=
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std_logic_vector(to_unsigned(WINDOW_LENGTH, BW_MAX_WINDOW_LENGTH));
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std_logic_vector(to_unsigned(WINDOW_LENGTH, BW_MAX_WINDOW_LENGTH));
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m_axis_ctrl_tdata( BW_MAX_WINDOW_LENGTH - 1 downto 0) <=
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m_axis_ctrl_tdata( BW_MAX_WINDOW_LENGTH - 1 downto 0) <=
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std_logic_vector(to_unsigned(ACQUISITION_LENGTH, BW_MAX_WINDOW_LENGTH));
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std_logic_vector(to_unsigned(ACQUISITION_LENGTH, BW_MAX_WINDOW_LENGTH));
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-- Check whether configuration succeeded
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-- Check whether configuration succeeded
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if m_axis_ctrl_tvalid = '1' and m_axis_ctrl_tready = '1' then
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if m_axis_ctrl_tvalid = '1' and m_axis_ctrl_tready = '1' then
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m_axis_ctrl_tvalid <= '0';
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m_axis_ctrl_tvalid <= '0';
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send_data_fsm <= SEND_DATA;
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send_data_fsm <= SEND_FIRST_DATA;
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else
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else
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m_axis_ctrl_tvalid <= '1';
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m_axis_ctrl_tvalid <= '1';
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end if;
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end if;
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when SEND_FIRST_DATA =>
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for j in 0 to NUMBER_PARITY_BITS - 1 loop
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m_axis_input_tdata(j * 8 + BW_LLR_INPUT - 1 downto j * 8) <=
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std_logic_vector(to_signed(v_llr(current_block * (current_block_length_tail * NUMBER_PARITY_BITS) + sys_bit_counter * NUMBER_PARITY_BITS + j), BW_LLR_INPUT));
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end loop;
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sys_bit_counter <= sys_bit_counter + 1;
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send_data_fsm <= SEND_DATA;
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m_axis_input_tvalid <= '1';
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--
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--
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-- Send all data of a block. If we are done with this, we check what to do next:
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-- Send all data of a block. If we are done with this, we check what to do next:
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-- 1) Configure the decoder to process the next block of the same length.
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-- 1) Configure the decoder to process the next block of the same length.
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-- 2) Read a new file if all blocks of this block length were simulated.
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-- 2) Read a new file if all blocks of this block length were simulated.
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-- 3) Quit simulation if all blocks of all block lengths were simulated.
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-- 3) Quit simulation if all blocks of all block lengths were simulated.
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--
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--
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when SEND_DATA =>
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when SEND_DATA =>
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m_axis_input_tvalid <= '1';
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m_axis_input_tvalid <= '1';
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-- Data transmission => increase bit counter and update data for next cycle.
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-- Data transmission => increase bit counter and update data for next cycle.
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if m_axis_input_tvalid = '1' and m_axis_input_tready = '1' then
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if m_axis_input_tvalid = '1' and m_axis_input_tready = '1' then
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v_sys_bit_counter := sys_bit_counter + 1;
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if valid_cnt = 5 then
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sys_bit_counter <= v_sys_bit_counter;
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valid_cnt <= 0;
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send_data_fsm <= DEASSERT_VALID;
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m_axis_input_tvalid <= '0';
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else
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else
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v_sys_bit_counter := sys_bit_counter;
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valid_cnt <= valid_cnt + 1;
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end if;
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sys_bit_counter <= sys_bit_counter + 1;
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end if;
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end if;
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if v_sys_bit_counter < current_block_length_tail then
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if m_axis_input_tvalid = '1' and m_axis_input_tready = '1' then
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if sys_bit_counter < current_block_length_tail then
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-- trim and move data to stream
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-- trim and move data to stream
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for j in 0 to NUMBER_PARITY_BITS - 1 loop
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for j in 0 to NUMBER_PARITY_BITS - 1 loop
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m_axis_input_tdata(j * 8 + BW_LLR_INPUT - 1 downto j * 8) <=
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m_axis_input_tdata(j * 8 + BW_LLR_INPUT - 1 downto j * 8) <=
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std_logic_vector(to_signed(v_llr(current_block * (current_block_length_tail * NUMBER_PARITY_BITS) + v_sys_bit_counter * NUMBER_PARITY_BITS + j), BW_LLR_INPUT));
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std_logic_vector(to_signed(v_llr(current_block * (current_block_length_tail * NUMBER_PARITY_BITS) + sys_bit_counter * NUMBER_PARITY_BITS + j), BW_LLR_INPUT));
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end loop;
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end loop;
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end if;
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end if;
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|
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-- Next data will be last of block
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-- Next data will be last of block
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if v_sys_bit_counter = current_block_length_tail - 1 then
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if sys_bit_counter = current_block_length_tail - 1 then
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m_axis_input_tlast <= '1';
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m_axis_input_tlast <= '1';
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else
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else
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m_axis_input_tlast <= '0';
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m_axis_input_tlast <= '0';
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end if;
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end if;
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end if;
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|
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-- We have just sent the very last bit of this block.
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-- We have just sent the very last bit of this block.
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if m_axis_input_tvalid = '1' and
|
if m_axis_input_tvalid = '1' and m_axis_input_tready = '1' and
|
m_axis_input_tready = '1' and
|
|
m_axis_input_tlast = '1' then
|
m_axis_input_tlast = '1' then
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-- if v_sys_bit_counter = current_block_length then
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sys_bit_counter <= 0;
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sys_bit_counter <= 0;
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m_axis_input_tvalid <= '0';
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m_axis_input_tvalid <= '0';
|
|
|
-- Did we process the last block of a block length?
|
-- Did we process the last block of a block length?
|
if current_block = block_send_end then
|
if current_block = block_send_end then
|
|
|
-- Go to next block length, if we are not done.
|
-- Go to next block length, if we are not done.
|
if current_block_length_tail = BLOCK_LENGTH_END + ENCODER_MEMORY_DEPTH then
|
if current_block_length_tail = BLOCK_LENGTH_END + ENCODER_MEMORY_DEPTH then
|
send_data_fsm <= SEND_DATA_FINISHED;
|
send_data_fsm <= SEND_DATA_FINISHED;
|
else
|
else
|
send_data_fsm <= READ_FILE;
|
send_data_fsm <= READ_FILE;
|
current_block_length <= current_block_length + BLOCK_LENGTH_INCR;
|
current_block_length <= current_block_length + BLOCK_LENGTH_INCR;
|
current_block_length_tail <= current_block_length + BLOCK_LENGTH_INCR + ENCODER_MEMORY_DEPTH;
|
current_block_length_tail <= current_block_length + BLOCK_LENGTH_INCR + ENCODER_MEMORY_DEPTH;
|
end if;
|
end if;
|
else
|
else
|
send_data_fsm <= CONFIGURE;
|
send_data_fsm <= CONFIGURE;
|
current_block <= current_block + 1;
|
current_block <= current_block + 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
when DEASSERT_VALID =>
|
|
send_data_fsm <= SEND_DATA;
|
|
|
--
|
--
|
-- We are done with all blocks, do nothing anynmore.
|
-- We are done with all blocks, do nothing anynmore.
|
--
|
--
|
when SEND_DATA_FINISHED =>
|
when SEND_DATA_FINISHED =>
|
|
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
--
|
--
|
-- Process receives the decoded data from the Viterbi decoder
|
-- Process receives the decoded data from the Viterbi decoder
|
-- The received data is compared to a test vector
|
-- The received data is compared to a test vector
|
--
|
--
|
pr_receive : process(clk) is
|
pr_receive : process(clk) is
|
variable v_filepart_ptr : t_string_ptr;
|
variable v_filepart_ptr : t_string_ptr;
|
variable v_filename_ptr : t_string_ptr;
|
variable v_filename_ptr : t_string_ptr;
|
variable v_num_lines : natural := 0;
|
variable v_num_lines : natural := 0;
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if aresetn = '0' then
|
if aresetn = '0' then
|
|
|
current_block_length_out <= 0;
|
current_block_length_out <= 0;
|
current_block_length_out_d <= 0;
|
|
sys_bit_counter_out <= 0;
|
sys_bit_counter_out <= 0;
|
s_axis_output_tready <= '1';
|
s_axis_output_tready <= '1';
|
block_receive_complete <= false;
|
block_receive_complete <= false;
|
new_block_length <= false;
|
new_block_length <= false;
|
|
ready_cnt <= 0;
|
|
|
else
|
else
|
|
|
block_receive_complete <= false;
|
block_receive_complete <= false;
|
new_block_length <= false;
|
new_block_length <= false;
|
current_block_length_out_d <= current_block_length_out;
|
s_axis_output_tready <= '1';
|
|
|
-- Data passes the output interface.
|
-- Data passes the output interface.
|
if s_axis_output_tvalid = '1' and s_axis_output_tready = '1' then
|
if s_axis_output_tvalid = '1' and s_axis_output_tready = '1' then
|
|
if ready_cnt = 8 then
|
|
ready_cnt <= 0;
|
|
s_axis_output_tready <= '0';
|
|
else
|
|
ready_cnt <= ready_cnt + 1;
|
|
end if;
|
|
|
decoded_hardware(sys_bit_counter_out) <= s_axis_output_tdata;
|
decoded_hardware(sys_bit_counter_out) <= s_axis_output_tdata;
|
|
|
sys_bit_counter_out <= sys_bit_counter_out + 1;
|
sys_bit_counter_out <= sys_bit_counter_out + 1;
|
|
|
-- This is the last bit of the flag.
|
-- This is the last bit of the flag.
|
if s_axis_output_tlast = '1' then
|
if s_axis_output_tlast = '1' then
|
block_receive_complete <= true;
|
block_receive_complete <= true;
|
current_block_length_out <= sys_bit_counter_out + 1;
|
current_block_length_out <= sys_bit_counter_out + 1;
|
sys_bit_counter_out <= 0;
|
sys_bit_counter_out <= 0;
|
|
|
-- Block received and block length changed => read file of correct blocks.
|
-- Block received and block length changed => read file of correct blocks.
|
if current_block_length_out /= sys_bit_counter_out + 1 then
|
if current_block_length_out /= sys_bit_counter_out + 1 then
|
new_block_length <= true;
|
new_block_length <= true;
|
v_filepart_ptr := new string'(get_filename_part(sys_bit_counter_out + 1, WINDOW_LENGTH, ACQUISITION_LENGTH));
|
v_filepart_ptr := new string'(get_filename_part(sys_bit_counter_out + 1, WINDOW_LENGTH, ACQUISITION_LENGTH));
|
v_filename_ptr := new string'(DATA_DIRECTORY & "decoded_" & v_filepart_ptr.all & "_out.txt");
|
v_filename_ptr := new string'(DATA_DIRECTORY & "decoded_" & v_filepart_ptr.all & "_out.txt");
|
v_num_lines := get_num_lines(v_filename_ptr.all);
|
v_num_lines := get_num_lines(v_filename_ptr.all);
|
read_file(v_decoded_software, v_num_lines, BW_LLR_INPUT, v_filename_ptr.all);
|
read_file(v_decoded_software, v_num_lines, BW_LLR_INPUT, v_filename_ptr.all);
|
|
|
if SIM_ALL_BLOCKS then
|
if SIM_ALL_BLOCKS then
|
first_block_out <= 0;
|
first_block_out <= 0;
|
last_block_out <= v_num_lines / (sys_bit_counter_out + 1);
|
last_block_out <= v_num_lines / (sys_bit_counter_out + 1) - 1;
|
else
|
else
|
first_block_out <= SIM_BLOCK_START;
|
first_block_out <= SIM_BLOCK_START;
|
last_block_out <= SIM_BLOCK_END;
|
last_block_out <= SIM_BLOCK_END;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end if; -- reset
|
end if; -- reset
|
end if;
|
end if;
|
end process pr_receive;
|
end process pr_receive;
|
|
|
|
|
|
|
--
|
--
|
-- Compare the block we just received from the decoder with the data stored within the files.
|
-- Compare the block we just received from the decoder with the data stored within the files.
|
-- Stop simulation if everything was simulated.
|
-- Stop simulation if everything was simulated.
|
--
|
--
|
pr_compare : process(clk) is
|
pr_compare : process(clk) is
|
variable v_bit_error_count : natural := 0;
|
variable v_bit_error_count : natural := 0;
|
variable v_line_out : line;
|
variable v_line_out : line;
|
variable v_current_block : natural;
|
variable v_current_block : natural;
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if aresetn = '0' then
|
if aresetn = '0' then
|
|
|
current_block_out <= 0;
|
current_block_out <= 0;
|
|
|
else
|
else
|
|
|
-- Which is our current block?
|
-- Which is our current block?
|
if new_block_length then
|
if new_block_length then
|
v_current_block := first_block_out;
|
v_current_block := first_block_out;
|
else
|
else
|
v_current_block := current_block_out;
|
v_current_block := current_block_out;
|
end if;
|
end if;
|
|
|
-- We got a whole block from the decoder, compare whether decoding was successful.
|
-- We got a whole block from the decoder, compare whether decoding was successful.
|
if block_receive_complete then
|
if block_receive_complete then
|
|
|
for i in 0 to current_block_length_out - 1 loop
|
for i in 0 to current_block_length_out - 1 loop
|
if (v_decoded_software(v_current_block * current_block_length_out + i) = 0 and decoded_hardware(i) = '1') or
|
if (v_decoded_software(v_current_block * current_block_length_out + i) = 0 and decoded_hardware(i) = '1') or
|
(v_decoded_software(v_current_block * current_block_length_out + i) = 1 and decoded_hardware(i) = '0') then
|
(v_decoded_software(v_current_block * current_block_length_out + i) = 1 and decoded_hardware(i) = '0') then
|
|
|
v_bit_error_count := v_bit_error_count + 1;
|
v_bit_error_count := v_bit_error_count + 1;
|
|
|
assert false report "Decoded bit " & str(i) & " in block " & str(v_current_block) & " does not match!"
|
assert false report "Decoded bit " & str(i) & " in block " & str(v_current_block) & " does not match!"
|
severity warning;
|
severity failure;
|
end if;
|
end if;
|
end loop;
|
end loop;
|
|
|
-- Dump message.
|
-- Dump message.
|
write(v_line_out, string'("Block length: ") & str(current_block_length_out));
|
write(v_line_out, string'("Block length: ") & str(current_block_length_out));
|
write(v_line_out, string'(", Block: ") & str(current_block_out));
|
write(v_line_out, string'(", Block: ") & str(v_current_block));
|
write(v_line_out, string'(", errors: ") & str(v_bit_error_count));
|
write(v_line_out, string'(", errors: ") & str(v_bit_error_count));
|
|
writeline(output, v_line_out);
|
|
|
if current_block_out /= last_block_out - 1 then
|
|
current_block_out <= current_block_out + 1;
|
current_block_out <= current_block_out + 1;
|
else
|
|
|
if current_block_out = last_block_out then
|
current_block_out <= 0;
|
current_block_out <= 0;
|
|
|
-- Stop simulation, if we are done with all blocks of all block lengths.
|
-- Stop simulation, if we are done with all blocks of all block lengths.
|
if current_block_length_out = BLOCK_LENGTH_END then
|
if current_block_length_out = BLOCK_LENGTH_END then
|
assert false report "End" severity failure;
|
assert false report "Simulation finished with no errors." severity failure;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process pr_compare;
|
end process pr_compare;
|
|
|
|
|
inst_dec_viterbi : dec_viterbi
|
inst_dec_viterbi : dec_viterbi
|
port map(
|
port map(
|
aclk => clk,
|
aclk => clk,
|
aresetn => aresetn,
|
aresetn => aresetn,
|
|
|
s_axis_input_tvalid => m_axis_input_tvalid,
|
s_axis_input_tvalid => m_axis_input_tvalid,
|
s_axis_input_tdata => m_axis_input_tdata,
|
s_axis_input_tdata => m_axis_input_tdata,
|
s_axis_input_tlast => m_axis_input_tlast,
|
s_axis_input_tlast => m_axis_input_tlast,
|
s_axis_input_tready => m_axis_input_tready,
|
s_axis_input_tready => m_axis_input_tready,
|
|
|
m_axis_output_tvalid => s_axis_output_tvalid,
|
m_axis_output_tvalid => s_axis_output_tvalid,
|
m_axis_output_tdata => s_axis_output_tdata,
|
m_axis_output_tdata => s_axis_output_tdata,
|
m_axis_output_tlast => s_axis_output_tlast,
|
m_axis_output_tlast => s_axis_output_tlast,
|
m_axis_output_tready => s_axis_output_tready,
|
m_axis_output_tready => s_axis_output_tready,
|
|
|
s_axis_ctrl_tvalid => m_axis_ctrl_tvalid,
|
s_axis_ctrl_tvalid => m_axis_ctrl_tvalid,
|
s_axis_ctrl_tdata => m_axis_ctrl_tdata,
|
s_axis_ctrl_tdata => m_axis_ctrl_tdata,
|
s_axis_ctrl_tlast => m_axis_ctrl_tlast,
|
s_axis_ctrl_tlast => m_axis_ctrl_tlast,
|
s_axis_ctrl_tready => m_axis_ctrl_tready
|
s_axis_ctrl_tready => m_axis_ctrl_tready
|
);
|
);
|
|
|
end architecture sim;
|
end architecture sim;
|
|
|
