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%% Filename: spec.tex
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%% Filename: spec.tex
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%% Project: Wishbone to ICAPE2 interface conversion
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%% Project: Wishbone to ICAPE2 interface conversion
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%%
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%% Purpose: This LaTeX file contains all of the documentation/description
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%% Purpose: This LaTeX file contains all of the documentation/description
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%% currently provided with this FPGA Real-time Clock Core.
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%% currently provided with this FPGA Real-time Clock Core.
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%% It's not nearly as interesting as the PDF file it creates,
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%% Creator: Dan Gisselquist
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%% Creator: Dan Gisselquist
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%% Gisselquist Technology, LLC
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%% Gisselquist Technology, LLC
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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|
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\documentclass{gqtekspec}
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\documentclass{gqtekspec}
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\project{Real-Time Clock}
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\project{ICAPE2 Access via Wishbone}
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\title{Specification}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~0.1}
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\revision{Rev.~0.1}
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\begin{document}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\pagestyle{gqtekspecplain}
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\titlepage
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\titlepage
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\begin{license}
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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|
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This project is free software (firmware): you can redistribute it and/or
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This project is free software (firmware): you can redistribute it and/or
|
modify it under the terms of the GNU General Public License as published
|
modify it under the terms of the GNU General Public License as published
|
by the Free Software Foundation, either version 3 of the License, or (at
|
by the Free Software Foundation, either version 3 of the License, or (at
|
your option) any later version.
|
your option) any later version.
|
|
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
|
ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
for more details.
|
for more details.
|
|
|
You should have received a copy of the GNU General Public License along
|
You should have received a copy of the GNU General Public License along
|
with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
|
with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
|
copy.
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copy.
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\end{license}
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\end{license}
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\begin{revisionhistory}
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\begin{revisionhistory}
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0.2 & 4/22/2016 & Gisselquist & Minor Updates \\\hline
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0.1 & 5/25/2015 & Gisselquist & First Draft \\\hline
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0.1 & 5/25/2015 & Gisselquist & First Draft \\\hline
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\end{revisionhistory}
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\end{revisionhistory}
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% Revision History
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% Revision History
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% Table of Contents, named Contents
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% Table of Contents, named Contents
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\tableofcontents
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\tableofcontents
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% \listoffigures
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% \listoffigures
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\listoftables
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\listoftables
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\begin{preface}
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\begin{preface}
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My thanks to those helpers on the Xilinx Forum who helped me get the final
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My thanks to those helpers on the Xilinx Forum who helped me through the final
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step to getting this working.
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step in getting this working.
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\end{preface}
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\end{preface}
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\chapter{Introduction}
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\chapter{Introduction}
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\pagenumbering{arabic}
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\pagenumbering{arabic}
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\setcounter{page}{1}
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\setcounter{page}{1}
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|
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This core makes the ICAPE2 FPGA configuration registers available to be read
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This core makes the ICAPE2 FPGA configuration registers available to be read
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or written from a wishbone bus. As the documentation of this capability could
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or written from a wishbone bus. As Xilinx's documentation of this capability
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use a bit to be desired, I have put this file together to help document
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leaves a bit to be desired, I have put this file together to help document
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what works.
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what works.
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The interface itself is very valuable for a couple of purposes---from my humble
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The interface itself is very valuable for a couple of purposes---from my humble
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and personal perspective. The first is the user configurable watchdog timer
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and personal perspective. The first is the user configurable watchdog timer
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which can be used to automatically reset an FPGA after it locks up. The second
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which can be used to automatically reset an FPGA after it locks up. The second
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is the warm boot start capability, which makes it possible to create a fall
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is the warm boot start capability, which makes it possible to create a fall
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back configuration image and test it without compromising the ability of the
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back configuration image and test it without compromising the ability of the
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FPGA to be started in a known good image. The third valuable capability is that
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FPGA to be started in a known good image. The third valuable capability is that
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of commanding a reconfiguration. All of these capabilities are available
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of commanding a reconfiguration. All of these capabilities are available
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through this interface. Further details are available from Xilinx's "7-Series
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through this interface. Further details are available from Xilinx's ``7-Series
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FPGAs Configuration" User Guide.
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FPGAs Configuration'' User Guide\footnote{For the Spartan, further details are
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available in the ``Spartan--6 FPGA Coniguration'' User Guide}.
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This introduction is the first chapter. Beyond this introduction, most
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This introduction is the first chapter. Beyond this introduction, most
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of the capabilities are documented elsewhere. Hence, the register chapter
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of the capabilities are documented elsewhere. Hence, the register chapter
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will be omitted and the reader will be gently pointed to the User's Guide.
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will be omitted and the reader will be gently pointed to the User's Guide.
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This leaves the Wishbone chapter and the I/O Port's chapter which follow.
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This leaves the Wishbone chapter and the I/O Port's chapter which follow.
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|
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As always, write me if you have any questions or problems.
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As always, write me if you have any questions or problems.
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\chapter{Architecture}\label{chap:arch}
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\chapter{Architecture}\label{chap:arch}
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|
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If I understand correctly, every one of Xilinx's 7--Series FPGA's contains
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If I understand correctly, every one of Xilinx's 7--Series FPGA's contains
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two ICAPE2 interface modules. These modules allow user logic to communicate
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two ICAPE2 interface modules. These modules allow user logic to communicate
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with the configuration interface of the chip. This interface, however, isn't
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with the configuration interface of the chip. This interface, however, isn't
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well documented. According to the User's Guide, it matches the SelectMAP
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well documented. According to the User's Guide, it matches the SelectMAP
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interface, yet in practice \ldots it doesn't.
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interface, yet in practice \ldots it doesn't. It may come close, but the
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timing and interface requirements of the SelectMAP aren't really the same as the
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ICAPE2 port.
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|
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This core encapsulates the difficulty of matching that interface. Register
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This core encapsulates the difficulty of matching that interface. Register
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addresses match those in the User's Guide, as do register definitions.
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addresses match those in the User's Guide, as do register definitions.
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\chapter{Operation}\label{chap:ops}
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\chapter{Operation}\label{chap:ops}
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|
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Consider the warm boot reload operation. To do this, write the address in
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Realistically, this is better documented by Xilinx than anything you will find
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configuration memory of an FPGA image to the warm boot start address (WBSTAR).
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here. Still, two examples might be worthwhile.
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In this case, that is address 5'h10 within this interface. A second write to
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the configuration command address (CMD), 5'h4 in this interface, will issue the
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First, consider the warm boot reload operation. To do this, write the address
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IPROG command to the FPGA and cause it to configure itself from the address
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in configuration memory of an FPGA image to the warm boot start address
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you just gave it.
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(WBSTAR). In this case, that is address 5'h10 within this interface. A second
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write to the configuration command address (CMD), 5'h4 in this interface, will
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issue the IPROG command to the FPGA and cause it to configure itself from the
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address you just gave it. You can see this from C pseudo code in
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Fig.~\ref{fig:warmboot}.
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\begin{figure}\begin{center}\begin{tabbing}
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{\tt warmboot(uint32 address) \{} \\
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\hbox to 0.25in{}\={\tt uint32\_t *icape = (volatile uint32\_t *)0x{\em <ICAPE port address>};}\\
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\>{\tt icape[16] = address};\\
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\>{\tt icape[4] = 15};\\
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\>{\em // FPGA is now reconfiguring itself from the new address}\\
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\>{\em // If executed on an FPGA, this routine will never return.}\\
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{\tt \}}
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\end{tabbing}
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\caption{Series--7 ICAPE2 Usage}\label{fig:warmboot}
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\end{center}\end{figure}
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There, wasn't that simple?
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There, wasn't that simple?
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We could do it for the Spartan--6 as well, as shown in Fig.~\ref{fig:sp6boot}.
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\begin{figure}\begin{center}\begin{tabbing}
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{\tt warmboot(uint32 address) \{} \\
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\hbox to 0.25in{}\={\tt uint32\_t *icape6 = (volatile uint32\_t *)0x{\em <ICAPE port address>};}\\
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\>{\tt icape6[13] = (address<<2)\&0x0ffff;}\\
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\>{\tt icape6[14] = ((address>>14)\&0x0ff)|((0x03)<<8);}\\
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\>{\tt icape6[4] = 14;}\\
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\>{\em // The Spartan--6 is now reconfiguring itself from the new address.}\\
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\>{\em // If executed from a softcore internal to a Spartan--6, this routine}\\
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\>{\em // will never return.}\\
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{\tt \}}
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\end{tabbing}
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\caption{Spartan--6 ICAPE Usage}\label{fig:sp6boot}
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\end{center}\end{figure}
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|
|
Now I can, from the comfort of my home, reconfigure an FPGA in my office without
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Now I can, from the comfort of my home, reconfigure an FPGA in my office without
|
needing to press the power button or connect to a JTAG cable. Not bad, no?
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needing to press the power button or connect to a JTAG cable. Not bad, no?
|
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\iffalse
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\chapter{Configuration Registers}\label{chap:registers}
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% Tbl.~\ref{tbl:wishbone}
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% 7 Series
|
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\begin{table}[htbp]\begin{center}\hline
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\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{2.875in}|}\hline
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|
\rowcolor[gray]{0.85} Name & Address & Access & Description \\\hline\hline
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CRC & {\tt 0x00} & R/W & CRC Register \\\hline
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FAR & {\tt 0x01} & R/W & Frame Address Register\\\hline
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FDRI & {\tt 0x02} & W & Frame Data Register, Input Register (write configuration data)\\\hline
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FDRO & {\tt 0x03} & R & Frame Data Register, Output Register (read configuration data)\\\hline
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CMD & {\tt 0x04} & R/W & Command Register\\\hline
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CTL0 & {\tt 0x05} & R/W & Control Register 0\\\hline
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MASK & {\tt 0x06} & R/W & Masking Register for CTL0 and CTL1\\\hline
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STAT & {\tt 0x07} & R & Status Register\\\hline
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LOUT & {\tt 0x08} & W & Legacy Output Register for Daisy Chain\\\hline
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COR0 & {\tt 0x09} & R/W & Configuration Option Register 0\\\hline
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MFWR & {\tt 0x0a} & W & Multiple Frame Write Register \\\hline
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CBC & {\tt 0x0b} & W & Initial CBC Value Register \\\hline
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IDCODE & {\tt 0x0c} & R/W & Device ID Register\\\hline
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AXSS & {\tt 0x0d} & R/W & User Access Register \\\hline
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COR1 & {\tt 0x0e} & R/W & Configuration Options Register 1\\\hline
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WBSTAR & {\tt 0x10} & R/W & Warm boot Start Addres Register \\\hline
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TIMER & {\tt 0x11} & R/W & Watchdog Timer Register\\\hline
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BOOTSTS & {\tt 0x16} & R & Boot History Status Register \\\hline
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CTL1 & {\tt 0x18} & R/W & Control Register 1 \\\hline
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BSPI & {\tt 0x1f} & R/W & BPI/SPI Configuration Options Register\\\hline
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\end{tabular}
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\caption{7--Series Configuration Register Addresses}\label{tbl:7addrs}
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\end{center}\end{table}
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% SPARTAN-6 series
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\begin{table}[htbp]\begin{center}\hline
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\begin{tabular}
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\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{2.875in}|}\hline
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\rowcolor[gray]{0.85} Name & Address & Access & Description \\\hline\hline
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CRC & {\tt 0x00} & W & Cyclic Redundancy Check\\\hline
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FAR\_MAJ & {\tt 0x01} & W & Frame Address Register Block and Major\\\hline
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FAR\_MIN & {\tt 0x02} & W & Frame Address Register Minor\\\hline
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FDRI & {\tt 0x03} & W & Frame Data Input\\\hline
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FDRO & {\tt 0x04} & R & Frame Data Output\\\hline
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CMD & {\tt 0x05} & R/W & Command \\\hline
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CTL & {\tt 0x06} & R/W & Control \\\hline
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MASK & {\tt 0x07} & R/W & Control Mask\\\hline
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STAT & {\tt 0x08} & R & Status \\\hline
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LOUT & {\tt 0x09} & W & Legacy Output for Daisy Chain\\\hline
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COR1 & {\tt 0x0a} & R/W & Configuration Option 1\\\hline
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COR2 & {\tt 0x0b} & R/W & Configuration Option 2\\\hline
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PWRDN\_REG & {\tt 0x0c} & R/W & Power Down Option Register\\\hline
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FLR & {\tt 0x0d} & W & Frame Length Register\\\hline
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IDCODE & {\tt 0x0e} & R/W & Product IDCODE\\\hline
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CWDT & {\tt 0x0f} & R/W & Configuration Watchdog Timer\\\hline
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HC\_OPT\_REG & {\tt 0x10} & R/W & House Clean Option Register\\\hline
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CSBO & {\tt 0x12} & W & CSB Output for Parallel Daisy Chaining\\\hline
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GENERAL1 & {\tt 0x13} & R/W & Power up Self-Test or Loadable Program Address\\\hline
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GENERAL2 & {\tt 0x14} & R/W & Power up Self-Test or Loadable Program Address and new SPI opcode\\\hline
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GENERAL3 & {\tt 0x15} & R/W & Golden Bitstream Address\\\hline
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GENERAL4 & {\tt 0x16} & R/W & Golden Bitstream Address and new SPI Opcode\\\hline
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GENERAL5 & {\tt 0x17} & R/W & User-defined register for fail-safe scheme\\\hline
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MODE\_REG & {\tt 0x18} & R/W & Reboot mode\\\hline
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PU\_GWE & {\tt 0x19} & W & GWE cycle during wake-up from suspend\\\hline
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PU\_GTS & {\tt 0x1a} & W & GTS cycle during wake-up from suspend\\\hline
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MFWR & {\tt 0x1b} & W & Multi-frame write register\\\hline
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CCLK\_FREQ & {\tt 0x1c} & W & CCLK frequency select for master mode\\\hline
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SEU\_OPT & {\tt 0x1d} & R/W & SEU frequency, enable and status\\\hline
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EXP\_SIGN & {\tt 0x1e} & R/W & Expected readback signature for SEU detection\\\hline
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RDBK\_SIGN & {\tt 0x1f} & W & Readback signature for readback command and SEU\\\hline
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BOOTSTS & {\tt 0x20} & R & Boot History Register\\\hline
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EYE\_MASK & {\tt 0x21} & R/W & Mask pins for Multi--Pin Wake-up\\\hline
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CBC\_REG & {\tt 0x22} & W & Initial CBC Value Register\\\hline
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\end{tabular}
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\caption{Spartan--6 Configuration Register Addresses}\label{tbl:6addrs}
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\end{center}\end{table}
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% icape->general1 = (fpgaddr<<2);
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% icape->general2 = ((fpgaddr>>14)&0x0ff)|((0x03)<<8);
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% icape->cmd = 0x0e // IPROG
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\fi
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\chapter{Wishbone Datasheet}\label{chap:wishbone}
|
\chapter{Wishbone Datasheet}\label{chap:wishbone}
|
Tbl.~\ref{tbl:wishbone}
|
Tbl.~\ref{tbl:wishbone}
|
\begin{table}[htbp]
|
\begin{table}[htbp]
|
\begin{center}
|
\begin{center}
|
\begin{wishboneds}
|
\begin{wishboneds}
|
Revision level of wishbone & WB B4 spec \\\hline
|
Revision level of wishbone & WB B4 spec \\\hline
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Type of interface & Slave, Read/Write \\\hline
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Type of interface & Slave, Read/Write \\\hline
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Port size & 32--bit \\\hline
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Port size & 32--bit \\\hline
|
Port granularity & 32--bit \\\hline
|
Port granularity & 32--bit \\\hline
|
Maximum Operand Size & 32--bit \\\hline
|
Maximum Operand Size & 32--bit \\\hline
|
Data transfer ordering & (Irrelevant) \\\hline
|
Data transfer ordering & (Irrelevant) \\\hline
|
Clock constraints & See the Datasheet for your part\\\hline
|
Clock constraints & See the Datasheet for your part\\\hline
|
Signal Names & \begin{tabular}{ll}
|
Signal Names & \begin{tabular}{ll}
|
Signal Name & Wishbone Equivalent \\\hline
|
Signal Name & Wishbone Equivalent \\\hline
|
{\tt i\_clk} & {\tt CLK\_I} \\
|
{\tt i\_clk} & {\tt CLK\_I} \\
|
{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
|
{\tt i\_wb\_cyc} & {\tt CYC\_I} \\
|
{\tt i\_wb\_stb} & {\tt STB\_I} \\
|
{\tt i\_wb\_stb} & {\tt STB\_I} \\
|
{\tt i\_wb\_we} & {\tt WE\_I} \\
|
{\tt i\_wb\_we} & {\tt WE\_I} \\
|
{\tt i\_wb\_addr} & {\tt ADR\_I} \\
|
{\tt i\_wb\_addr} & {\tt ADR\_I} \\
|
{\tt i\_wb\_data} & {\tt DAT\_I} \\
|
{\tt i\_wb\_data} & {\tt DAT\_I} \\
|
{\tt o\_wb\_ack} & {\tt ACK\_O} \\
|
{\tt o\_wb\_ack} & {\tt ACK\_O} \\
|
{\tt o\_wb\_stall} & {\tt STALL\_O} \\
|
{\tt o\_wb\_stall} & {\tt STALL\_O} \\
|
{\tt o\_wb\_data} & {\tt DAT\_O}
|
{\tt o\_wb\_data} & {\tt DAT\_O}
|
\end{tabular}\\\hline
|
\end{tabular}\\\hline
|
\end{wishboneds}
|
\end{wishboneds}
|
\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
is required by the wishbone specification, and so
|
is required by the wishbone specification, and so
|
it is included here. The big thing to notice is that this ICAPE2 interface
|
it is included here. The big thing to notice is that this ICAPE2 interface
|
acts as a wishbone slave, and that all accesses to the ICAPE2 registers become
|
acts as a wishbone slave, and that all accesses to the ICAPE2 registers become
|
32--bit reads and writes to this interface. Bit ordering is the normal
|
32--bit reads and writes to this interface. Bit ordering is the normal
|
ordering where bit~31 is the most significant bit and so forth. (Bit reversal
|
ordering where bit~31 is the most significant bit and so forth. (Bit reversal
|
is accomplished internally to match Xilinx's definition.) The {\tt o\_stall}
|
is accomplished internally to match Xilinx's definition.) The {\tt o\_stall}
|
and {\tt o\_ack} lines are necessarily used to deal with the fact that
|
and {\tt o\_ack} lines are necessarily used to deal with the fact that
|
operations to the device take many clocks to complete (14 for writes, 21 for
|
operations to the device take many clocks to complete (14 for writes, 21 for
|
reads), so be prepared to wait a couple of clocks for your access to complete.
|
reads), so be prepared to wait a couple of clocks for your access to complete.
|
Further, the {\tt o\_ack} line will go high while the bus is stalled in many
|
Further, the {\tt o\_ack} line will go high while the bus is stalled in many
|
cases, indicating that the operation is complete but that the core is not
|
cases, indicating that the operation is complete but that the core is not
|
yet ready to handle a subsequent request.
|
yet ready to handle a subsequent request.
|
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\chapter{I/O Ports}\label{chap:ioports}
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\chapter{I/O Ports}\label{chap:ioports}
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This core offers no I/O ports beyond those of the wishbone discussed in
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This core offers no I/O ports beyond those of the wishbone discussed in
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Chapt.~\ref{chap:wishbone}. The I/O ports associated with the ICAPE2 interface
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Chapt.~\ref{chap:wishbone}. The I/O ports associated with the ICAPE2 interface
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are captured internally, and not brought to the output of this core.
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are captured internally, and not brought to the output of this core.
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% Appendices
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% Appendices
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% Index
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% Index
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\end{document}
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\end{document}
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