//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_4k_split.v
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// fm_4k_split.v
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//
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//
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// Abstract:
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// Abstract:
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// command split module by 4KB address boundary
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// command split module by 4KB address boundary
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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`include "polyphony_def.v"
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`include "polyphony_def.v"
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module fm_4k_split (
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module fm_4k_split (
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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// incoming
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// incoming
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i_brg_req,
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i_brg_req,
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i_brg_adrs,
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i_brg_adrs,
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i_brg_rw,
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i_brg_rw,
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i_brg_len,
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i_brg_len,
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o_brg_ack,
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o_brg_ack,
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// outgoing
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// outgoing
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o_brg_adrs,
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o_brg_adrs,
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o_brg_len,
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o_brg_len,
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i_brg_ack
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i_brg_ack
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);
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);
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`include "polyphony_axi_def.v"
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`include "polyphony_axi_def.v"
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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// system
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// system
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input clk_core;
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input clk_core;
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input rst_x;
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input rst_x;
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// incoming
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// incoming
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input i_brg_req;
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input i_brg_req;
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input [P_IB_ADDR_WIDTH-1:0]
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input [P_IB_ADDR_WIDTH-1:0]
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i_brg_adrs;
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i_brg_adrs;
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input i_brg_rw;
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input i_brg_rw;
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input [P_IB_LEN_WIDTH-1:0]
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input [P_IB_LEN_WIDTH-1:0]
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i_brg_len;
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i_brg_len;
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output o_brg_ack;
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output o_brg_ack;
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// outgoing
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// outgoing
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output [P_IB_ADDR_WIDTH-1:0]
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output [P_IB_ADDR_WIDTH-1:0]
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o_brg_adrs;
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o_brg_adrs;
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output [P_IB_LEN_WIDTH-1:0]
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output [P_IB_LEN_WIDTH-1:0]
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o_brg_len;
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o_brg_len;
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input i_brg_ack;
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input i_brg_ack;
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//////////////////////////////////
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//////////////////////////////////
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// parameter definition
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// parameter definition
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//////////////////////////////////
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//////////////////////////////////
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localparam P_IDLE = 1'b0;
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localparam P_IDLE = 1'b0;
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localparam P_2ND = 1'b1;
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localparam P_2ND = 1'b1;
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//////////////////////////////////
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//////////////////////////////////
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// reg
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// reg
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//////////////////////////////////
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//////////////////////////////////
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reg r_state;
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reg r_state;
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//////////////////////////////////
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//////////////////////////////////
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// wire
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// wire
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//////////////////////////////////
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//////////////////////////////////
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wire [P_IB_ADDR_WIDTH-1:0]
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wire [P_IB_ADDR_WIDTH-1:0]
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w_2nd_adrs;
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w_2nd_adrs;
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wire w_4k_boundary;
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wire w_4k_boundary;
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wire w_4k_ack;
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wire w_4k_ack;
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//////////////////////////////////
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//////////////////////////////////
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// assign
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// assign
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//////////////////////////////////
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//////////////////////////////////
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assign w_2nd_adrs = i_brg_adrs + 1'b1; // add 8byte address
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assign w_2nd_adrs = i_brg_adrs + 1'b1; // add 8byte address
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assign w_4k_boundary = (i_brg_adrs[P_IB_ADDR_WIDTH-1:(11-3)] !=
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assign w_4k_boundary = (i_brg_adrs[P_IB_ADDR_WIDTH-1:(11-3)] !=
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w_2nd_adrs[P_IB_ADDR_WIDTH-1:(11-3)]) & !i_brg_rw;
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w_2nd_adrs[P_IB_ADDR_WIDTH-1:(11-3)]) & !i_brg_rw;
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assign w_4k_ack = (r_state == P_2ND) & i_brg_ack ;
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assign w_4k_ack = (r_state == P_2ND) & i_brg_ack ;
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assign o_brg_adrs = (r_state == P_2ND) ? w_2nd_adrs : i_brg_adrs;
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assign o_brg_adrs = (r_state == P_2ND) ? w_2nd_adrs : i_brg_adrs;
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assign o_brg_ack = (!i_brg_req) ? i_brg_ack :
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assign o_brg_ack = (!i_brg_req) ? i_brg_ack :
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(w_4k_boundary) ? w_4k_ack : i_brg_ack;
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(w_4k_boundary) ? w_4k_ack : i_brg_ack;
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assign o_brg_len = (w_4k_boundary) ? 'd1 : i_brg_len;
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assign o_brg_len = (w_4k_boundary) ? 'd1 : i_brg_len;
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//////////////////////////////////
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//////////////////////////////////
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// always
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// always
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//////////////////////////////////
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//////////////////////////////////
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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end else begin
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end else begin
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case (r_state)
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case (r_state)
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P_IDLE: begin
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P_IDLE: begin
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if (i_brg_req & i_brg_ack) begin
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if (i_brg_req & i_brg_ack) begin
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if (w_4k_boundary) r_state <= P_2ND;
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if (w_4k_boundary) r_state <= P_2ND;
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end
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end
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end
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end
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P_2ND: begin
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P_2ND: begin
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if (i_brg_ack) begin
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if (i_brg_ack) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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