//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_mic_cnv.v
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// fm_mic_cnv.v
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//
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//
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// Abstract:
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// Abstract:
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// 32-64 bit data bus width conversion
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// 32-64 bit data bus width conversion
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2016, Kenji Ishimaru
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// Copyright (c) 2016, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_mic_cnv (
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module fm_mic_cnv (
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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// incoming
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// incoming
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i_req_in,
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i_req_in,
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i_wr_in,
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i_wr_in,
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i_adrs_in,
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i_adrs_in,
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i_len_in,
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i_len_in,
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o_ack_in,
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o_ack_in,
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i_be_in,
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i_be_in,
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i_wdata_in,
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i_wdata_in,
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o_rstr_in,
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o_rstr_in,
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o_rdata_in,
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o_rdata_in,
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// outcoming
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// outcoming
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o_req_out,
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o_req_out,
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o_wr_out,
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o_wr_out,
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o_adrs_out,
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o_adrs_out,
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o_len_out,
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o_len_out,
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i_ack_out,
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i_ack_out,
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o_be_out,
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o_be_out,
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o_wdata_out,
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o_wdata_out,
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i_rstr_out,
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i_rstr_out,
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i_rdata_out
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i_rdata_out
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);
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);
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`include "polyphony_params.v"
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`include "polyphony_params.v"
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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input clk_core;
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input clk_core;
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input rst_x;
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input rst_x;
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// incoming
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// incoming
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input i_req_in;
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input i_req_in;
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input i_wr_in;
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input i_wr_in;
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input [31:2] i_adrs_in;
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input [31:2] i_adrs_in;
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input [2:0] i_len_in;
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input [2:0] i_len_in;
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output o_ack_in;
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output o_ack_in;
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input [3:0] i_be_in;
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input [3:0] i_be_in;
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input [31:0] i_wdata_in;
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input [31:0] i_wdata_in;
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output o_rstr_in;
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output o_rstr_in;
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output [31:0] o_rdata_in;
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output [31:0] o_rdata_in;
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// outcoming
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// outcoming
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output o_req_out;
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output o_req_out;
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output o_wr_out;
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output o_wr_out;
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output [31:3] o_adrs_out;
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output [31:3] o_adrs_out;
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output [5:0] o_len_out;
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output [5:0] o_len_out;
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input i_ack_out;
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input i_ack_out;
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output [7:0] o_be_out;
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output [7:0] o_be_out;
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output [63:0] o_wdata_out;
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output [63:0] o_wdata_out;
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input i_rstr_out;
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input i_rstr_out;
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input [63:0] i_rdata_out;
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input [63:0] i_rdata_out;
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//////////////////////////////////
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//////////////////////////////////
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// regs
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// regs
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//////////////////////////////////
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//////////////////////////////////
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reg [2:0] r_cnt;
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reg [2:0] r_cnt;
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//////////////////////////////////
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//////////////////////////////////
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// wires
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// wires
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//////////////////////////////////
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//////////////////////////////////
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wire w_sel;
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wire w_sel;
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wire w_fifo_write;
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wire w_fifo_write;
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wire [3:0] w_fifo_din;
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wire [3:0] w_fifo_din;
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wire w_fifo_full;
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wire w_fifo_full;
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wire w_read_end;
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wire w_read_end;
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wire [3:0] w_fifo_dout;
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wire [3:0] w_fifo_dout;
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wire w_empty;
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wire w_empty;
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wire w_add_lsb;
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wire w_add_lsb;
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wire w_add_lsb_out;
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wire w_add_lsb_out;
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wire [2:0] w_len;
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wire [2:0] w_len;
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wire w_dread_end;
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wire w_dread_end;
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wire [63:0]w_dfifo_dout;
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wire [63:0]w_dfifo_dout;
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wire w_dempty;
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wire w_dempty;
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//////////////////////////////////
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//////////////////////////////////
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// assign statement
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// assign statement
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//////////////////////////////////
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//////////////////////////////////
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assign o_req_out = i_req_in;
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assign o_req_out = i_req_in;
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assign {o_adrs_out[31:3],w_add_lsb} = i_adrs_in[31:2];
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assign {o_adrs_out[31:3],w_add_lsb} = i_adrs_in[31:2];
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assign o_len_out = i_len_in[2:1] + i_len_in[0];
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assign o_len_out = i_len_in[2:1] + i_len_in[0];
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assign o_be_out = (w_add_lsb) ? {i_be_in,4'h0} : {4'h0,i_be_in};
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assign o_be_out = (w_add_lsb) ? {i_be_in,4'h0} : {4'h0,i_be_in};
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assign o_wdata_out = (w_add_lsb) ? {i_wdata_in,32'h0} : {32'h0,i_wdata_in};
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assign o_wdata_out = (w_add_lsb) ? {i_wdata_in,32'h0} : {32'h0,i_wdata_in};
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assign o_wr_out = i_wr_in;
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assign o_wr_out = i_wr_in;
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// command
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// command
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assign w_fifo_din = {w_add_lsb,i_len_in};
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assign w_fifo_din = {w_add_lsb,i_len_in};
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assign {w_add_lsb_out,w_len} = w_fifo_dout;
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assign {w_add_lsb_out,w_len} = w_fifo_dout;
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assign w_fifo_write = o_req_out & i_ack_out & (!i_wr_in);
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assign w_fifo_write = o_req_out & i_ack_out & (!i_wr_in);
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assign w_read_end = (!w_dempty) & (w_len == r_cnt);
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assign w_read_end = (!w_dempty) & (w_len == r_cnt);
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assign o_ack_in = i_ack_out & !w_fifo_full;
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assign o_ack_in = i_ack_out & !w_fifo_full;
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// data
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// data
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assign w_sel = (w_add_lsb_out) ? r_cnt[0] : ~r_cnt[0];
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assign w_sel = (w_add_lsb_out) ? r_cnt[0] : ~r_cnt[0];
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assign w_dread_end = w_sel | w_read_end;
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assign w_dread_end = w_sel | w_read_end;
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assign o_rstr_in = !w_dempty;
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assign o_rstr_in = !w_dempty;
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assign o_rdata_in = (w_sel) ? w_dfifo_dout[63:32] :w_dfifo_dout[31:0];
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assign o_rdata_in = (w_sel) ? w_dfifo_dout[63:32] :w_dfifo_dout[31:0];
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//////////////////////////////////
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//////////////////////////////////
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// module instantiation
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// module instantiation
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//////////////////////////////////
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//////////////////////////////////
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_cnt <= 'd1;
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r_cnt <= 'd1;
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end else begin
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end else begin
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if (!w_dempty) begin
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if (!w_dempty) begin
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if (w_len == r_cnt) r_cnt <= 'd1;
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if (w_len == r_cnt) r_cnt <= 'd1;
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else r_cnt <= r_cnt + 1'b1;
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else r_cnt <= r_cnt + 1'b1;
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end
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end
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end
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end
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end
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end
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// len, lsb
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// len, lsb
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fm_cmn_bfifo #(4,4) u_fifo (
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fm_cmn_bfifo #(4,4) u_fifo (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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.i_wstrobe(w_fifo_write),
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.i_wstrobe(w_fifo_write),
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.i_dt(w_fifo_din),
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.i_dt(w_fifo_din),
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.o_full(w_fifo_full),
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.o_full(w_fifo_full),
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.i_renable(w_read_end),
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.i_renable(w_read_end),
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.o_dt(w_fifo_dout),
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.o_dt(w_fifo_dout),
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.o_empty(w_empty),
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.o_empty(w_empty),
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.o_dnum()
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.o_dnum()
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);
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);
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fm_cmn_bfifo #(64,4) u_dfifo (
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fm_cmn_bfifo #(64,4) u_dfifo (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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.i_wstrobe(i_rstr_out),
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.i_wstrobe(i_rstr_out),
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.i_dt(i_rdata_out),
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.i_dt(i_rdata_out),
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.o_full(),
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.o_full(),
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.i_renable(w_dread_end),
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.i_renable(w_dread_end),
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.o_dt(w_dfifo_dout),
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.o_dt(w_dfifo_dout),
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.o_empty(w_dempty),
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.o_empty(w_dempty),
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.o_dnum()
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.o_dnum()
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);
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);
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endmodule
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endmodule
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