//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_port_unit.v
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// fm_port_unit.v
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//
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//
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// Abstract:
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// Abstract:
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// Memory Interconnect port module
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// Memory Interconnect port module
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2016, Kenji Ishimaru
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// Copyright (c) 2016, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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module fm_port_unit (
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module fm_port_unit (
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clk_core,
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clk_core,
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rst_x,
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rst_x,
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// port side
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// port side
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i_req,
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i_req,
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i_we,
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i_we,
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i_len,
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i_len,
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o_ack,
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o_ack,
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i_strw,
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i_strw,
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o_ackw,
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o_ackw,
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o_strr,
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o_strr,
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o_dbr,
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o_dbr,
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// internal
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// internal
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i_cack,
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i_cack,
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o_wdata_read_end,
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o_wdata_read_end,
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i_wdata_ack,
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i_wdata_ack,
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i_strr,
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i_strr,
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i_dbr
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i_dbr
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);
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);
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`include "polyphony_params.v"
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`include "polyphony_params.v"
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////////////////////////////
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////////////////////////////
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// Parameter definition
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// Parameter definition
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////////////////////////////
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////////////////////////////
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parameter P_SIDLE = 1'b0;
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parameter P_SIDLE = 1'b0;
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parameter P_SDOUT = 1'b1;
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parameter P_SDOUT = 1'b1;
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////////////////////////////
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////////////////////////////
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// I/O definitions
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// I/O definitions
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////////////////////////////
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////////////////////////////
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input i_req; // command request
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input i_req; // command request
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input i_we; // write enable
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input i_we; // write enable
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input [P_IB_LEN_WIDTH-1:0]
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input [P_IB_LEN_WIDTH-1:0]
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i_len; // burst length
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i_len; // burst length
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output o_ack; // command acknowledge
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output o_ack; // command acknowledge
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input i_strw; // write data strobe
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input i_strw; // write data strobe
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output o_ackw; // write data acknowledge
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output o_ackw; // write data acknowledge
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output o_strr; // read data strobe
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output o_strr; // read data strobe
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output [P_IB_DATA_WIDTH-1:0] o_dbr; // read data
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output [P_IB_DATA_WIDTH-1:0] o_dbr; // read data
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input i_cack; // command acknowledge
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input i_cack; // command acknowledge
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output o_wdata_read_end;// write data end
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output o_wdata_read_end;// write data end
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input i_wdata_ack; // write data acknowledge
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input i_wdata_ack; // write data acknowledge
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input i_strr; // read data strobe
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input i_strr; // read data strobe
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input [P_IB_DATA_WIDTH-1:0] i_dbr; // read data
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input [P_IB_DATA_WIDTH-1:0] i_dbr; // read data
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input clk_core; // system clock
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input clk_core; // system clock
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input rst_x; // system reset
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input rst_x; // system reset
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/////////////////////////
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/////////////////////////
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// register definition
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// register definition
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/////////////////////////
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/////////////////////////
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reg r_state;
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reg r_state;
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reg [P_IB_LEN_WIDTH-1:0]
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reg [P_IB_LEN_WIDTH-1:0]
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r_len;
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r_len;
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reg r_strr;
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reg r_strr;
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reg [P_IB_DATA_WIDTH-1:0]
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reg [P_IB_DATA_WIDTH-1:0]
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r_dbr;
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r_dbr;
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/////////////////////////
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/////////////////////////
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// wire definition
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// wire definition
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/////////////////////////
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/////////////////////////
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wire w_accept;
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wire w_accept;
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wire w_not_burst;
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wire w_not_burst;
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wire w_idle_state;
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wire w_idle_state;
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wire w_wdata_ack;
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wire w_wdata_ack;
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/////////////////////////
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/////////////////////////
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// assign statement
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// assign statement
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/////////////////////////
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/////////////////////////
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assign w_accept = i_req & i_cack & i_we;
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assign w_accept = i_req & i_cack & i_we;
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assign w_not_burst = !i_we | (i_len == 1);
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assign w_not_burst = !i_we | (i_len == 1);
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assign w_idle_state = (r_state == P_SIDLE);
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assign w_idle_state = (r_state == P_SIDLE);
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// output port connection
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// output port connection
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assign o_ack = (i_req) ? i_cack : 1'b1;
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assign o_ack = (i_req) ? i_cack : 1'b1;
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assign w_wdata_ack = (i_req) ? i_cack & i_wdata_ack : 1'b1;
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assign w_wdata_ack = (i_req) ? i_cack & i_wdata_ack : 1'b1;
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assign o_ackw = (w_idle_state) ? w_wdata_ack : i_wdata_ack;
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assign o_ackw = (w_idle_state) ? w_wdata_ack : i_wdata_ack;
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assign o_wdata_read_end = (w_idle_state) ? (i_strw & w_not_burst & i_wdata_ack) :
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assign o_wdata_read_end = (w_idle_state) ? (i_strw & w_not_burst & i_wdata_ack) :
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(i_strw & (r_len == 1) & i_wdata_ack);
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(i_strw & (r_len == 1) & i_wdata_ack);
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assign o_strr = r_strr;
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assign o_strr = r_strr;
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assign o_dbr = r_dbr;
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assign o_dbr = r_dbr;
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/////////////////////////
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/////////////////////////
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// always statement
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// always statement
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/////////////////////////
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/////////////////////////
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_state <= P_SIDLE;
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r_state <= P_SIDLE;
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end else begin
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end else begin
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case (r_state)
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case (r_state)
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P_SIDLE :
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P_SIDLE :
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begin
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begin
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if (w_accept & !w_not_burst) begin
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if (w_accept & !w_not_burst) begin
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r_state <= P_SDOUT;
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r_state <= P_SDOUT;
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end
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end
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end
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end
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P_SDOUT :
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P_SDOUT :
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begin
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begin
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if (o_wdata_read_end) begin
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if (o_wdata_read_end) begin
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r_state <= P_SIDLE;
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r_state <= P_SIDLE;
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end
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end
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end
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end
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default : r_state <= r_state;
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default : r_state <= r_state;
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endcase
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endcase
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end
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end
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end
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end
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// set input data
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// set input data
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_len <= 1;
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r_len <= 1;
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end else begin
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end else begin
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if (w_accept) begin
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if (w_accept) begin
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r_len <= i_len - 1'b1;
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r_len <= i_len - 1'b1;
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end else if (i_strw & i_wdata_ack) begin
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end else if (i_strw & i_wdata_ack) begin
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r_len <= r_len - 1'b1;
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r_len <= r_len - 1'b1;
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end
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end
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end
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end
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end
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end
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// read data
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// read data
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_strr <= 1'b0;
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r_strr <= 1'b0;
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end else begin
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end else begin
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r_strr <= i_strr;
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r_strr <= i_strr;
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end
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end
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end
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end
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always @(posedge clk_core) begin
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always @(posedge clk_core) begin
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r_dbr <= i_dbr;
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r_dbr <= i_dbr;
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end
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end
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endmodule
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endmodule
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