//=======================================================================
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//=======================================================================
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// Project Monophony
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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//
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// File:
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// File:
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// fm_avalon.v
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// fm_avalon.v
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//
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//
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// Abstract:
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// Abstract:
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// AVALON interface
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// AVALON interface
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (info.wf3d@gmail.com)
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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//
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//
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// -Redistributions of source code must retain the above copyright notice,
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// and/or other materials provided with the distribution.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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`include "fm_3d_define.v"
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`include "fm_3d_define.v"
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module fm_3d_wrapper (
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module fm_3d_wrapper (
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// system
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// system
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input clk_core,
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input clk_core,
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input rst_x,
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input rst_x,
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output o_int,
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output o_int,
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// avalon slave I/F
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// avalon slave I/F
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input [5:0] i_avs_adr,
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input [5:0] i_avs_adr,
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input [3:0] i_avs_be,
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input [3:0] i_avs_be,
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input i_avs_r,
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input i_avs_r,
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output [31:0] o_avs_rd,
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output [31:0] o_avs_rd,
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input i_avs_w,
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input i_avs_w,
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input [31:0] i_avs_wd,
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input [31:0] i_avs_wd,
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output o_avs_wait,
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output o_avs_wait,
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// avalon geometry DMA I/F
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// avalon geometry DMA I/F
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output [25:0] o_avm_adr,
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output [25:0] o_avm_adr,
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output [3:0] o_avm_be,
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output [3:0] o_avm_be,
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output [31:0] o_avm_wd,
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output [31:0] o_avm_wd,
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output [2:0] o_avm_blen,
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output [2:0] o_avm_blen,
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output o_avm_r,
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output o_avm_r,
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output o_avm_w,
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output o_avm_w,
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input i_avm_wait,
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input i_avm_wait,
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input i_avm_rvalid,
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input i_avm_rvalid,
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input [31:0] i_avm_rd
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input [31:0] i_avm_rd
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);
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);
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wire w_req;
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wire w_req;
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wire w_wr;
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wire w_wr;
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wire [5:0] w_adrs;
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wire [5:0] w_adrs;
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wire w_ack;
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wire w_ack;
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wire [3:0] w_be;
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wire [3:0] w_be;
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wire [31:0] w_wd;
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wire [31:0] w_wd;
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wire w_rstr;
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wire w_rstr;
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wire [31:0] w_rd;
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wire [31:0] w_rd;
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wire [3:0] w_avm_be;
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wire [3:0] w_avm_be;
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wire w_avm_ack;
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wire w_avm_ack;
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wire w_req_m;
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wire w_req_m;
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wire w_wr_m;
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wire w_wr_m;
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`ifdef D3D_WISHBONE
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`ifdef D3D_WISHBONE
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reg r_state;
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reg r_state;
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assign o_avm_r = w_req_m & (~w_wr_m) & (r_state == P_IDLE);
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assign o_avm_r = w_req_m & (~w_wr_m) & (r_state == P_IDLE);
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assign w_avm_ack = (r_state == P_READ) ? i_avm_rvalid :
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assign w_avm_ack = (r_state == P_READ) ? i_avm_rvalid :
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(!i_avm_wait & w_wr_m);
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(!i_avm_wait & w_wr_m);
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localparam P_IDLE = 1'b0;
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localparam P_IDLE = 1'b0;
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localparam P_READ = 1'b1;
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localparam P_READ = 1'b1;
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always @(posedge clk_core or negedge rst_x) begin
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always @(posedge clk_core or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_state <= P_IDLE;
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r_state <= P_IDLE;
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end else begin
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end else begin
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case (r_state)
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case (r_state)
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P_IDLE: if (w_req_m & !i_avm_wait & !w_wr_m) r_state <= P_READ;
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P_IDLE: if (w_req_m & !i_avm_wait & !w_wr_m) r_state <= P_READ;
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P_READ: if (i_avm_rvalid ) r_state <= P_IDLE;
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P_READ: if (i_avm_rvalid ) r_state <= P_IDLE;
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endcase
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endcase
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end
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end
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end
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end
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`else
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`else
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assign o_avm_r = w_req_m & (~w_wr_m);
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assign o_avm_r = w_req_m & (~w_wr_m);
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`endif
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`endif
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assign o_avm_w = w_req_m & (w_wr_m);
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assign o_avm_w = w_req_m & (w_wr_m);
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assign o_avm_be = (~w_wr_m) ? 4'hff: w_avm_be; // byte enable must be 'hff in read mode to get right data
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assign o_avm_be = (~w_wr_m) ? 4'hff: w_avm_be; // byte enable must be 'hff in read mode to get right data
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`ifdef D3D_WISHBONE
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`ifdef D3D_WISHBONE
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fm_avalon_wb #(.P_AVALON_ADR_WIDTH(6)) u_avalon_wb (
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fm_avalon_wb #(.P_AVALON_ADR_WIDTH(6)) u_avalon_wb (
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`else
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`else
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fm_avalon #(.P_AVALON_ADR_WIDTH(6)) u_avalon (
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fm_avalon #(.P_AVALON_ADR_WIDTH(6)) u_avalon (
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`endif
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`endif
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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// AVALON slave bus
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// AVALON slave bus
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.i_av_adr(i_avs_adr),
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.i_av_adr(i_avs_adr),
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.i_av_be(i_avs_be),
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.i_av_be(i_avs_be),
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.i_av_r(i_avs_r),
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.i_av_r(i_avs_r),
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.o_av_rd(o_avs_rd),
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.o_av_rd(o_avs_rd),
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.i_av_w(i_avs_w),
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.i_av_w(i_avs_w),
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.i_av_wd(i_avs_wd),
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.i_av_wd(i_avs_wd),
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.o_av_wait(o_avs_wait),
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.o_av_wait(o_avs_wait),
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// internal side
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// internal side
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.o_req(w_req),
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.o_req(w_req),
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.o_wr(w_wr),
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.o_wr(w_wr),
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.o_adrs(w_adrs),
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.o_adrs(w_adrs),
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.i_ack(w_ack),
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.i_ack(w_ack),
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.o_be(w_be),
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.o_be(w_be),
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.o_wd(w_wd),
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.o_wd(w_wd),
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`ifdef D3D_WISHBONE
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`ifdef D3D_WISHBONE
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`else
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`else
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.i_rstr(w_rstr),
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.i_rstr(w_rstr),
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`endif
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`endif
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.i_rd(w_rd)
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.i_rd(w_rd)
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);
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);
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`ifdef D3D_WISHBONE
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`ifdef D3D_WISHBONE
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assign o_avm_blen = 3'd1;
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assign o_avm_blen = 3'd1;
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wire [25:2] w_avm_adr_t;
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wire [25:2] w_avm_adr_t;
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assign o_avm_adr = {w_avm_adr_t,2'b00};
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assign o_avm_adr = {w_avm_adr_t,2'b00};
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`endif
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`endif
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fm_3d_core u_3d_core (
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fm_3d_core u_3d_core (
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.clk_i(clk_core),
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.clk_i(clk_core),
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.rst_i(~rst_x),
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.rst_i(~rst_x),
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.int_o(o_int),
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.int_o(o_int),
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`ifdef D3D_WISHBONE
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`ifdef D3D_WISHBONE
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// internal side
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// internal side
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.s_wb_stb_i(w_req),
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.s_wb_stb_i(w_req),
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.s_wb_we_i(w_wr),
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.s_wb_we_i(w_wr),
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.s_wb_adr_i(w_adrs),
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.s_wb_adr_i(w_adrs),
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.s_wb_ack_o(w_ack),
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.s_wb_ack_o(w_ack),
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.s_wb_sel_i(w_be),
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.s_wb_sel_i(w_be),
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.s_wb_dat_i(w_wd),
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.s_wb_dat_i(w_wd),
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.s_wb_dat_o(w_rd),
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.s_wb_dat_o(w_rd),
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// geometry DMA, pixel write
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// geometry DMA, pixel write
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.m_wb_stb_o(w_req_m),
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.m_wb_stb_o(w_req_m),
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.m_wb_we_o(w_wr_m),
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.m_wb_we_o(w_wr_m),
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.m_wb_adr_o(w_avm_adr_t),
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.m_wb_adr_o(w_avm_adr_t),
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.m_wb_ack_i(w_avm_ack),
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.m_wb_ack_i(w_avm_ack),
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.m_wb_sel_o(w_avm_be),
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.m_wb_sel_o(w_avm_be),
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.m_wb_dat_o(o_avm_wd),
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.m_wb_dat_o(o_avm_wd),
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.m_wb_dat_i(i_avm_rd),
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.m_wb_dat_i(i_avm_rd),
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`else
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`else
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// internal side
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// internal side
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.i_req_s(w_req),
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.i_req_s(w_req),
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.i_wr_s(w_wr),
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.i_wr_s(w_wr),
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.i_adrs_s({w_adrs,2'b0}),
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.i_adrs_s({w_adrs,2'b0}),
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.o_ack_s(w_ack),
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.o_ack_s(w_ack),
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.i_be_s(w_be),
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.i_be_s(w_be),
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.i_dbw_s(w_wd),
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.i_dbw_s(w_wd),
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.o_strr_s(w_rstr),
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.o_strr_s(w_rstr),
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.o_dbr_s(w_rd),
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.o_dbr_s(w_rd),
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// geometry DMA, pixel write
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// geometry DMA, pixel write
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.o_req_m(w_req_m),
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.o_req_m(w_req_m),
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.o_wr_m(w_wr_m),
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.o_wr_m(w_wr_m),
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.o_adrs_m(o_avm_adr),
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.o_adrs_m(o_avm_adr),
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.o_len_m(o_avm_blen),
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.o_len_m(o_avm_blen),
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.i_ack_m(!i_avm_wait),
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.i_ack_m(!i_avm_wait),
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.o_be_m(w_avm_be),
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.o_be_m(w_avm_be),
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.o_dbw_m(o_avm_wd),
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.o_dbw_m(o_avm_wd),
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.i_strr_m(i_avm_rvalid),
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.i_strr_m(i_avm_rvalid),
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.i_dbr_m(i_avm_rd)
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.i_dbr_m(i_avm_rd)
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`endif
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`endif
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);
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);
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endmodule
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endmodule
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